1 /***************************************************************************
2 * Copyright (C) 2006, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2009 Michael Schwingen *
9 * michael@schwingen.org *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
30 #include "breakpoints.h"
32 #include "target_type.h"
34 #include "arm_simulator.h"
35 #include "arm_disassembler.h"
36 #include "time_support.h"
42 * Important XScale documents available as of October 2009 include:
44 * Intel XScale® Core Developer’s Manual, January 2004
45 * Order Number: 273473-002
46 * This has a chapter detailing debug facilities, and punts some
47 * details to chip-specific microarchitecture documents.
49 * Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
50 * Document Number: 273539-005
51 * Less detailed than the developer's manual, but summarizes those
52 * missing details (for most XScales) and gives LOTS of notes about
53 * debugger/handler interaction issues. Presents a simpler reset
54 * and load-handler sequence than the arch doc. (Note, OpenOCD
55 * doesn't currently support "Hot-Debug" as defined there.)
57 * Chip-specific microarchitecture documents may also be useful.
61 /* forward declarations */
62 static int xscale_resume(struct target
*, int current
,
63 uint32_t address
, int handle_breakpoints
, int debug_execution
);
64 static int xscale_debug_entry(struct target
*);
65 static int xscale_restore_context(struct target
*);
66 static int xscale_get_reg(struct reg
*reg
);
67 static int xscale_set_reg(struct reg
*reg
, uint8_t *buf
);
68 static int xscale_set_breakpoint(struct target
*, struct breakpoint
*);
69 static int xscale_set_watchpoint(struct target
*, struct watchpoint
*);
70 static int xscale_unset_breakpoint(struct target
*, struct breakpoint
*);
71 static int xscale_read_trace(struct target
*);
74 /* This XScale "debug handler" is loaded into the processor's
75 * mini-ICache, which is 2K of code writable only via JTAG.
77 * FIXME the OpenOCD "bin2char" utility currently doesn't handle
78 * binary files cleanly. It's string oriented, and terminates them
79 * with a NUL character. Better would be to generate the constants
80 * and let other code decide names, scoping, and other housekeeping.
82 static /* unsigned const char xscale_debug_handler[] = ... */
83 #include "xscale_debug.h"
85 static char *const xscale_reg_list
[] =
87 "XSCALE_MAINID", /* 0 */
97 "XSCALE_IBCR0", /* 10 */
107 "XSCALE_RX", /* 20 */
111 static const struct xscale_reg xscale_reg_arch_info
[] =
113 {XSCALE_MAINID
, NULL
},
114 {XSCALE_CACHETYPE
, NULL
},
116 {XSCALE_AUXCTRL
, NULL
},
122 {XSCALE_CPACCESS
, NULL
},
123 {XSCALE_IBCR0
, NULL
},
124 {XSCALE_IBCR1
, NULL
},
127 {XSCALE_DBCON
, NULL
},
128 {XSCALE_TBREG
, NULL
},
129 {XSCALE_CHKPT0
, NULL
},
130 {XSCALE_CHKPT1
, NULL
},
131 {XSCALE_DCSR
, NULL
}, /* DCSR accessed via JTAG or SW */
132 {-1, NULL
}, /* TX accessed via JTAG */
133 {-1, NULL
}, /* RX accessed via JTAG */
134 {-1, NULL
}, /* TXRXCTRL implicit access via JTAG */
137 /* convenience wrapper to access XScale specific registers */
138 static int xscale_set_reg_u32(struct reg
*reg
, uint32_t value
)
142 buf_set_u32(buf
, 0, 32, value
);
144 return xscale_set_reg(reg
, buf
);
147 static const char xscale_not
[] = "target is not an XScale";
149 static int xscale_verify_pointer(struct command_context
*cmd_ctx
,
150 struct xscale_common
*xscale
)
152 if (xscale
->common_magic
!= XSCALE_COMMON_MAGIC
) {
153 command_print(cmd_ctx
, xscale_not
);
154 return ERROR_TARGET_INVALID
;
159 static int xscale_jtag_set_instr(struct jtag_tap
*tap
, uint32_t new_instr
)
164 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) != new_instr
)
166 struct scan_field field
;
169 memset(&field
, 0, sizeof field
);
171 field
.num_bits
= tap
->ir_length
;
172 field
.out_value
= scratch
;
173 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_instr
);
175 jtag_add_ir_scan(1, &field
, jtag_get_end_state());
181 static int xscale_read_dcsr(struct target
*target
)
183 struct xscale_common
*xscale
= target_to_xscale(target
);
185 struct scan_field fields
[3];
186 uint8_t field0
= 0x0;
187 uint8_t field0_check_value
= 0x2;
188 uint8_t field0_check_mask
= 0x7;
189 uint8_t field2
= 0x0;
190 uint8_t field2_check_value
= 0x0;
191 uint8_t field2_check_mask
= 0x1;
193 jtag_set_end_state(TAP_DRPAUSE
);
194 xscale_jtag_set_instr(target
->tap
, XSCALE_SELDCSR
);
196 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
197 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
199 memset(&fields
, 0, sizeof fields
);
201 fields
[0].tap
= target
->tap
;
202 fields
[0].num_bits
= 3;
203 fields
[0].out_value
= &field0
;
205 fields
[0].in_value
= &tmp
;
207 fields
[1].tap
= target
->tap
;
208 fields
[1].num_bits
= 32;
209 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
211 fields
[2].tap
= target
->tap
;
212 fields
[2].num_bits
= 1;
213 fields
[2].out_value
= &field2
;
215 fields
[2].in_value
= &tmp2
;
217 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
219 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
220 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
222 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
224 LOG_ERROR("JTAG error while reading DCSR");
228 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
229 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
231 /* write the register with the value we just read
232 * on this second pass, only the first bit of field0 is guaranteed to be 0)
234 field0_check_mask
= 0x1;
235 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
236 fields
[1].in_value
= NULL
;
238 jtag_set_end_state(TAP_IDLE
);
240 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
242 /* DANGER!!! this must be here. It will make sure that the arguments
243 * to jtag_set_check_value() does not go out of scope! */
244 return jtag_execute_queue();
248 static void xscale_getbuf(jtag_callback_data_t arg
)
250 uint8_t *in
= (uint8_t *)arg
;
251 *((uint32_t *)in
) = buf_get_u32(in
, 0, 32);
254 static int xscale_receive(struct target
*target
, uint32_t *buffer
, int num_words
)
257 return ERROR_INVALID_ARGUMENTS
;
259 int retval
= ERROR_OK
;
261 struct scan_field fields
[3];
262 uint8_t *field0
= malloc(num_words
* 1);
263 uint8_t field0_check_value
= 0x2;
264 uint8_t field0_check_mask
= 0x6;
265 uint32_t *field1
= malloc(num_words
* 4);
266 uint8_t field2_check_value
= 0x0;
267 uint8_t field2_check_mask
= 0x1;
269 int words_scheduled
= 0;
272 path
[0] = TAP_DRSELECT
;
273 path
[1] = TAP_DRCAPTURE
;
274 path
[2] = TAP_DRSHIFT
;
276 memset(&fields
, 0, sizeof fields
);
278 fields
[0].tap
= target
->tap
;
279 fields
[0].num_bits
= 3;
280 fields
[0].check_value
= &field0_check_value
;
281 fields
[0].check_mask
= &field0_check_mask
;
283 fields
[1].tap
= target
->tap
;
284 fields
[1].num_bits
= 32;
286 fields
[2].tap
= target
->tap
;
287 fields
[2].num_bits
= 1;
288 fields
[2].check_value
= &field2_check_value
;
289 fields
[2].check_mask
= &field2_check_mask
;
291 jtag_set_end_state(TAP_IDLE
);
292 xscale_jtag_set_instr(target
->tap
, XSCALE_DBGTX
);
293 jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
295 /* repeat until all words have been collected */
297 while (words_done
< num_words
)
301 for (i
= words_done
; i
< num_words
; i
++)
303 fields
[0].in_value
= &field0
[i
];
305 jtag_add_pathmove(3, path
);
307 fields
[1].in_value
= (uint8_t *)(field1
+ i
);
309 jtag_add_dr_scan_check(3, fields
, jtag_set_end_state(TAP_IDLE
));
311 jtag_add_callback(xscale_getbuf
, (jtag_callback_data_t
)(field1
+ i
));
316 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
318 LOG_ERROR("JTAG error while receiving data from debug handler");
322 /* examine results */
323 for (i
= words_done
; i
< num_words
; i
++)
325 if (!(field0
[0] & 1))
327 /* move backwards if necessary */
329 for (j
= i
; j
< num_words
- 1; j
++)
331 field0
[j
] = field0
[j
+ 1];
332 field1
[j
] = field1
[j
+ 1];
337 if (words_scheduled
== 0)
339 if (attempts
++==1000)
341 LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts");
342 retval
= ERROR_TARGET_TIMEOUT
;
347 words_done
+= words_scheduled
;
350 for (i
= 0; i
< num_words
; i
++)
351 *(buffer
++) = buf_get_u32((uint8_t*)&field1
[i
], 0, 32);
358 static int xscale_read_tx(struct target
*target
, int consume
)
360 struct xscale_common
*xscale
= target_to_xscale(target
);
362 tap_state_t noconsume_path
[6];
364 struct timeval timeout
, now
;
365 struct scan_field fields
[3];
366 uint8_t field0_in
= 0x0;
367 uint8_t field0_check_value
= 0x2;
368 uint8_t field0_check_mask
= 0x6;
369 uint8_t field2_check_value
= 0x0;
370 uint8_t field2_check_mask
= 0x1;
372 jtag_set_end_state(TAP_IDLE
);
374 xscale_jtag_set_instr(target
->tap
, XSCALE_DBGTX
);
376 path
[0] = TAP_DRSELECT
;
377 path
[1] = TAP_DRCAPTURE
;
378 path
[2] = TAP_DRSHIFT
;
380 noconsume_path
[0] = TAP_DRSELECT
;
381 noconsume_path
[1] = TAP_DRCAPTURE
;
382 noconsume_path
[2] = TAP_DREXIT1
;
383 noconsume_path
[3] = TAP_DRPAUSE
;
384 noconsume_path
[4] = TAP_DREXIT2
;
385 noconsume_path
[5] = TAP_DRSHIFT
;
387 memset(&fields
, 0, sizeof fields
);
389 fields
[0].tap
= target
->tap
;
390 fields
[0].num_bits
= 3;
391 fields
[0].in_value
= &field0_in
;
393 fields
[1].tap
= target
->tap
;
394 fields
[1].num_bits
= 32;
395 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
;
397 fields
[2].tap
= target
->tap
;
398 fields
[2].num_bits
= 1;
400 fields
[2].in_value
= &tmp
;
402 gettimeofday(&timeout
, NULL
);
403 timeval_add_time(&timeout
, 1, 0);
407 /* if we want to consume the register content (i.e. clear TX_READY),
408 * we have to go straight from Capture-DR to Shift-DR
409 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
412 jtag_add_pathmove(3, path
);
415 jtag_add_pathmove(sizeof(noconsume_path
)/sizeof(*noconsume_path
), noconsume_path
);
418 jtag_add_dr_scan(3, fields
, jtag_set_end_state(TAP_IDLE
));
420 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
421 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
423 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
425 LOG_ERROR("JTAG error while reading TX");
426 return ERROR_TARGET_TIMEOUT
;
429 gettimeofday(&now
, NULL
);
430 if ((now
.tv_sec
> timeout
.tv_sec
) || ((now
.tv_sec
== timeout
.tv_sec
)&& (now
.tv_usec
> timeout
.tv_usec
)))
432 LOG_ERROR("time out reading TX register");
433 return ERROR_TARGET_TIMEOUT
;
435 if (!((!(field0_in
& 1)) && consume
))
439 if (debug_level
>= 3)
441 LOG_DEBUG("waiting 100ms");
442 alive_sleep(100); /* avoid flooding the logs */
450 if (!(field0_in
& 1))
451 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
456 static int xscale_write_rx(struct target
*target
)
458 struct xscale_common
*xscale
= target_to_xscale(target
);
460 struct timeval timeout
, now
;
461 struct scan_field fields
[3];
462 uint8_t field0_out
= 0x0;
463 uint8_t field0_in
= 0x0;
464 uint8_t field0_check_value
= 0x2;
465 uint8_t field0_check_mask
= 0x6;
466 uint8_t field2
= 0x0;
467 uint8_t field2_check_value
= 0x0;
468 uint8_t field2_check_mask
= 0x1;
470 jtag_set_end_state(TAP_IDLE
);
472 xscale_jtag_set_instr(target
->tap
, XSCALE_DBGRX
);
474 memset(&fields
, 0, sizeof fields
);
476 fields
[0].tap
= target
->tap
;
477 fields
[0].num_bits
= 3;
478 fields
[0].out_value
= &field0_out
;
479 fields
[0].in_value
= &field0_in
;
481 fields
[1].tap
= target
->tap
;
482 fields
[1].num_bits
= 32;
483 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
;
485 fields
[2].tap
= target
->tap
;
486 fields
[2].num_bits
= 1;
487 fields
[2].out_value
= &field2
;
489 fields
[2].in_value
= &tmp
;
491 gettimeofday(&timeout
, NULL
);
492 timeval_add_time(&timeout
, 1, 0);
494 /* poll until rx_read is low */
495 LOG_DEBUG("polling RX");
498 jtag_add_dr_scan(3, fields
, jtag_set_end_state(TAP_IDLE
));
500 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
501 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
503 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
505 LOG_ERROR("JTAG error while writing RX");
509 gettimeofday(&now
, NULL
);
510 if ((now
.tv_sec
> timeout
.tv_sec
) || ((now
.tv_sec
== timeout
.tv_sec
)&& (now
.tv_usec
> timeout
.tv_usec
)))
512 LOG_ERROR("time out writing RX register");
513 return ERROR_TARGET_TIMEOUT
;
515 if (!(field0_in
& 1))
517 if (debug_level
>= 3)
519 LOG_DEBUG("waiting 100ms");
520 alive_sleep(100); /* avoid flooding the logs */
530 jtag_add_dr_scan(3, fields
, jtag_set_end_state(TAP_IDLE
));
532 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
534 LOG_ERROR("JTAG error while writing RX");
541 /* send count elements of size byte to the debug handler */
542 static int xscale_send(struct target
*target
, uint8_t *buffer
, int count
, int size
)
549 jtag_set_end_state(TAP_IDLE
);
551 xscale_jtag_set_instr(target
->tap
, XSCALE_DBGRX
);
558 int endianness
= target
->endianness
;
559 while (done_count
++ < count
)
564 if (endianness
== TARGET_LITTLE_ENDIAN
)
566 t
[1]=le_to_h_u32(buffer
);
569 t
[1]=be_to_h_u32(buffer
);
573 if (endianness
== TARGET_LITTLE_ENDIAN
)
575 t
[1]=le_to_h_u16(buffer
);
578 t
[1]=be_to_h_u16(buffer
);
585 LOG_ERROR("BUG: size neither 4, 2 nor 1");
586 return ERROR_INVALID_ARGUMENTS
;
588 jtag_add_dr_out(target
->tap
,
592 jtag_set_end_state(TAP_IDLE
));
596 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
598 LOG_ERROR("JTAG error while sending data to debug handler");
605 static int xscale_send_u32(struct target
*target
, uint32_t value
)
607 struct xscale_common
*xscale
= target_to_xscale(target
);
609 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
610 return xscale_write_rx(target
);
613 static int xscale_write_dcsr(struct target
*target
, int hold_rst
, int ext_dbg_brk
)
615 struct xscale_common
*xscale
= target_to_xscale(target
);
617 struct scan_field fields
[3];
618 uint8_t field0
= 0x0;
619 uint8_t field0_check_value
= 0x2;
620 uint8_t field0_check_mask
= 0x7;
621 uint8_t field2
= 0x0;
622 uint8_t field2_check_value
= 0x0;
623 uint8_t field2_check_mask
= 0x1;
626 xscale
->hold_rst
= hold_rst
;
628 if (ext_dbg_brk
!= -1)
629 xscale
->external_debug_break
= ext_dbg_brk
;
631 jtag_set_end_state(TAP_IDLE
);
632 xscale_jtag_set_instr(target
->tap
, XSCALE_SELDCSR
);
634 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
635 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
637 memset(&fields
, 0, sizeof fields
);
639 fields
[0].tap
= target
->tap
;
640 fields
[0].num_bits
= 3;
641 fields
[0].out_value
= &field0
;
643 fields
[0].in_value
= &tmp
;
645 fields
[1].tap
= target
->tap
;
646 fields
[1].num_bits
= 32;
647 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
649 fields
[2].tap
= target
->tap
;
650 fields
[2].num_bits
= 1;
651 fields
[2].out_value
= &field2
;
653 fields
[2].in_value
= &tmp2
;
655 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
657 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
658 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
660 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
662 LOG_ERROR("JTAG error while writing DCSR");
666 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
667 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
672 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
673 static unsigned int parity (unsigned int v
)
675 // unsigned int ov = v;
680 // LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
681 return (0x6996 >> v
) & 1;
684 static int xscale_load_ic(struct target
*target
, uint32_t va
, uint32_t buffer
[8])
689 struct scan_field fields
[2];
691 LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32
"", va
);
694 jtag_set_end_state(TAP_IDLE
);
695 xscale_jtag_set_instr(target
->tap
, XSCALE_LDIC
);
697 /* CMD is b011 to load a cacheline into the Mini ICache.
698 * Loading into the main ICache is deprecated, and unused.
699 * It's followed by three zero bits, and 27 address bits.
701 buf_set_u32(&cmd
, 0, 6, 0x3);
703 /* virtual address of desired cache line */
704 buf_set_u32(packet
, 0, 27, va
>> 5);
706 memset(&fields
, 0, sizeof fields
);
708 fields
[0].tap
= target
->tap
;
709 fields
[0].num_bits
= 6;
710 fields
[0].out_value
= &cmd
;
712 fields
[1].tap
= target
->tap
;
713 fields
[1].num_bits
= 27;
714 fields
[1].out_value
= packet
;
716 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
718 /* rest of packet is a cacheline: 8 instructions, with parity */
719 fields
[0].num_bits
= 32;
720 fields
[0].out_value
= packet
;
722 fields
[1].num_bits
= 1;
723 fields
[1].out_value
= &cmd
;
725 for (word
= 0; word
< 8; word
++)
727 buf_set_u32(packet
, 0, 32, buffer
[word
]);
730 memcpy(&value
, packet
, sizeof(uint32_t));
733 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
736 return jtag_execute_queue();
739 static int xscale_invalidate_ic_line(struct target
*target
, uint32_t va
)
743 struct scan_field fields
[2];
745 jtag_set_end_state(TAP_IDLE
);
746 xscale_jtag_set_instr(target
->tap
, XSCALE_LDIC
);
748 /* CMD for invalidate IC line b000, bits [6:4] b000 */
749 buf_set_u32(&cmd
, 0, 6, 0x0);
751 /* virtual address of desired cache line */
752 buf_set_u32(packet
, 0, 27, va
>> 5);
754 memset(&fields
, 0, sizeof fields
);
756 fields
[0].tap
= target
->tap
;
757 fields
[0].num_bits
= 6;
758 fields
[0].out_value
= &cmd
;
760 fields
[1].tap
= target
->tap
;
761 fields
[1].num_bits
= 27;
762 fields
[1].out_value
= packet
;
764 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
769 static int xscale_update_vectors(struct target
*target
)
771 struct xscale_common
*xscale
= target_to_xscale(target
);
775 uint32_t low_reset_branch
, high_reset_branch
;
777 for (i
= 1; i
< 8; i
++)
779 /* if there's a static vector specified for this exception, override */
780 if (xscale
->static_high_vectors_set
& (1 << i
))
782 xscale
->high_vectors
[i
] = xscale
->static_high_vectors
[i
];
786 retval
= target_read_u32(target
, 0xffff0000 + 4*i
, &xscale
->high_vectors
[i
]);
787 if (retval
== ERROR_TARGET_TIMEOUT
)
789 if (retval
!= ERROR_OK
)
791 /* Some of these reads will fail as part of normal execution */
792 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
797 for (i
= 1; i
< 8; i
++)
799 if (xscale
->static_low_vectors_set
& (1 << i
))
801 xscale
->low_vectors
[i
] = xscale
->static_low_vectors
[i
];
805 retval
= target_read_u32(target
, 0x0 + 4*i
, &xscale
->low_vectors
[i
]);
806 if (retval
== ERROR_TARGET_TIMEOUT
)
808 if (retval
!= ERROR_OK
)
810 /* Some of these reads will fail as part of normal execution */
811 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
816 /* calculate branches to debug handler */
817 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
818 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
820 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
821 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
823 /* invalidate and load exception vectors in mini i-cache */
824 xscale_invalidate_ic_line(target
, 0x0);
825 xscale_invalidate_ic_line(target
, 0xffff0000);
827 xscale_load_ic(target
, 0x0, xscale
->low_vectors
);
828 xscale_load_ic(target
, 0xffff0000, xscale
->high_vectors
);
833 static int xscale_arch_state(struct target
*target
)
835 struct xscale_common
*xscale
= target_to_xscale(target
);
836 struct armv4_5_common_s
*armv4_5
= &xscale
->armv4_5_common
;
838 static const char *state
[] =
840 "disabled", "enabled"
843 static const char *arch_dbg_reason
[] =
845 "", "\n(processor reset)", "\n(trace buffer full)"
848 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
850 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
851 return ERROR_INVALID_ARGUMENTS
;
854 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
855 "cpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"\n"
856 "MMU: %s, D-Cache: %s, I-Cache: %s"
858 armv4_5_state_strings
[armv4_5
->core_state
],
859 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
860 arm_mode_name(armv4_5
->core_mode
),
861 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
862 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
863 state
[xscale
->armv4_5_mmu
.mmu_enabled
],
864 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
865 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
],
866 arch_dbg_reason
[xscale
->arch_debug_reason
]);
871 static int xscale_poll(struct target
*target
)
873 int retval
= ERROR_OK
;
875 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_DEBUG_RUNNING
))
877 enum target_state previous_state
= target
->state
;
878 if ((retval
= xscale_read_tx(target
, 0)) == ERROR_OK
)
881 /* there's data to read from the tx register, we entered debug state */
882 target
->state
= TARGET_HALTED
;
884 /* process debug entry, fetching current mode regs */
885 retval
= xscale_debug_entry(target
);
887 else if (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
889 LOG_USER("error while polling TX register, reset CPU");
890 /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
891 target
->state
= TARGET_HALTED
;
894 /* debug_entry could have overwritten target state (i.e. immediate resume)
895 * don't signal event handlers in that case
897 if (target
->state
!= TARGET_HALTED
)
900 /* if target was running, signal that we halted
901 * otherwise we reentered from debug execution */
902 if (previous_state
== TARGET_RUNNING
)
903 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
905 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
911 static int xscale_debug_entry(struct target
*target
)
913 struct xscale_common
*xscale
= target_to_xscale(target
);
914 struct armv4_5_common_s
*armv4_5
= &xscale
->armv4_5_common
;
921 /* clear external dbg break (will be written on next DCSR read) */
922 xscale
->external_debug_break
= 0;
923 if ((retval
= xscale_read_dcsr(target
)) != ERROR_OK
)
926 /* get r0, pc, r1 to r7 and cpsr */
927 if ((retval
= xscale_receive(target
, buffer
, 10)) != ERROR_OK
)
930 /* move r0 from buffer to register cache */
931 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, buffer
[0]);
932 armv4_5
->core_cache
->reg_list
[0].dirty
= 1;
933 armv4_5
->core_cache
->reg_list
[0].valid
= 1;
934 LOG_DEBUG("r0: 0x%8.8" PRIx32
"", buffer
[0]);
936 /* move pc from buffer to register cache */
937 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, buffer
[1]);
938 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
939 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
940 LOG_DEBUG("pc: 0x%8.8" PRIx32
"", buffer
[1]);
942 /* move data from buffer to register cache */
943 for (i
= 1; i
<= 7; i
++)
945 buf_set_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32, buffer
[1 + i
]);
946 armv4_5
->core_cache
->reg_list
[i
].dirty
= 1;
947 armv4_5
->core_cache
->reg_list
[i
].valid
= 1;
948 LOG_DEBUG("r%i: 0x%8.8" PRIx32
"", i
, buffer
[i
+ 1]);
951 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32, buffer
[9]);
952 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
953 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
954 LOG_DEBUG("cpsr: 0x%8.8" PRIx32
"", buffer
[9]);
956 armv4_5
->core_mode
= buffer
[9] & 0x1f;
957 if (!is_arm_mode(armv4_5
->core_mode
))
959 target
->state
= TARGET_UNKNOWN
;
960 LOG_ERROR("cpsr contains invalid mode value - communication failure");
961 return ERROR_TARGET_FAILURE
;
963 LOG_DEBUG("target entered debug state in %s mode",
964 arm_mode_name(armv4_5
->core_mode
));
966 if (buffer
[9] & 0x20)
967 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
969 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
972 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
973 if ((armv4_5
->core_mode
!= ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_SYS
))
975 xscale_receive(target
, buffer
, 8);
976 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
977 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).dirty
= 0;
978 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).valid
= 1;
982 /* r8 to r14, but no spsr */
983 xscale_receive(target
, buffer
, 7);
986 /* move data from buffer to register cache */
987 for (i
= 8; i
<= 14; i
++)
989 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, buffer
[i
- 8]);
990 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 0;
991 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
994 /* examine debug reason */
995 xscale_read_dcsr(target
);
996 moe
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 2, 3);
998 /* stored PC (for calculating fixup) */
999 pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1003 case 0x0: /* Processor reset */
1004 target
->debug_reason
= DBG_REASON_DBGRQ
;
1005 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_RESET
;
1008 case 0x1: /* Instruction breakpoint hit */
1009 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1010 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1013 case 0x2: /* Data breakpoint hit */
1014 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1015 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1018 case 0x3: /* BKPT instruction executed */
1019 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1020 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1023 case 0x4: /* Ext. debug event */
1024 target
->debug_reason
= DBG_REASON_DBGRQ
;
1025 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1028 case 0x5: /* Vector trap occured */
1029 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1030 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1033 case 0x6: /* Trace buffer full break */
1034 target
->debug_reason
= DBG_REASON_DBGRQ
;
1035 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_TB_FULL
;
1038 case 0x7: /* Reserved (may flag Hot-Debug support) */
1040 LOG_ERROR("Method of Entry is 'Reserved'");
1045 /* apply PC fixup */
1046 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, pc
);
1048 /* on the first debug entry, identify cache type */
1049 if (xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
1051 uint32_t cache_type_reg
;
1053 /* read cp15 cache type register */
1054 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
]);
1055 cache_type_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
].value
, 0, 32);
1057 armv4_5_identify_cache(cache_type_reg
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
1060 /* examine MMU and Cache settings */
1061 /* read cp15 control register */
1062 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
1063 xscale
->cp15_control_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
1064 xscale
->armv4_5_mmu
.mmu_enabled
= (xscale
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1065 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (xscale
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1066 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (xscale
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1068 /* tracing enabled, read collected trace data */
1069 if (xscale
->trace
.buffer_enabled
)
1071 xscale_read_trace(target
);
1072 xscale
->trace
.buffer_fill
--;
1074 /* resume if we're still collecting trace data */
1075 if ((xscale
->arch_debug_reason
== XSCALE_DBG_REASON_TB_FULL
)
1076 && (xscale
->trace
.buffer_fill
> 0))
1078 xscale_resume(target
, 1, 0x0, 1, 0);
1082 xscale
->trace
.buffer_enabled
= 0;
1089 static int xscale_halt(struct target
*target
)
1091 struct xscale_common
*xscale
= target_to_xscale(target
);
1093 LOG_DEBUG("target->state: %s",
1094 target_state_name(target
));
1096 if (target
->state
== TARGET_HALTED
)
1098 LOG_DEBUG("target was already halted");
1101 else if (target
->state
== TARGET_UNKNOWN
)
1103 /* this must not happen for a xscale target */
1104 LOG_ERROR("target was in unknown state when halt was requested");
1105 return ERROR_TARGET_INVALID
;
1107 else if (target
->state
== TARGET_RESET
)
1109 LOG_DEBUG("target->state == TARGET_RESET");
1113 /* assert external dbg break */
1114 xscale
->external_debug_break
= 1;
1115 xscale_read_dcsr(target
);
1117 target
->debug_reason
= DBG_REASON_DBGRQ
;
1123 static int xscale_enable_single_step(struct target
*target
, uint32_t next_pc
)
1125 struct xscale_common
*xscale
= target_to_xscale(target
);
1126 struct reg
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1129 if (xscale
->ibcr0_used
)
1131 struct breakpoint
*ibcr0_bp
= breakpoint_find(target
, buf_get_u32(ibcr0
->value
, 0, 32) & 0xfffffffe);
1135 xscale_unset_breakpoint(target
, ibcr0_bp
);
1139 LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1144 if ((retval
= xscale_set_reg_u32(ibcr0
, next_pc
| 0x1)) != ERROR_OK
)
1150 static int xscale_disable_single_step(struct target
*target
)
1152 struct xscale_common
*xscale
= target_to_xscale(target
);
1153 struct reg
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1156 if ((retval
= xscale_set_reg_u32(ibcr0
, 0x0)) != ERROR_OK
)
1162 static void xscale_enable_watchpoints(struct target
*target
)
1164 struct watchpoint
*watchpoint
= target
->watchpoints
;
1168 if (watchpoint
->set
== 0)
1169 xscale_set_watchpoint(target
, watchpoint
);
1170 watchpoint
= watchpoint
->next
;
1174 static void xscale_enable_breakpoints(struct target
*target
)
1176 struct breakpoint
*breakpoint
= target
->breakpoints
;
1178 /* set any pending breakpoints */
1181 if (breakpoint
->set
== 0)
1182 xscale_set_breakpoint(target
, breakpoint
);
1183 breakpoint
= breakpoint
->next
;
1187 static int xscale_resume(struct target
*target
, int current
,
1188 uint32_t address
, int handle_breakpoints
, int debug_execution
)
1190 struct xscale_common
*xscale
= target_to_xscale(target
);
1191 struct armv4_5_common_s
*armv4_5
= &xscale
->armv4_5_common
;
1192 struct breakpoint
*breakpoint
= target
->breakpoints
;
1193 uint32_t current_pc
;
1199 if (target
->state
!= TARGET_HALTED
)
1201 LOG_WARNING("target not halted");
1202 return ERROR_TARGET_NOT_HALTED
;
1205 if (!debug_execution
)
1207 target_free_all_working_areas(target
);
1210 /* update vector tables */
1211 if ((retval
= xscale_update_vectors(target
)) != ERROR_OK
)
1214 /* current = 1: continue on current pc, otherwise continue at <address> */
1216 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1218 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1220 /* if we're at the reset vector, we have to simulate the branch */
1221 if (current_pc
== 0x0)
1223 arm_simulate_step(target
, NULL
);
1224 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1227 /* the front-end may request us not to handle breakpoints */
1228 if (handle_breakpoints
)
1230 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1234 /* there's a breakpoint at the current PC, we have to step over it */
1235 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
1236 xscale_unset_breakpoint(target
, breakpoint
);
1238 /* calculate PC of next instruction */
1239 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1241 uint32_t current_opcode
;
1242 target_read_u32(target
, current_pc
, ¤t_opcode
);
1243 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"", current_opcode
);
1246 LOG_DEBUG("enable single-step");
1247 xscale_enable_single_step(target
, next_pc
);
1249 /* restore banked registers */
1250 xscale_restore_context(target
);
1252 /* send resume request (command 0x30 or 0x31)
1253 * clean the trace buffer if it is to be enabled (0x62) */
1254 if (xscale
->trace
.buffer_enabled
)
1256 xscale_send_u32(target
, 0x62);
1257 xscale_send_u32(target
, 0x31);
1260 xscale_send_u32(target
, 0x30);
1263 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1264 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1266 for (i
= 7; i
>= 0; i
--)
1269 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1270 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32
"", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1274 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1275 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1277 /* wait for and process debug entry */
1278 xscale_debug_entry(target
);
1280 LOG_DEBUG("disable single-step");
1281 xscale_disable_single_step(target
);
1283 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
1284 xscale_set_breakpoint(target
, breakpoint
);
1288 /* enable any pending breakpoints and watchpoints */
1289 xscale_enable_breakpoints(target
);
1290 xscale_enable_watchpoints(target
);
1292 /* restore banked registers */
1293 xscale_restore_context(target
);
1295 /* send resume request (command 0x30 or 0x31)
1296 * clean the trace buffer if it is to be enabled (0x62) */
1297 if (xscale
->trace
.buffer_enabled
)
1299 xscale_send_u32(target
, 0x62);
1300 xscale_send_u32(target
, 0x31);
1303 xscale_send_u32(target
, 0x30);
1306 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1307 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1309 for (i
= 7; i
>= 0; i
--)
1312 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1313 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32
"", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1317 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1318 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1320 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1322 if (!debug_execution
)
1324 /* registers are now invalid */
1325 register_cache_invalidate(armv4_5
->core_cache
);
1326 target
->state
= TARGET_RUNNING
;
1327 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1331 target
->state
= TARGET_DEBUG_RUNNING
;
1332 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1335 LOG_DEBUG("target resumed");
1340 static int xscale_step_inner(struct target
*target
, int current
,
1341 uint32_t address
, int handle_breakpoints
)
1343 struct xscale_common
*xscale
= target_to_xscale(target
);
1344 struct armv4_5_common_s
*armv4_5
= &xscale
->armv4_5_common
;
1349 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1351 /* calculate PC of next instruction */
1352 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1354 uint32_t current_opcode
, current_pc
;
1355 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1357 target_read_u32(target
, current_pc
, ¤t_opcode
);
1358 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"", current_opcode
);
1362 LOG_DEBUG("enable single-step");
1363 if ((retval
= xscale_enable_single_step(target
, next_pc
)) != ERROR_OK
)
1366 /* restore banked registers */
1367 if ((retval
= xscale_restore_context(target
)) != ERROR_OK
)
1370 /* send resume request (command 0x30 or 0x31)
1371 * clean the trace buffer if it is to be enabled (0x62) */
1372 if (xscale
->trace
.buffer_enabled
)
1374 if ((retval
= xscale_send_u32(target
, 0x62)) != ERROR_OK
)
1376 if ((retval
= xscale_send_u32(target
, 0x31)) != ERROR_OK
)
1380 if ((retval
= xscale_send_u32(target
, 0x30)) != ERROR_OK
)
1384 if ((retval
= xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32))) != ERROR_OK
)
1386 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1388 for (i
= 7; i
>= 0; i
--)
1391 if ((retval
= xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32))) != ERROR_OK
)
1393 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32
"", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1397 if ((retval
= xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))) != ERROR_OK
)
1399 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1401 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1403 /* registers are now invalid */
1404 register_cache_invalidate(armv4_5
->core_cache
);
1406 /* wait for and process debug entry */
1407 if ((retval
= xscale_debug_entry(target
)) != ERROR_OK
)
1410 LOG_DEBUG("disable single-step");
1411 if ((retval
= xscale_disable_single_step(target
)) != ERROR_OK
)
1414 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1419 static int xscale_step(struct target
*target
, int current
,
1420 uint32_t address
, int handle_breakpoints
)
1422 struct armv4_5_common_s
*armv4_5
= target_to_armv4_5(target
);
1423 struct breakpoint
*breakpoint
= target
->breakpoints
;
1425 uint32_t current_pc
;
1428 if (target
->state
!= TARGET_HALTED
)
1430 LOG_WARNING("target not halted");
1431 return ERROR_TARGET_NOT_HALTED
;
1434 /* current = 1: continue on current pc, otherwise continue at <address> */
1436 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1438 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1440 /* if we're at the reset vector, we have to simulate the step */
1441 if (current_pc
== 0x0)
1443 if ((retval
= arm_simulate_step(target
, NULL
)) != ERROR_OK
)
1445 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1447 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1448 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1453 /* the front-end may request us not to handle breakpoints */
1454 if (handle_breakpoints
)
1455 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1457 if ((retval
= xscale_unset_breakpoint(target
, breakpoint
)) != ERROR_OK
)
1461 retval
= xscale_step_inner(target
, current
, address
, handle_breakpoints
);
1465 xscale_set_breakpoint(target
, breakpoint
);
1468 LOG_DEBUG("target stepped");
1474 static int xscale_assert_reset(struct target
*target
)
1476 struct xscale_common
*xscale
= target_to_xscale(target
);
1478 LOG_DEBUG("target->state: %s",
1479 target_state_name(target
));
1481 /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1482 * end up in T-L-R, which would reset JTAG
1484 jtag_set_end_state(TAP_IDLE
);
1485 xscale_jtag_set_instr(target
->tap
, XSCALE_SELDCSR
);
1487 /* set Hold reset, Halt mode and Trap Reset */
1488 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1489 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1490 xscale_write_dcsr(target
, 1, 0);
1492 /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1493 xscale_jtag_set_instr(target
->tap
, 0x7f);
1494 jtag_execute_queue();
1497 jtag_add_reset(0, 1);
1499 /* sleep 1ms, to be sure we fulfill any requirements */
1500 jtag_add_sleep(1000);
1501 jtag_execute_queue();
1503 target
->state
= TARGET_RESET
;
1505 if (target
->reset_halt
)
1508 if ((retval
= target_halt(target
)) != ERROR_OK
)
1515 static int xscale_deassert_reset(struct target
*target
)
1517 struct xscale_common
*xscale
= target_to_xscale(target
);
1518 struct breakpoint
*breakpoint
= target
->breakpoints
;
1522 xscale
->ibcr_available
= 2;
1523 xscale
->ibcr0_used
= 0;
1524 xscale
->ibcr1_used
= 0;
1526 xscale
->dbr_available
= 2;
1527 xscale
->dbr0_used
= 0;
1528 xscale
->dbr1_used
= 0;
1530 /* mark all hardware breakpoints as unset */
1533 if (breakpoint
->type
== BKPT_HARD
)
1535 breakpoint
->set
= 0;
1537 breakpoint
= breakpoint
->next
;
1540 register_cache_invalidate(xscale
->armv4_5_common
.core_cache
);
1542 /* FIXME mark hardware watchpoints got unset too. Also,
1543 * at least some of the XScale registers are invalid...
1547 * REVISIT: *assumes* we had a SRST+TRST reset so the mini-icache
1548 * contents got invalidated. Safer to force that, so writing new
1549 * contents can't ever fail..
1554 const uint8_t *buffer
= xscale_debug_handler
;
1558 jtag_add_reset(0, 0);
1560 /* wait 300ms; 150 and 100ms were not enough */
1561 jtag_add_sleep(300*1000);
1563 jtag_add_runtest(2030, jtag_set_end_state(TAP_IDLE
));
1564 jtag_execute_queue();
1566 /* set Hold reset, Halt mode and Trap Reset */
1567 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1568 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1569 xscale_write_dcsr(target
, 1, 0);
1571 /* Load the debug handler into the mini-icache. Since
1572 * it's using halt mode (not monitor mode), it runs in
1573 * "Special Debug State" for access to registers, memory,
1574 * coprocessors, trace data, etc.
1576 address
= xscale
->handler_address
;
1577 for (unsigned binary_size
= sizeof xscale_debug_handler
- 1;
1579 binary_size
-= buf_cnt
, buffer
+= buf_cnt
)
1581 uint32_t cache_line
[8];
1584 buf_cnt
= binary_size
;
1588 for (i
= 0; i
< buf_cnt
; i
+= 4)
1590 /* convert LE buffer to host-endian uint32_t */
1591 cache_line
[i
/ 4] = le_to_h_u32(&buffer
[i
]);
1594 for (; i
< 32; i
+= 4)
1596 cache_line
[i
/ 4] = 0xe1a08008;
1599 /* only load addresses other than the reset vectors */
1600 if ((address
% 0x400) != 0x0)
1602 retval
= xscale_load_ic(target
, address
,
1604 if (retval
!= ERROR_OK
)
1611 retval
= xscale_load_ic(target
, 0x0,
1612 xscale
->low_vectors
);
1613 if (retval
!= ERROR_OK
)
1615 retval
= xscale_load_ic(target
, 0xffff0000,
1616 xscale
->high_vectors
);
1617 if (retval
!= ERROR_OK
)
1620 jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE
));
1622 jtag_add_sleep(100000);
1624 /* set Hold reset, Halt mode and Trap Reset */
1625 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1626 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1627 xscale_write_dcsr(target
, 1, 0);
1629 /* clear Hold reset to let the target run (should enter debug handler) */
1630 xscale_write_dcsr(target
, 0, 1);
1631 target
->state
= TARGET_RUNNING
;
1633 if (!target
->reset_halt
)
1635 jtag_add_sleep(10000);
1637 /* we should have entered debug now */
1638 xscale_debug_entry(target
);
1639 target
->state
= TARGET_HALTED
;
1641 /* resume the target */
1642 xscale_resume(target
, 1, 0x0, 1, 0);
1649 static int xscale_read_core_reg(struct target
*target
, struct reg
*r
,
1650 int num
, enum armv4_5_mode mode
)
1652 /** \todo add debug handler support for core register reads */
1653 LOG_ERROR("not implemented");
1657 static int xscale_write_core_reg(struct target
*target
, struct reg
*r
,
1658 int num
, enum armv4_5_mode mode
, uint32_t value
)
1660 /** \todo add debug handler support for core register writes */
1661 LOG_ERROR("not implemented");
1665 static int xscale_full_context(struct target
*target
)
1667 struct armv4_5_common_s
*armv4_5
= target_to_armv4_5(target
);
1675 if (target
->state
!= TARGET_HALTED
)
1677 LOG_WARNING("target not halted");
1678 return ERROR_TARGET_NOT_HALTED
;
1681 buffer
= malloc(4 * 8);
1683 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1684 * we can't enter User mode on an XScale (unpredictable),
1685 * but User shares registers with SYS
1687 for (i
= 1; i
< 7; i
++)
1691 /* check if there are invalid registers in the current mode
1693 for (j
= 0; j
<= 16; j
++)
1695 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1703 /* request banked registers */
1704 xscale_send_u32(target
, 0x0);
1707 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1708 tmp_cpsr
|= 0xc0; /* I/F bits */
1710 /* send CPSR for desired mode */
1711 xscale_send_u32(target
, tmp_cpsr
);
1713 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1714 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1716 xscale_receive(target
, buffer
, 8);
1717 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
1718 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1719 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
= 1;
1723 xscale_receive(target
, buffer
, 7);
1726 /* move data from buffer to register cache */
1727 for (j
= 8; j
<= 14; j
++)
1729 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).value
, 0, 32, buffer
[j
- 8]);
1730 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1731 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
= 1;
1741 static int xscale_restore_context(struct target
*target
)
1743 struct armv4_5_common_s
*armv4_5
= target_to_armv4_5(target
);
1747 if (target
->state
!= TARGET_HALTED
)
1749 LOG_WARNING("target not halted");
1750 return ERROR_TARGET_NOT_HALTED
;
1753 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1754 * we can't enter User mode on an XScale (unpredictable),
1755 * but User shares registers with SYS
1757 for (i
= 1; i
< 7; i
++)
1761 /* check if there are invalid registers in the current mode
1763 for (j
= 8; j
<= 14; j
++)
1765 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
== 1)
1769 /* if not USR/SYS, check if the SPSR needs to be written */
1770 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1772 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
== 1)
1780 /* send banked registers */
1781 xscale_send_u32(target
, 0x1);
1784 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1785 tmp_cpsr
|= 0xc0; /* I/F bits */
1787 /* send CPSR for desired mode */
1788 xscale_send_u32(target
, tmp_cpsr
);
1790 /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1791 for (j
= 8; j
<= 14; j
++)
1793 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, j
).value
, 0, 32));
1794 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1797 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1799 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32));
1800 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1808 static int xscale_read_memory(struct target
*target
, uint32_t address
,
1809 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1811 struct xscale_common
*xscale
= target_to_xscale(target
);
1816 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
, address
, size
, count
);
1818 if (target
->state
!= TARGET_HALTED
)
1820 LOG_WARNING("target not halted");
1821 return ERROR_TARGET_NOT_HALTED
;
1824 /* sanitize arguments */
1825 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1826 return ERROR_INVALID_ARGUMENTS
;
1828 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1829 return ERROR_TARGET_UNALIGNED_ACCESS
;
1831 /* send memory read request (command 0x1n, n: access size) */
1832 if ((retval
= xscale_send_u32(target
, 0x10 | size
)) != ERROR_OK
)
1835 /* send base address for read request */
1836 if ((retval
= xscale_send_u32(target
, address
)) != ERROR_OK
)
1839 /* send number of requested data words */
1840 if ((retval
= xscale_send_u32(target
, count
)) != ERROR_OK
)
1843 /* receive data from target (count times 32-bit words in host endianness) */
1844 buf32
= malloc(4 * count
);
1845 if ((retval
= xscale_receive(target
, buf32
, count
)) != ERROR_OK
)
1848 /* extract data from host-endian buffer into byte stream */
1849 for (i
= 0; i
< count
; i
++)
1854 target_buffer_set_u32(target
, buffer
, buf32
[i
]);
1858 target_buffer_set_u16(target
, buffer
, buf32
[i
] & 0xffff);
1862 *buffer
++ = buf32
[i
] & 0xff;
1865 LOG_ERROR("invalid read size");
1866 return ERROR_INVALID_ARGUMENTS
;
1872 /* examine DCSR, to see if Sticky Abort (SA) got set */
1873 if ((retval
= xscale_read_dcsr(target
)) != ERROR_OK
)
1875 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
1878 if ((retval
= xscale_send_u32(target
, 0x60)) != ERROR_OK
)
1881 return ERROR_TARGET_DATA_ABORT
;
1887 static int xscale_write_memory(struct target
*target
, uint32_t address
,
1888 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1890 struct xscale_common
*xscale
= target_to_xscale(target
);
1893 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
, address
, size
, count
);
1895 if (target
->state
!= TARGET_HALTED
)
1897 LOG_WARNING("target not halted");
1898 return ERROR_TARGET_NOT_HALTED
;
1901 /* sanitize arguments */
1902 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1903 return ERROR_INVALID_ARGUMENTS
;
1905 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1906 return ERROR_TARGET_UNALIGNED_ACCESS
;
1908 /* send memory write request (command 0x2n, n: access size) */
1909 if ((retval
= xscale_send_u32(target
, 0x20 | size
)) != ERROR_OK
)
1912 /* send base address for read request */
1913 if ((retval
= xscale_send_u32(target
, address
)) != ERROR_OK
)
1916 /* send number of requested data words to be written*/
1917 if ((retval
= xscale_send_u32(target
, count
)) != ERROR_OK
)
1920 /* extract data from host-endian buffer into byte stream */
1922 for (i
= 0; i
< count
; i
++)
1927 value
= target_buffer_get_u32(target
, buffer
);
1928 xscale_send_u32(target
, value
);
1932 value
= target_buffer_get_u16(target
, buffer
);
1933 xscale_send_u32(target
, value
);
1938 xscale_send_u32(target
, value
);
1942 LOG_ERROR("should never get here");
1947 if ((retval
= xscale_send(target
, buffer
, count
, size
)) != ERROR_OK
)
1950 /* examine DCSR, to see if Sticky Abort (SA) got set */
1951 if ((retval
= xscale_read_dcsr(target
)) != ERROR_OK
)
1953 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
1956 if ((retval
= xscale_send_u32(target
, 0x60)) != ERROR_OK
)
1959 return ERROR_TARGET_DATA_ABORT
;
1965 static int xscale_bulk_write_memory(struct target
*target
, uint32_t address
,
1966 uint32_t count
, uint8_t *buffer
)
1968 return xscale_write_memory(target
, address
, 4, count
, buffer
);
1971 static uint32_t xscale_get_ttb(struct target
*target
)
1973 struct xscale_common
*xscale
= target_to_xscale(target
);
1976 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_TTB
]);
1977 ttb
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_TTB
].value
, 0, 32);
1982 static void xscale_disable_mmu_caches(struct target
*target
, int mmu
,
1983 int d_u_cache
, int i_cache
)
1985 struct xscale_common
*xscale
= target_to_xscale(target
);
1986 uint32_t cp15_control
;
1988 /* read cp15 control register */
1989 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
1990 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
1993 cp15_control
&= ~0x1U
;
1998 xscale_send_u32(target
, 0x50);
1999 xscale_send_u32(target
, xscale
->cache_clean_address
);
2001 /* invalidate DCache */
2002 xscale_send_u32(target
, 0x51);
2004 cp15_control
&= ~0x4U
;
2009 /* invalidate ICache */
2010 xscale_send_u32(target
, 0x52);
2011 cp15_control
&= ~0x1000U
;
2014 /* write new cp15 control register */
2015 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2017 /* execute cpwait to ensure outstanding operations complete */
2018 xscale_send_u32(target
, 0x53);
2021 static void xscale_enable_mmu_caches(struct target
*target
, int mmu
,
2022 int d_u_cache
, int i_cache
)
2024 struct xscale_common
*xscale
= target_to_xscale(target
);
2025 uint32_t cp15_control
;
2027 /* read cp15 control register */
2028 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2029 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2032 cp15_control
|= 0x1U
;
2035 cp15_control
|= 0x4U
;
2038 cp15_control
|= 0x1000U
;
2040 /* write new cp15 control register */
2041 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2043 /* execute cpwait to ensure outstanding operations complete */
2044 xscale_send_u32(target
, 0x53);
2047 static int xscale_set_breakpoint(struct target
*target
,
2048 struct breakpoint
*breakpoint
)
2051 struct xscale_common
*xscale
= target_to_xscale(target
);
2053 if (target
->state
!= TARGET_HALTED
)
2055 LOG_WARNING("target not halted");
2056 return ERROR_TARGET_NOT_HALTED
;
2059 if (breakpoint
->set
)
2061 LOG_WARNING("breakpoint already set");
2065 if (breakpoint
->type
== BKPT_HARD
)
2067 uint32_t value
= breakpoint
->address
| 1;
2068 if (!xscale
->ibcr0_used
)
2070 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], value
);
2071 xscale
->ibcr0_used
= 1;
2072 breakpoint
->set
= 1; /* breakpoint set on first breakpoint register */
2074 else if (!xscale
->ibcr1_used
)
2076 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], value
);
2077 xscale
->ibcr1_used
= 1;
2078 breakpoint
->set
= 2; /* breakpoint set on second breakpoint register */
2082 LOG_ERROR("BUG: no hardware comparator available");
2086 else if (breakpoint
->type
== BKPT_SOFT
)
2088 if (breakpoint
->length
== 4)
2090 /* keep the original instruction in target endianness */
2091 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2095 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2096 if ((retval
= target_write_u32(target
, breakpoint
->address
, xscale
->arm_bkpt
)) != ERROR_OK
)
2103 /* keep the original instruction in target endianness */
2104 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2108 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2109 if ((retval
= target_write_u32(target
, breakpoint
->address
, xscale
->thumb_bkpt
)) != ERROR_OK
)
2114 breakpoint
->set
= 1;
2120 static int xscale_add_breakpoint(struct target
*target
,
2121 struct breakpoint
*breakpoint
)
2123 struct xscale_common
*xscale
= target_to_xscale(target
);
2125 if (target
->state
!= TARGET_HALTED
)
2127 LOG_WARNING("target not halted");
2128 return ERROR_TARGET_NOT_HALTED
;
2131 if ((breakpoint
->type
== BKPT_HARD
) && (xscale
->ibcr_available
< 1))
2133 LOG_INFO("no breakpoint unit available for hardware breakpoint");
2134 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2137 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
2139 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2140 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2143 if (breakpoint
->type
== BKPT_HARD
)
2145 xscale
->ibcr_available
--;
2151 static int xscale_unset_breakpoint(struct target
*target
,
2152 struct breakpoint
*breakpoint
)
2155 struct xscale_common
*xscale
= target_to_xscale(target
);
2157 if (target
->state
!= TARGET_HALTED
)
2159 LOG_WARNING("target not halted");
2160 return ERROR_TARGET_NOT_HALTED
;
2163 if (!breakpoint
->set
)
2165 LOG_WARNING("breakpoint not set");
2169 if (breakpoint
->type
== BKPT_HARD
)
2171 if (breakpoint
->set
== 1)
2173 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], 0x0);
2174 xscale
->ibcr0_used
= 0;
2176 else if (breakpoint
->set
== 2)
2178 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], 0x0);
2179 xscale
->ibcr1_used
= 0;
2181 breakpoint
->set
= 0;
2185 /* restore original instruction (kept in target endianness) */
2186 if (breakpoint
->length
== 4)
2188 if ((retval
= target_write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2195 if ((retval
= target_write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2200 breakpoint
->set
= 0;
2206 static int xscale_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
2208 struct xscale_common
*xscale
= target_to_xscale(target
);
2210 if (target
->state
!= TARGET_HALTED
)
2212 LOG_WARNING("target not halted");
2213 return ERROR_TARGET_NOT_HALTED
;
2216 if (breakpoint
->set
)
2218 xscale_unset_breakpoint(target
, breakpoint
);
2221 if (breakpoint
->type
== BKPT_HARD
)
2222 xscale
->ibcr_available
++;
2227 static int xscale_set_watchpoint(struct target
*target
,
2228 struct watchpoint
*watchpoint
)
2230 struct xscale_common
*xscale
= target_to_xscale(target
);
2232 struct reg
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2233 uint32_t dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2235 if (target
->state
!= TARGET_HALTED
)
2237 LOG_WARNING("target not halted");
2238 return ERROR_TARGET_NOT_HALTED
;
2241 xscale_get_reg(dbcon
);
2243 switch (watchpoint
->rw
)
2255 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2258 if (!xscale
->dbr0_used
)
2260 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR0
], watchpoint
->address
);
2261 dbcon_value
|= enable
;
2262 xscale_set_reg_u32(dbcon
, dbcon_value
);
2263 watchpoint
->set
= 1;
2264 xscale
->dbr0_used
= 1;
2266 else if (!xscale
->dbr1_used
)
2268 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR1
], watchpoint
->address
);
2269 dbcon_value
|= enable
<< 2;
2270 xscale_set_reg_u32(dbcon
, dbcon_value
);
2271 watchpoint
->set
= 2;
2272 xscale
->dbr1_used
= 1;
2276 LOG_ERROR("BUG: no hardware comparator available");
2283 static int xscale_add_watchpoint(struct target
*target
,
2284 struct watchpoint
*watchpoint
)
2286 struct xscale_common
*xscale
= target_to_xscale(target
);
2288 if (target
->state
!= TARGET_HALTED
)
2290 LOG_WARNING("target not halted");
2291 return ERROR_TARGET_NOT_HALTED
;
2294 if (xscale
->dbr_available
< 1)
2296 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2299 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
2301 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2304 xscale
->dbr_available
--;
2309 static int xscale_unset_watchpoint(struct target
*target
,
2310 struct watchpoint
*watchpoint
)
2312 struct xscale_common
*xscale
= target_to_xscale(target
);
2313 struct reg
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2314 uint32_t dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2316 if (target
->state
!= TARGET_HALTED
)
2318 LOG_WARNING("target not halted");
2319 return ERROR_TARGET_NOT_HALTED
;
2322 if (!watchpoint
->set
)
2324 LOG_WARNING("breakpoint not set");
2328 if (watchpoint
->set
== 1)
2330 dbcon_value
&= ~0x3;
2331 xscale_set_reg_u32(dbcon
, dbcon_value
);
2332 xscale
->dbr0_used
= 0;
2334 else if (watchpoint
->set
== 2)
2336 dbcon_value
&= ~0xc;
2337 xscale_set_reg_u32(dbcon
, dbcon_value
);
2338 xscale
->dbr1_used
= 0;
2340 watchpoint
->set
= 0;
2345 static int xscale_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
2347 struct xscale_common
*xscale
= target_to_xscale(target
);
2349 if (target
->state
!= TARGET_HALTED
)
2351 LOG_WARNING("target not halted");
2352 return ERROR_TARGET_NOT_HALTED
;
2355 if (watchpoint
->set
)
2357 xscale_unset_watchpoint(target
, watchpoint
);
2360 xscale
->dbr_available
++;
2365 static int xscale_get_reg(struct reg
*reg
)
2367 struct xscale_reg
*arch_info
= reg
->arch_info
;
2368 struct target
*target
= arch_info
->target
;
2369 struct xscale_common
*xscale
= target_to_xscale(target
);
2371 /* DCSR, TX and RX are accessible via JTAG */
2372 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2374 return xscale_read_dcsr(arch_info
->target
);
2376 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2378 /* 1 = consume register content */
2379 return xscale_read_tx(arch_info
->target
, 1);
2381 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2383 /* can't read from RX register (host -> debug handler) */
2386 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2388 /* can't (explicitly) read from TXRXCTRL register */
2391 else /* Other DBG registers have to be transfered by the debug handler */
2393 /* send CP read request (command 0x40) */
2394 xscale_send_u32(target
, 0x40);
2396 /* send CP register number */
2397 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2399 /* read register value */
2400 xscale_read_tx(target
, 1);
2401 buf_cpy(xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
, reg
->value
, 32);
2410 static int xscale_set_reg(struct reg
*reg
, uint8_t* buf
)
2412 struct xscale_reg
*arch_info
= reg
->arch_info
;
2413 struct target
*target
= arch_info
->target
;
2414 struct xscale_common
*xscale
= target_to_xscale(target
);
2415 uint32_t value
= buf_get_u32(buf
, 0, 32);
2417 /* DCSR, TX and RX are accessible via JTAG */
2418 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2420 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32, value
);
2421 return xscale_write_dcsr(arch_info
->target
, -1, -1);
2423 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2425 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
2426 return xscale_write_rx(arch_info
->target
);
2428 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2430 /* can't write to TX register (debug-handler -> host) */
2433 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2435 /* can't (explicitly) write to TXRXCTRL register */
2438 else /* Other DBG registers have to be transfered by the debug handler */
2440 /* send CP write request (command 0x41) */
2441 xscale_send_u32(target
, 0x41);
2443 /* send CP register number */
2444 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2446 /* send CP register value */
2447 xscale_send_u32(target
, value
);
2448 buf_set_u32(reg
->value
, 0, 32, value
);
2454 static int xscale_write_dcsr_sw(struct target
*target
, uint32_t value
)
2456 struct xscale_common
*xscale
= target_to_xscale(target
);
2457 struct reg
*dcsr
= &xscale
->reg_cache
->reg_list
[XSCALE_DCSR
];
2458 struct xscale_reg
*dcsr_arch_info
= dcsr
->arch_info
;
2460 /* send CP write request (command 0x41) */
2461 xscale_send_u32(target
, 0x41);
2463 /* send CP register number */
2464 xscale_send_u32(target
, dcsr_arch_info
->dbg_handler_number
);
2466 /* send CP register value */
2467 xscale_send_u32(target
, value
);
2468 buf_set_u32(dcsr
->value
, 0, 32, value
);
2473 static int xscale_read_trace(struct target
*target
)
2475 struct xscale_common
*xscale
= target_to_xscale(target
);
2476 struct armv4_5_common_s
*armv4_5
= &xscale
->armv4_5_common
;
2477 struct xscale_trace_data
**trace_data_p
;
2479 /* 258 words from debug handler
2480 * 256 trace buffer entries
2481 * 2 checkpoint addresses
2483 uint32_t trace_buffer
[258];
2484 int is_address
[256];
2487 if (target
->state
!= TARGET_HALTED
)
2489 LOG_WARNING("target must be stopped to read trace data");
2490 return ERROR_TARGET_NOT_HALTED
;
2493 /* send read trace buffer command (command 0x61) */
2494 xscale_send_u32(target
, 0x61);
2496 /* receive trace buffer content */
2497 xscale_receive(target
, trace_buffer
, 258);
2499 /* parse buffer backwards to identify address entries */
2500 for (i
= 255; i
>= 0; i
--)
2503 if (((trace_buffer
[i
] & 0xf0) == 0x90) ||
2504 ((trace_buffer
[i
] & 0xf0) == 0xd0))
2507 is_address
[--i
] = 1;
2509 is_address
[--i
] = 1;
2511 is_address
[--i
] = 1;
2513 is_address
[--i
] = 1;
2518 /* search first non-zero entry */
2519 for (j
= 0; (j
< 256) && (trace_buffer
[j
] == 0) && (!is_address
[j
]); j
++)
2524 LOG_DEBUG("no trace data collected");
2525 return ERROR_XSCALE_NO_TRACE_DATA
;
2528 for (trace_data_p
= &xscale
->trace
.data
; *trace_data_p
; trace_data_p
= &(*trace_data_p
)->next
)
2531 *trace_data_p
= malloc(sizeof(struct xscale_trace_data
));
2532 (*trace_data_p
)->next
= NULL
;
2533 (*trace_data_p
)->chkpt0
= trace_buffer
[256];
2534 (*trace_data_p
)->chkpt1
= trace_buffer
[257];
2535 (*trace_data_p
)->last_instruction
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
2536 (*trace_data_p
)->entries
= malloc(sizeof(struct xscale_trace_entry
) * (256 - j
));
2537 (*trace_data_p
)->depth
= 256 - j
;
2539 for (i
= j
; i
< 256; i
++)
2541 (*trace_data_p
)->entries
[i
- j
].data
= trace_buffer
[i
];
2543 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_ADDRESS
;
2545 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_MESSAGE
;
2551 static int xscale_read_instruction(struct target
*target
,
2552 struct arm_instruction
*instruction
)
2554 struct xscale_common
*xscale
= target_to_xscale(target
);
2561 if (!xscale
->trace
.image
)
2562 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
2564 /* search for the section the current instruction belongs to */
2565 for (i
= 0; i
< xscale
->trace
.image
->num_sections
; i
++)
2567 if ((xscale
->trace
.image
->sections
[i
].base_address
<= xscale
->trace
.current_pc
) &&
2568 (xscale
->trace
.image
->sections
[i
].base_address
+ xscale
->trace
.image
->sections
[i
].size
> xscale
->trace
.current_pc
))
2577 /* current instruction couldn't be found in the image */
2578 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2581 if (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
)
2584 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2585 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2586 4, buf
, &size_read
)) != ERROR_OK
)
2588 LOG_ERROR("error while reading instruction: %i", retval
);
2589 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2591 opcode
= target_buffer_get_u32(target
, buf
);
2592 arm_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2594 else if (xscale
->trace
.core_state
== ARMV4_5_STATE_THUMB
)
2597 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2598 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2599 2, buf
, &size_read
)) != ERROR_OK
)
2601 LOG_ERROR("error while reading instruction: %i", retval
);
2602 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2604 opcode
= target_buffer_get_u16(target
, buf
);
2605 thumb_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2609 LOG_ERROR("BUG: unknown core state encountered");
2616 static int xscale_branch_address(struct xscale_trace_data
*trace_data
,
2617 int i
, uint32_t *target
)
2619 /* if there are less than four entries prior to the indirect branch message
2620 * we can't extract the address */
2626 *target
= (trace_data
->entries
[i
-1].data
) | (trace_data
->entries
[i
-2].data
<< 8) |
2627 (trace_data
->entries
[i
-3].data
<< 16) | (trace_data
->entries
[i
-4].data
<< 24);
2632 static int xscale_analyze_trace(struct target
*target
, struct command_context
*cmd_ctx
)
2634 struct xscale_common
*xscale
= target_to_xscale(target
);
2636 uint32_t next_pc
= 0x0;
2637 struct xscale_trace_data
*trace_data
= xscale
->trace
.data
;
2646 xscale
->trace
.core_state
= ARMV4_5_STATE_ARM
;
2651 for (i
= 0; i
< trace_data
->depth
; i
++)
2657 if (trace_data
->entries
[i
].type
== XSCALE_TRACE_ADDRESS
)
2660 switch ((trace_data
->entries
[i
].data
& 0xf0) >> 4)
2662 case 0: /* Exceptions */
2670 exception
= (trace_data
->entries
[i
].data
& 0x70) >> 4;
2672 next_pc
= (trace_data
->entries
[i
].data
& 0xf0) >> 2;
2673 command_print(cmd_ctx
, "--- exception %i ---", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2675 case 8: /* Direct Branch */
2678 case 9: /* Indirect Branch */
2680 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2685 case 13: /* Checkpointed Indirect Branch */
2686 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2689 if (((chkpt
== 0) && (next_pc
!= trace_data
->chkpt0
))
2690 || ((chkpt
== 1) && (next_pc
!= trace_data
->chkpt1
)))
2691 LOG_WARNING("checkpointed indirect branch target address doesn't match checkpoint");
2693 /* explicit fall-through */
2694 case 12: /* Checkpointed Direct Branch */
2699 next_pc
= trace_data
->chkpt0
;
2702 else if (chkpt
== 1)
2705 next_pc
= trace_data
->chkpt0
;
2710 LOG_WARNING("more than two checkpointed branches encountered");
2713 case 15: /* Roll-over */
2716 default: /* Reserved */
2717 command_print(cmd_ctx
, "--- reserved trace message ---");
2718 LOG_ERROR("BUG: trace message %i is reserved", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2722 if (xscale
->trace
.pc_ok
)
2724 int executed
= (trace_data
->entries
[i
].data
& 0xf) + rollover
* 16;
2725 struct arm_instruction instruction
;
2727 if ((exception
== 6) || (exception
== 7))
2729 /* IRQ or FIQ exception, no instruction executed */
2733 while (executed
-- >= 0)
2735 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2737 /* can't continue tracing with no image available */
2738 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2742 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2744 /* TODO: handle incomplete images */
2748 /* a precise abort on a load to the PC is included in the incremental
2749 * word count, other instructions causing data aborts are not included
2751 if ((executed
== 0) && (exception
== 4)
2752 && ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDM
)))
2754 if ((instruction
.type
== ARM_LDM
)
2755 && ((instruction
.info
.load_store_multiple
.register_list
& 0x8000) == 0))
2759 else if (((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDRSH
))
2760 && (instruction
.info
.load_store
.Rd
!= 15))
2766 /* only the last instruction executed
2767 * (the one that caused the control flow change)
2768 * could be a taken branch
2770 if (((executed
== -1) && (branch
== 1)) &&
2771 (((instruction
.type
== ARM_B
) ||
2772 (instruction
.type
== ARM_BL
) ||
2773 (instruction
.type
== ARM_BLX
)) &&
2774 (instruction
.info
.b_bl_bx_blx
.target_address
!= 0xffffffff)))
2776 xscale
->trace
.current_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
2780 xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
2782 command_print(cmd_ctx
, "%s", instruction
.text
);
2790 xscale
->trace
.current_pc
= next_pc
;
2791 xscale
->trace
.pc_ok
= 1;
2795 for (; xscale
->trace
.current_pc
< trace_data
->last_instruction
; xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2)
2797 struct arm_instruction instruction
;
2798 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2800 /* can't continue tracing with no image available */
2801 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2805 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2807 /* TODO: handle incomplete images */
2810 command_print(cmd_ctx
, "%s", instruction
.text
);
2813 trace_data
= trace_data
->next
;
2819 static const struct reg_arch_type xscale_reg_type
= {
2820 .get
= xscale_get_reg
,
2821 .set
= xscale_set_reg
,
2824 static void xscale_build_reg_cache(struct target
*target
)
2826 struct xscale_common
*xscale
= target_to_xscale(target
);
2827 struct armv4_5_common_s
*armv4_5
= &xscale
->armv4_5_common
;
2828 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
2829 struct xscale_reg
*arch_info
= malloc(sizeof(xscale_reg_arch_info
));
2831 int num_regs
= sizeof(xscale_reg_arch_info
) / sizeof(struct xscale_reg
);
2833 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
2835 (*cache_p
)->next
= malloc(sizeof(struct reg_cache
));
2836 cache_p
= &(*cache_p
)->next
;
2838 /* fill in values for the xscale reg cache */
2839 (*cache_p
)->name
= "XScale registers";
2840 (*cache_p
)->next
= NULL
;
2841 (*cache_p
)->reg_list
= malloc(num_regs
* sizeof(struct reg
));
2842 (*cache_p
)->num_regs
= num_regs
;
2844 for (i
= 0; i
< num_regs
; i
++)
2846 (*cache_p
)->reg_list
[i
].name
= xscale_reg_list
[i
];
2847 (*cache_p
)->reg_list
[i
].value
= calloc(4, 1);
2848 (*cache_p
)->reg_list
[i
].dirty
= 0;
2849 (*cache_p
)->reg_list
[i
].valid
= 0;
2850 (*cache_p
)->reg_list
[i
].size
= 32;
2851 (*cache_p
)->reg_list
[i
].arch_info
= &arch_info
[i
];
2852 (*cache_p
)->reg_list
[i
].type
= &xscale_reg_type
;
2853 arch_info
[i
] = xscale_reg_arch_info
[i
];
2854 arch_info
[i
].target
= target
;
2857 xscale
->reg_cache
= (*cache_p
);
2860 static int xscale_init_target(struct command_context
*cmd_ctx
,
2861 struct target
*target
)
2863 xscale_build_reg_cache(target
);
2867 static int xscale_init_arch_info(struct target
*target
,
2868 struct xscale_common
*xscale
, struct jtag_tap
*tap
, const char *variant
)
2870 struct arm
*armv4_5
;
2871 uint32_t high_reset_branch
, low_reset_branch
;
2874 armv4_5
= &xscale
->armv4_5_common
;
2876 /* store architecture specfic data (none so far) */
2877 xscale
->common_magic
= XSCALE_COMMON_MAGIC
;
2879 /* we don't really *need* variant info ... */
2883 if (strcmp(variant
, "pxa250") == 0
2884 || strcmp(variant
, "pxa255") == 0
2885 || strcmp(variant
, "pxa26x") == 0)
2887 else if (strcmp(variant
, "pxa27x") == 0
2888 || strcmp(variant
, "ixp42x") == 0
2889 || strcmp(variant
, "ixp45x") == 0
2890 || strcmp(variant
, "ixp46x") == 0)
2893 LOG_WARNING("%s: unrecognized variant %s",
2894 tap
->dotted_name
, variant
);
2896 if (ir_length
&& ir_length
!= tap
->ir_length
) {
2897 LOG_WARNING("%s: IR length for %s is %d; fixing",
2898 tap
->dotted_name
, variant
, ir_length
);
2899 tap
->ir_length
= ir_length
;
2903 /* the debug handler isn't installed (and thus not running) at this time */
2904 xscale
->handler_address
= 0xfe000800;
2906 /* clear the vectors we keep locally for reference */
2907 memset(xscale
->low_vectors
, 0, sizeof(xscale
->low_vectors
));
2908 memset(xscale
->high_vectors
, 0, sizeof(xscale
->high_vectors
));
2910 /* no user-specified vectors have been configured yet */
2911 xscale
->static_low_vectors_set
= 0x0;
2912 xscale
->static_high_vectors_set
= 0x0;
2914 /* calculate branches to debug handler */
2915 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
2916 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
2918 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
2919 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
2921 for (i
= 1; i
<= 7; i
++)
2923 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
2924 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
2927 /* 64kB aligned region used for DCache cleaning */
2928 xscale
->cache_clean_address
= 0xfffe0000;
2930 xscale
->hold_rst
= 0;
2931 xscale
->external_debug_break
= 0;
2933 xscale
->ibcr_available
= 2;
2934 xscale
->ibcr0_used
= 0;
2935 xscale
->ibcr1_used
= 0;
2937 xscale
->dbr_available
= 2;
2938 xscale
->dbr0_used
= 0;
2939 xscale
->dbr1_used
= 0;
2941 xscale
->arm_bkpt
= ARMV5_BKPT(0x0);
2942 xscale
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
2944 xscale
->vector_catch
= 0x1;
2946 xscale
->trace
.capture_status
= TRACE_IDLE
;
2947 xscale
->trace
.data
= NULL
;
2948 xscale
->trace
.image
= NULL
;
2949 xscale
->trace
.buffer_enabled
= 0;
2950 xscale
->trace
.buffer_fill
= 0;
2952 /* prepare ARMv4/5 specific information */
2953 armv4_5
->arch_info
= xscale
;
2954 armv4_5
->read_core_reg
= xscale_read_core_reg
;
2955 armv4_5
->write_core_reg
= xscale_write_core_reg
;
2956 armv4_5
->full_context
= xscale_full_context
;
2958 armv4_5_init_arch_info(target
, armv4_5
);
2960 xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
2961 xscale
->armv4_5_mmu
.get_ttb
= xscale_get_ttb
;
2962 xscale
->armv4_5_mmu
.read_memory
= xscale_read_memory
;
2963 xscale
->armv4_5_mmu
.write_memory
= xscale_write_memory
;
2964 xscale
->armv4_5_mmu
.disable_mmu_caches
= xscale_disable_mmu_caches
;
2965 xscale
->armv4_5_mmu
.enable_mmu_caches
= xscale_enable_mmu_caches
;
2966 xscale
->armv4_5_mmu
.has_tiny_pages
= 1;
2967 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
2972 static int xscale_target_create(struct target
*target
, Jim_Interp
*interp
)
2974 struct xscale_common
*xscale
;
2976 if (sizeof xscale_debug_handler
- 1 > 0x800) {
2977 LOG_ERROR("debug_handler.bin: larger than 2kb");
2981 xscale
= calloc(1, sizeof(*xscale
));
2985 return xscale_init_arch_info(target
, xscale
, target
->tap
,
2989 COMMAND_HANDLER(xscale_handle_debug_handler_command
)
2991 struct target
*target
= NULL
;
2992 struct xscale_common
*xscale
;
2994 uint32_t handler_address
;
2998 LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
3002 if ((target
= get_target(CMD_ARGV
[0])) == NULL
)
3004 LOG_ERROR("target '%s' not defined", CMD_ARGV
[0]);
3008 xscale
= target_to_xscale(target
);
3009 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3010 if (retval
!= ERROR_OK
)
3013 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], handler_address
);
3015 if (((handler_address
>= 0x800) && (handler_address
<= 0x1fef800)) ||
3016 ((handler_address
>= 0xfe000800) && (handler_address
<= 0xfffff800)))
3018 xscale
->handler_address
= handler_address
;
3022 LOG_ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3029 COMMAND_HANDLER(xscale_handle_cache_clean_address_command
)
3031 struct target
*target
= NULL
;
3032 struct xscale_common
*xscale
;
3034 uint32_t cache_clean_address
;
3038 return ERROR_COMMAND_SYNTAX_ERROR
;
3041 target
= get_target(CMD_ARGV
[0]);
3044 LOG_ERROR("target '%s' not defined", CMD_ARGV
[0]);
3047 xscale
= target_to_xscale(target
);
3048 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3049 if (retval
!= ERROR_OK
)
3052 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], cache_clean_address
);
3054 if (cache_clean_address
& 0xffff)
3056 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3060 xscale
->cache_clean_address
= cache_clean_address
;
3066 COMMAND_HANDLER(xscale_handle_cache_info_command
)
3068 struct target
*target
= get_current_target(CMD_CTX
);
3069 struct xscale_common
*xscale
= target_to_xscale(target
);
3072 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3073 if (retval
!= ERROR_OK
)
3076 return armv4_5_handle_cache_info_command(CMD_CTX
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
3079 static int xscale_virt2phys(struct target
*target
,
3080 uint32_t virtual, uint32_t *physical
)
3082 struct xscale_common
*xscale
= target_to_xscale(target
);
3088 if (xscale
->common_magic
!= XSCALE_COMMON_MAGIC
) {
3089 LOG_ERROR(xscale_not
);
3090 return ERROR_TARGET_INVALID
;
3093 uint32_t ret
= armv4_5_mmu_translate_va(target
, &xscale
->armv4_5_mmu
, virtual, &type
, &cb
, &domain
, &ap
);
3102 static int xscale_mmu(struct target
*target
, int *enabled
)
3104 struct xscale_common
*xscale
= target_to_xscale(target
);
3106 if (target
->state
!= TARGET_HALTED
)
3108 LOG_ERROR("Target not halted");
3109 return ERROR_TARGET_INVALID
;
3111 *enabled
= xscale
->armv4_5_mmu
.mmu_enabled
;
3115 COMMAND_HANDLER(xscale_handle_mmu_command
)
3117 struct target
*target
= get_current_target(CMD_CTX
);
3118 struct xscale_common
*xscale
= target_to_xscale(target
);
3121 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3122 if (retval
!= ERROR_OK
)
3125 if (target
->state
!= TARGET_HALTED
)
3127 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3134 COMMAND_PARSE_ENABLE(CMD_ARGV
[0], enable
);
3136 xscale_enable_mmu_caches(target
, 1, 0, 0);
3138 xscale_disable_mmu_caches(target
, 1, 0, 0);
3139 xscale
->armv4_5_mmu
.mmu_enabled
= enable
;
3142 command_print(CMD_CTX
, "mmu %s", (xscale
->armv4_5_mmu
.mmu_enabled
) ? "enabled" : "disabled");
3147 COMMAND_HANDLER(xscale_handle_idcache_command
)
3149 struct target
*target
= get_current_target(CMD_CTX
);
3150 struct xscale_common
*xscale
= target_to_xscale(target
);
3152 int retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3153 if (retval
!= ERROR_OK
)
3156 if (target
->state
!= TARGET_HALTED
)
3158 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3163 COMMAND_PARSE_BOOL(CMD_NAME
, icache
, "icache", "dcache");
3168 COMMAND_PARSE_ENABLE(CMD_ARGV
[0], enable
);
3170 xscale_enable_mmu_caches(target
, 1, 0, 0);
3172 xscale_disable_mmu_caches(target
, 1, 0, 0);
3174 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= enable
;
3176 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= enable
;
3179 bool enabled
= icache
?
3180 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
:
3181 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
;
3182 const char *msg
= enabled
? "enabled" : "disabled";
3183 command_print(CMD_CTX
, "%s %s", CMD_NAME
, msg
);
3188 COMMAND_HANDLER(xscale_handle_vector_catch_command
)
3190 struct target
*target
= get_current_target(CMD_CTX
);
3191 struct xscale_common
*xscale
= target_to_xscale(target
);
3194 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3195 if (retval
!= ERROR_OK
)
3200 command_print(CMD_CTX
, "usage: xscale vector_catch [mask]");
3204 COMMAND_PARSE_NUMBER(u8
, CMD_ARGV
[0], xscale
->vector_catch
);
3205 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 8, xscale
->vector_catch
);
3206 xscale_write_dcsr(target
, -1, -1);
3209 command_print(CMD_CTX
, "vector catch mask: 0x%2.2x", xscale
->vector_catch
);
3215 COMMAND_HANDLER(xscale_handle_vector_table_command
)
3217 struct target
*target
= get_current_target(CMD_CTX
);
3218 struct xscale_common
*xscale
= target_to_xscale(target
);
3222 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3223 if (retval
!= ERROR_OK
)
3226 if (CMD_ARGC
== 0) /* print current settings */
3230 command_print(CMD_CTX
, "active user-set static vectors:");
3231 for (idx
= 1; idx
< 8; idx
++)
3232 if (xscale
->static_low_vectors_set
& (1 << idx
))
3233 command_print(CMD_CTX
, "low %d: 0x%" PRIx32
, idx
, xscale
->static_low_vectors
[idx
]);
3234 for (idx
= 1; idx
< 8; idx
++)
3235 if (xscale
->static_high_vectors_set
& (1 << idx
))
3236 command_print(CMD_CTX
, "high %d: 0x%" PRIx32
, idx
, xscale
->static_high_vectors
[idx
]);
3245 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[1], idx
);
3247 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], vec
);
3249 if (idx
< 1 || idx
>= 8)
3252 if (!err
&& strcmp(CMD_ARGV
[0], "low") == 0)
3254 xscale
->static_low_vectors_set
|= (1<<idx
);
3255 xscale
->static_low_vectors
[idx
] = vec
;
3257 else if (!err
&& (strcmp(CMD_ARGV
[0], "high") == 0))
3259 xscale
->static_high_vectors_set
|= (1<<idx
);
3260 xscale
->static_high_vectors
[idx
] = vec
;
3267 command_print(CMD_CTX
, "usage: xscale vector_table <high|low> <index> <code>");
3273 COMMAND_HANDLER(xscale_handle_trace_buffer_command
)
3275 struct target
*target
= get_current_target(CMD_CTX
);
3276 struct xscale_common
*xscale
= target_to_xscale(target
);
3277 struct armv4_5_common_s
*armv4_5
= &xscale
->armv4_5_common
;
3278 uint32_t dcsr_value
;
3281 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3282 if (retval
!= ERROR_OK
)
3285 if (target
->state
!= TARGET_HALTED
)
3287 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3291 if ((CMD_ARGC
>= 1) && (strcmp("enable", CMD_ARGV
[0]) == 0))
3293 struct xscale_trace_data
*td
, *next_td
;
3294 xscale
->trace
.buffer_enabled
= 1;
3296 /* free old trace data */
3297 td
= xscale
->trace
.data
;
3307 xscale
->trace
.data
= NULL
;
3309 else if ((CMD_ARGC
>= 1) && (strcmp("disable", CMD_ARGV
[0]) == 0))
3311 xscale
->trace
.buffer_enabled
= 0;
3314 if ((CMD_ARGC
>= 2) && (strcmp("fill", CMD_ARGV
[1]) == 0))
3318 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], fill
);
3319 xscale
->trace
.buffer_fill
= fill
;
3321 else if ((CMD_ARGC
>= 2) && (strcmp("wrap", CMD_ARGV
[1]) == 0))
3323 xscale
->trace
.buffer_fill
= -1;
3326 if (xscale
->trace
.buffer_enabled
)
3328 /* if we enable the trace buffer in fill-once
3329 * mode we know the address of the first instruction */
3330 xscale
->trace
.pc_ok
= 1;
3331 xscale
->trace
.current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
3335 /* otherwise the address is unknown, and we have no known good PC */
3336 xscale
->trace
.pc_ok
= 0;
3339 command_print(CMD_CTX
, "trace buffer %s (%s)",
3340 (xscale
->trace
.buffer_enabled
) ? "enabled" : "disabled",
3341 (xscale
->trace
.buffer_fill
> 0) ? "fill" : "wrap");
3343 dcsr_value
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32);
3344 if (xscale
->trace
.buffer_fill
>= 0)
3345 xscale_write_dcsr_sw(target
, (dcsr_value
& 0xfffffffc) | 2);
3347 xscale_write_dcsr_sw(target
, dcsr_value
& 0xfffffffc);
3352 COMMAND_HANDLER(xscale_handle_trace_image_command
)
3354 struct target
*target
= get_current_target(CMD_CTX
);
3355 struct xscale_common
*xscale
= target_to_xscale(target
);
3360 command_print(CMD_CTX
, "usage: xscale trace_image <file> [base address] [type]");
3364 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3365 if (retval
!= ERROR_OK
)
3368 if (xscale
->trace
.image
)
3370 image_close(xscale
->trace
.image
);
3371 free(xscale
->trace
.image
);
3372 command_print(CMD_CTX
, "previously loaded image found and closed");
3375 xscale
->trace
.image
= malloc(sizeof(struct image
));
3376 xscale
->trace
.image
->base_address_set
= 0;
3377 xscale
->trace
.image
->start_address_set
= 0;
3379 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3382 xscale
->trace
.image
->base_address_set
= 1;
3383 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[1], xscale
->trace
.image
->base_address
);
3387 xscale
->trace
.image
->base_address_set
= 0;
3390 if (image_open(xscale
->trace
.image
, CMD_ARGV
[0], (CMD_ARGC
>= 3) ? CMD_ARGV
[2] : NULL
) != ERROR_OK
)
3392 free(xscale
->trace
.image
);
3393 xscale
->trace
.image
= NULL
;
3400 COMMAND_HANDLER(xscale_handle_dump_trace_command
)
3402 struct target
*target
= get_current_target(CMD_CTX
);
3403 struct xscale_common
*xscale
= target_to_xscale(target
);
3404 struct xscale_trace_data
*trace_data
;
3408 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3409 if (retval
!= ERROR_OK
)
3412 if (target
->state
!= TARGET_HALTED
)
3414 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3420 command_print(CMD_CTX
, "usage: xscale dump_trace <file>");
3424 trace_data
= xscale
->trace
.data
;
3428 command_print(CMD_CTX
, "no trace data collected");
3432 if (fileio_open(&file
, CMD_ARGV
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
3441 fileio_write_u32(&file
, trace_data
->chkpt0
);
3442 fileio_write_u32(&file
, trace_data
->chkpt1
);
3443 fileio_write_u32(&file
, trace_data
->last_instruction
);
3444 fileio_write_u32(&file
, trace_data
->depth
);
3446 for (i
= 0; i
< trace_data
->depth
; i
++)
3447 fileio_write_u32(&file
, trace_data
->entries
[i
].data
| ((trace_data
->entries
[i
].type
& 0xffff) << 16));
3449 trace_data
= trace_data
->next
;
3452 fileio_close(&file
);
3457 COMMAND_HANDLER(xscale_handle_analyze_trace_buffer_command
)
3459 struct target
*target
= get_current_target(CMD_CTX
);
3460 struct xscale_common
*xscale
= target_to_xscale(target
);
3463 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3464 if (retval
!= ERROR_OK
)
3467 xscale_analyze_trace(target
, CMD_CTX
);
3472 COMMAND_HANDLER(xscale_handle_cp15
)
3474 struct target
*target
= get_current_target(CMD_CTX
);
3475 struct xscale_common
*xscale
= target_to_xscale(target
);
3478 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3479 if (retval
!= ERROR_OK
)
3482 if (target
->state
!= TARGET_HALTED
)
3484 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3487 uint32_t reg_no
= 0;
3488 struct reg
*reg
= NULL
;
3491 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], reg_no
);
3492 /*translate from xscale cp15 register no to openocd register*/
3496 reg_no
= XSCALE_MAINID
;
3499 reg_no
= XSCALE_CTRL
;
3502 reg_no
= XSCALE_TTB
;
3505 reg_no
= XSCALE_DAC
;
3508 reg_no
= XSCALE_FSR
;
3511 reg_no
= XSCALE_FAR
;
3514 reg_no
= XSCALE_PID
;
3517 reg_no
= XSCALE_CPACCESS
;
3520 command_print(CMD_CTX
, "invalid register number");
3521 return ERROR_INVALID_ARGUMENTS
;
3523 reg
= &xscale
->reg_cache
->reg_list
[reg_no
];
3530 /* read cp15 control register */
3531 xscale_get_reg(reg
);
3532 value
= buf_get_u32(reg
->value
, 0, 32);
3533 command_print(CMD_CTX
, "%s (/%i): 0x%" PRIx32
"", reg
->name
, (int)(reg
->size
), value
);
3535 else if (CMD_ARGC
== 2)
3538 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
3540 /* send CP write request (command 0x41) */
3541 xscale_send_u32(target
, 0x41);
3543 /* send CP register number */
3544 xscale_send_u32(target
, reg_no
);
3546 /* send CP register value */
3547 xscale_send_u32(target
, value
);
3549 /* execute cpwait to ensure outstanding operations complete */
3550 xscale_send_u32(target
, 0x53);
3554 command_print(CMD_CTX
, "usage: cp15 [register]<, [value]>");
3560 static int xscale_register_commands(struct command_context
*cmd_ctx
)
3562 struct command
*xscale_cmd
;
3564 xscale_cmd
= register_command(cmd_ctx
, NULL
, "xscale", NULL
, COMMAND_ANY
, "xscale specific commands");
3566 register_command(cmd_ctx
, xscale_cmd
, "debug_handler", xscale_handle_debug_handler_command
, COMMAND_ANY
, "'xscale debug_handler <target#> <address>' command takes two required operands");
3567 register_command(cmd_ctx
, xscale_cmd
, "cache_clean_address", xscale_handle_cache_clean_address_command
, COMMAND_ANY
, NULL
);
3569 register_command(cmd_ctx
, xscale_cmd
, "cache_info", xscale_handle_cache_info_command
, COMMAND_EXEC
, NULL
);
3570 register_command(cmd_ctx
, xscale_cmd
, "mmu", xscale_handle_mmu_command
, COMMAND_EXEC
, "['enable'|'disable'] the MMU");
3571 register_command(cmd_ctx
, xscale_cmd
, "icache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the ICache");
3572 register_command(cmd_ctx
, xscale_cmd
, "dcache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the DCache");
3574 register_command(cmd_ctx
, xscale_cmd
, "vector_catch", xscale_handle_vector_catch_command
, COMMAND_EXEC
, "<mask> of vectors that should be catched");
3575 register_command(cmd_ctx
, xscale_cmd
, "vector_table", xscale_handle_vector_table_command
, COMMAND_EXEC
, "<high|low> <index> <code> set static code for exception handler entry");
3577 register_command(cmd_ctx
, xscale_cmd
, "trace_buffer", xscale_handle_trace_buffer_command
, COMMAND_EXEC
, "<enable | disable> ['fill' [n]|'wrap']");
3579 register_command(cmd_ctx
, xscale_cmd
, "dump_trace", xscale_handle_dump_trace_command
, COMMAND_EXEC
, "dump content of trace buffer to <file>");
3580 register_command(cmd_ctx
, xscale_cmd
, "analyze_trace", xscale_handle_analyze_trace_buffer_command
, COMMAND_EXEC
, "analyze content of trace buffer");
3581 register_command(cmd_ctx
, xscale_cmd
, "trace_image", xscale_handle_trace_image_command
,
3582 COMMAND_EXEC
, "load image from <file> [base address]");
3584 register_command(cmd_ctx
, xscale_cmd
, "cp15", xscale_handle_cp15
, COMMAND_EXEC
, "access coproc 15 <register> [value]");
3586 armv4_5_register_commands(cmd_ctx
);
3591 struct target_type xscale_target
=
3595 .poll
= xscale_poll
,
3596 .arch_state
= xscale_arch_state
,
3598 .target_request_data
= NULL
,
3600 .halt
= xscale_halt
,
3601 .resume
= xscale_resume
,
3602 .step
= xscale_step
,
3604 .assert_reset
= xscale_assert_reset
,
3605 .deassert_reset
= xscale_deassert_reset
,
3606 .soft_reset_halt
= NULL
,
3608 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
3610 .read_memory
= xscale_read_memory
,
3611 .write_memory
= xscale_write_memory
,
3612 .bulk_write_memory
= xscale_bulk_write_memory
,
3614 .checksum_memory
= arm_checksum_memory
,
3615 .blank_check_memory
= arm_blank_check_memory
,
3617 .run_algorithm
= armv4_5_run_algorithm
,
3619 .add_breakpoint
= xscale_add_breakpoint
,
3620 .remove_breakpoint
= xscale_remove_breakpoint
,
3621 .add_watchpoint
= xscale_add_watchpoint
,
3622 .remove_watchpoint
= xscale_remove_watchpoint
,
3624 .register_commands
= xscale_register_commands
,
3625 .target_create
= xscale_target_create
,
3626 .init_target
= xscale_init_target
,
3628 .virt2phys
= xscale_virt2phys
,
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