src/target/x86_32_common.h

   1 /*
   2  * Copyright(c) 2013 Intel Corporation.
   3  *
   4  * Adrian Burns (adrian.burns@intel.com)
   5  * Thomas Faust (thomas.faust@intel.com)
   6  * Ivan De Cesaris (ivan.de.cesaris@intel.com)
   7  * Julien Carreno (julien.carreno@intel.com)
   8  * Jeffrey Maxwell (jeffrey.r.maxwell@intel.com)
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  23  *
  24  * Contact Information:
  25  * Intel Corporation
  26  */
  27
  28 /*
  29  * @file
  30  * This is the interface to the x86 32 bit memory and breakpoint operations.
  31  */
  32
  33 #ifndef X86_32_COMMON_H
  34 #define X86_32_COMMON_H
  35
  36 #include <jtag/jtag.h>
  37 #include <helper/command.h>
  38 #include <helper/types.h>
  39
  40 extern const struct command_registration x86_32_command_handlers[];
  41
  42 /* for memory access */
  43 #define BYTE                    1
  44 #define WORD                    2
  45 #define DWORD                   4
  46
  47 #define EFLAGS_TF               ((uint32_t)0x00000100) /* Trap Flag */
  48 #define EFLAGS_IF               ((uint32_t)0x00000200) /* Interrupt Flag */
  49 #define EFLAGS_RF               ((uint32_t)0x00010000) /* Resume Flag */
  50 #define EFLAGS_VM86             ((uint32_t)0x00020000) /* Virtual 8086 Mode */
  51
  52 #define CSAR_DPL                ((uint32_t)0x00006000)
  53 #define CSAR_D                  ((uint32_t)0x00400000)
  54 #define SSAR_DPL                ((uint32_t)0x00006000)
  55
  56 #define CR0_PE                  ((uint32_t)0x00000001) /* Protected Mode Enable */
  57 #define CR0_NW                  ((uint32_t)0x20000000) /* Non Write-Through */
  58 #define CR0_CD                  ((uint32_t)0x40000000) /* Cache Disable */
  59 #define CR0_PG                  ((uint32_t)0x80000000) /* Paging Enable */
  60
  61 /* TODO - move back to PM specific file */
  62 #define PM_DR6                  ((uint32_t)0xFFFF0FF0)
  63
  64 #define DR6_BRKDETECT_0         ((uint32_t)0x00000001) /* B0 through B3 */
  65 #define DR6_BRKDETECT_1         ((uint32_t)0x00000002) /* breakpoint condition detected */
  66 #define DR6_BRKDETECT_2         ((uint32_t)0x00000004)
  67 #define DR6_BRKDETECT_3         ((uint32_t)0x00000008)
  68
  69 enum {
  70         /* general purpose registers */
  71         EAX = 0,
  72         ECX,
  73         EDX,
  74         EBX,
  75         ESP,
  76         EBP,
  77         ESI,
  78         EDI,
  79         /* instruction pointer & flags */
  80         EIP,
  81         EFLAGS,
  82
  83         /* segment registers */
  84         CS,
  85         SS,
  86         DS,
  87         ES,
  88         FS,
  89         GS,
  90
  91         /* floating point unit registers */
  92         ST0,
  93         ST1,
  94         ST2,
  95         ST3,
  96         ST4,
  97         ST5,
  98         ST6,
  99         ST7,
 100         FCTRL,
 101         FSTAT,
 102         FTAG,
 103         FISEG,
 104         FIOFF,
 105         FOSEG,
 106         FOOFF,
 107         FOP,
 108
 109         /* control registers */
 110         CR0,
 111         CR2,
 112         CR3,
 113         CR4,
 114
 115         /* debug registers */
 116         DR0,
 117         DR1,
 118         DR2,
 119         DR3,
 120         DR6,
 121         DR7,
 122
 123         /* descriptor tables */
 124         IDTB,
 125         IDTL,
 126         IDTAR,
 127         GDTB,
 128         GDTL,
 129         GDTAR,
 130         TR,
 131         LDTR,
 132         LDTB,
 133         LDTL,
 134         LDTAR,
 135
 136         /* segment registers */
 137         CSB,
 138         CSL,
 139         CSAR,
 140         DSB,
 141         DSL,
 142         DSAR,
 143         ESB,
 144         ESL,
 145         ESAR,
 146         FSB,
 147         FSL,
 148         FSAR,
 149         GSB,
 150         GSL,
 151         GSAR,
 152         SSB,
 153         SSL,
 154         SSAR,
 155         TSSB,
 156         TSSL,
 157         TSSAR,
 158
 159         /* PM control reg */
 160         PMCR,
 161 };
 162
 163 #define X86_32_COMMON_MAGIC 0x86328632
 164
 165 enum {
 166         /* memory read/write */
 167         MEMRDB32 = 0,
 168         MEMRDB16,
 169         MEMRDH32,
 170         MEMRDH16,
 171         MEMRDW32,
 172         MEMRDW16,
 173         MEMWRB32,
 174         MEMWRB16,
 175         MEMWRH32,
 176         MEMWRH16,
 177         MEMWRW32,
 178         MEMWRW16,
 179         /* IO read/write */
 180         IORDB32,
 181         IORDB16,
 182         IORDH32,
 183         IORDH16,
 184         IORDW32,
 185         IORDW16,
 186         IOWRB32,
 187         IOWRB16,
 188         IOWRH32,
 189         IOWRH16,
 190         IOWRW32,
 191         IOWRW16,
 192         /* lakemont1 core shadow ram access opcodes */
 193         SRAMACCESS,
 194         SRAM2PDR,
 195         PDR2SRAM,
 196         WBINVD,
 197 };
 198
 199 struct swbp_mem_patch {
 200         uint8_t orig_byte;
 201         uint32_t swbp_unique_id;
 202         uint32_t physaddr;
 203         struct swbp_mem_patch *next;
 204 };
 205
 206 /* TODO - probemode specific - consider removing */
 207 #define NUM_PM_REGS             18 /* regs used in save/restore */
 208
 209 struct x86_32_common {
 210         uint32_t common_magic;
 211         void *arch_info;
 212         struct reg_cache *cache;
 213         struct jtag_tap *curr_tap;
 214         uint32_t stored_pc;
 215         int flush;
 216
 217         /* pm_regs are for probemode save/restore state */
 218         uint32_t pm_regs[NUM_PM_REGS];
 219
 220         /* working area for fastdata access */
 221         struct working_area *fast_data_area;
 222
 223         int num_hw_bpoints;
 224         struct x86_32_dbg_reg *hw_break_list;
 225         struct swbp_mem_patch *swbbp_mem_patch_list;
 226
 227         /* core probemode implementation dependent functions */
 228         uint8_t (*get_num_user_regs)(struct target *t);
 229         bool (*is_paging_enabled)(struct target *t);
 230         int (*disable_paging)(struct target *t);
 231         int (*enable_paging)(struct target *t);
 232         bool (*sw_bpts_supported)(struct target *t);
 233         int (*transaction_status)(struct target *t);
 234         int (*submit_instruction)(struct target *t, int num);
 235         int (*read_hw_reg)(struct target *t, int reg, uint32_t *regval, uint8_t cache);
 236         int (*write_hw_reg)(struct target *t, int reg,
 237                                 uint32_t regval, uint8_t cache);
 238
 239         /* register cache to processor synchronization */
 240         int (*read_hw_reg_to_cache)(struct target *target, int num);
 241         int (*write_hw_reg_from_cache)(struct target *target, int num);
 242 };
 243
 244 static inline struct x86_32_common *
 245 target_to_x86_32(struct target *target)
 246 {
 247         return target->arch_info;
 248 }
 249 bool check_not_halted(const struct target *t);
 250
 251 /* breakpoint defines */
 252 #define MAX_DEBUG_REGS          4
 253 #define SW_BP_OPCODE            0xf1
 254 #define MAX_SW_BPTS             20
 255
 256 struct x86_32_dbg_reg {
 257         int used;
 258         uint32_t bp_value;
 259 };
 260
 261 #define DR7_G_ENABLE_SHIFT              1
 262 #define DR7_ENABLE_SIZE                 2 /* 2 bits per debug reg */
 263 #define DR7_RW_SHIFT                    16
 264 #define DR7_LENGTH_SHIFT                18
 265 #define DR7_RW_LEN_SIZE                 4
 266 #define DR7_BP_EXECUTE                  0 /* 00 - only on instruction execution*/
 267 #define DR7_BP_WRITE                    1 /* 01 - only on data writes */
 268 /*#define DR7_RW_IORW                   2 UNSUPPORTED 10 - an I/O read and I/O write */
 269 #define DR7_BP_READWRITE                3 /* on data read or data write */
 270 #define DR7_BP_LENGTH_1                 0 /* 00 - 1 byte length */
 271 #define DR7_BP_LENGTH_2                 1 /* 01 - 2 byte length */
 272 #define DR7_BP_LENGTH_4                 3 /* 11 - 4 byte length */
 273
 274 #define DR7_GLOBAL_ENABLE(val, regnum) \
 275         (val |= (1 << (DR7_G_ENABLE_SHIFT + (DR7_ENABLE_SIZE * (regnum)))))
 276
 277 #define DR7_GLOBAL_DISABLE(val, regnum) \
 278         (val &= ~(3 << (DR7_ENABLE_SIZE * (regnum))))
 279
 280 #define DR7_BP_FREE(val, regnum) \
 281         ((val & (3 << (DR7_ENABLE_SIZE * (regnum)))) == 0)
 282
 283 #define DR7_RESET_RWLEN_BITS(val, regnum) \
 284         (val &= ~(0x0f << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
 285
 286 #define DR7_SET_EXE(val, regnum) \
 287         (val &= ~(0x0f << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
 288
 289 #define DR7_SET_WRITE(val, regnum) \
 290         (val |= (DR7_BP_WRITE << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
 291
 292 #define DR7_SET_ACCESS(val, regnum) \
 293         (val |= (DR7_BP_READWRITE << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
 294
 295 #define DR7_SET_LENGTH(val, regnum, len) \
 296         (val |= (len == 1) ? (DR7_BP_LENGTH_1 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))) : \
 297         (len == 2) ? (DR7_BP_LENGTH_2 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))) : \
 298         (DR7_BP_LENGTH_4 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
 299
 300 /* public interface */
 301 int x86_32_get_gdb_reg_list(struct target *t,
 302                         struct reg **reg_list[], int *reg_list_size,
 303                         enum target_register_class reg_class);
 304 int x86_32_common_init_arch_info(struct target *target,
 305                         struct x86_32_common *x86_32);
 306 int x86_32_common_mmu(struct target *t, int *enabled);
 307 int x86_32_common_virt2phys(struct target *t, uint32_t address, uint32_t *physical);
 308 int x86_32_common_read_phys_mem(struct target *t, uint32_t phys_address,
 309                         uint32_t size, uint32_t count, uint8_t *buffer);
 310 int x86_32_common_write_phys_mem(struct target *t, uint32_t phys_address,
 311                         uint32_t size, uint32_t count, const uint8_t *buffer);
 312 int x86_32_common_read_memory(struct target *t, uint32_t addr,
 313                         uint32_t size, uint32_t count, uint8_t *buf);
 314 int x86_32_common_write_memory(struct target *t, uint32_t addr,
 315                         uint32_t size, uint32_t count, const uint8_t *buf);
 316 int x86_32_common_read_io(struct target *t, uint32_t addr,
 317                         uint32_t size, uint8_t *buf);
 318 int x86_32_common_write_io(struct target *t, uint32_t addr,
 319                         uint32_t size, const uint8_t *buf);
 320 int x86_32_common_add_breakpoint(struct target *t, struct breakpoint *bp);
 321 int x86_32_common_remove_breakpoint(struct target *t, struct breakpoint *bp);
 322 int x86_32_common_add_watchpoint(struct target *t, struct watchpoint *wp);
 323 int x86_32_common_remove_watchpoint(struct target *t, struct watchpoint *wp);
 324
 325 #endif /* X86_32_COMMON_H */