src/target/target/stm32.cfg

   1 # script for stm32
   2
   3 if { [info exists CHIPNAME] } {
   4    set  _CHIPNAME $CHIPNAME
   5 } else {
   6    set  _CHIPNAME stm32
   7 }
   8
   9 if { [info exists ENDIAN] } {
  10    set  _ENDIAN $ENDIAN
  11 } else {
  12    set  _ENDIAN little
  13 }
  14
  15
  16 # jtag speed
  17 jtag_khz 500
  18
  19 jtag_nsrst_delay 100
  20 jtag_ntrst_delay 100
  21
  22 #use combined on interfaces or targets that can't set TRST/SRST separately
  23 reset_config trst_and_srst
  24
  25 #jtag scan chain
  26 if { [info exists CPUTAPID ] } {
  27    set _CPUTAPID $CPUTAPID
  28 } else {
  29   # See STM Document RM0008
  30   # Section 26.6.3
  31    set _CPUTAPID 0x3ba00477
  32 }
  33 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  34
  35 if { [info exists BSTAPID ] } {
  36    set _BSTAPID $BSTAPID
  37 } else {
  38   # See STM Document RM0008
  39   # Section 26.6.2
  40   # Medium Density RevA
  41   set _BSTAPID 0x06410041
  42   # Rev B and Rev Z
  43   set _BSTAPID 0x16410041
  44   # High Density Devices, Rev A
  45   set _BSTAPID 0x06414041
  46 }
  47 jtag newtap $_CHIPNAME bs  -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
  48
  49 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
  50 target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
  51
  52 $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
  53
  54
  55 flash bank stm32x 0 0 0 0 0
  56
  57 # For more information about the configuration files, take a look at:
  58 # openocd.texi