9 #include "target/target.h"
10 #include "target/algorithm.h"
11 #include "target/target_type.h"
13 #include "jtag/jtag.h"
14 #include "target/register.h"
15 #include "target/breakpoints.h"
16 #include "helper/time_support.h"
19 #include "rtos/rtos.h"
22 * Since almost everything can be accomplish by scanning the dbus register, all
23 * functions here assume dbus is already selected. The exception are functions
24 * called directly by OpenOCD, which can't assume anything about what's
25 * currently in IR. They should set IR to dbus explicitly.
31 * At the bottom of the stack are the OpenOCD JTAG functions:
36 * There are a few functions to just instantly shift a register and get its
42 * Because doing one scan and waiting for the result is slow, most functions
43 * batch up a bunch of dbus writes and then execute them all at once. They use
44 * the scans "class" for this:
49 * Usually you new(), call a bunch of add functions, then execute() and look
50 * at the results by calling scans_get...()
52 * Optimized functions will directly use the scans class above, but slightly
53 * lazier code will use the cache functions that in turn use the scans
58 * cache_set... update a local structure, which is then synced to the target
59 * with cache_write(). Only Debug RAM words that are actually changed are sent
60 * to the target. Afterwards use cache_get... to read results.
63 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
64 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
66 #define DIM(x) (sizeof(x)/sizeof(*x))
68 /* Constants for legacy SiFive hardware breakpoints. */
69 #define CSR_BPCONTROL_X (1<<0)
70 #define CSR_BPCONTROL_W (1<<1)
71 #define CSR_BPCONTROL_R (1<<2)
72 #define CSR_BPCONTROL_U (1<<3)
73 #define CSR_BPCONTROL_S (1<<4)
74 #define CSR_BPCONTROL_H (1<<5)
75 #define CSR_BPCONTROL_M (1<<6)
76 #define CSR_BPCONTROL_BPMATCH (0xf<<7)
77 #define CSR_BPCONTROL_BPACTION (0xff<<11)
79 #define DEBUG_ROM_START 0x800
80 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
81 #define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
82 #define DEBUG_RAM_START 0x400
84 #define SETHALTNOT 0x10c
86 /*** JTAG registers. ***/
88 #define DTMCONTROL 0x10
89 #define DTMCONTROL_DBUS_RESET (1<<16)
90 #define DTMCONTROL_IDLE (7<<10)
91 #define DTMCONTROL_ADDRBITS (0xf<<4)
92 #define DTMCONTROL_VERSION (0xf)
95 #define DBUS_OP_START 0
96 #define DBUS_OP_SIZE 2
103 DBUS_STATUS_SUCCESS
= 0,
104 DBUS_STATUS_FAILED
= 2,
107 #define DBUS_DATA_START 2
108 #define DBUS_DATA_SIZE 34
109 #define DBUS_ADDRESS_START 36
123 /*** Debug Bus registers. ***/
125 #define DMCONTROL 0x10
126 #define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
127 #define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
128 #define DMCONTROL_BUSERROR (7<<19)
129 #define DMCONTROL_SERIAL (3<<16)
130 #define DMCONTROL_AUTOINCREMENT (1<<15)
131 #define DMCONTROL_ACCESS (7<<12)
132 #define DMCONTROL_HARTID (0x3ff<<2)
133 #define DMCONTROL_NDRESET (1<<1)
134 #define DMCONTROL_FULLRESET 1
137 #define DMINFO_ABUSSIZE (0x7fU<<25)
138 #define DMINFO_SERIALCOUNT (0xf<<21)
139 #define DMINFO_ACCESS128 (1<<20)
140 #define DMINFO_ACCESS64 (1<<19)
141 #define DMINFO_ACCESS32 (1<<18)
142 #define DMINFO_ACCESS16 (1<<17)
143 #define DMINFO_ACCESS8 (1<<16)
144 #define DMINFO_DRAMSIZE (0x3f<<10)
145 #define DMINFO_AUTHENTICATED (1<<5)
146 #define DMINFO_AUTHBUSY (1<<4)
147 #define DMINFO_AUTHTYPE (3<<2)
148 #define DMINFO_VERSION 3
150 /*** Info about the core being debugged. ***/
152 #define DBUS_ADDRESS_UNKNOWN 0xffff
155 #define DRAM_CACHE_SIZE 16
157 uint8_t ir_dtmcontrol
[4] = {DTMCONTROL
};
158 struct scan_field select_dtmcontrol
= {
160 .out_value
= ir_dtmcontrol
162 uint8_t ir_dbus
[4] = {DBUS
};
163 struct scan_field select_dbus
= {
167 uint8_t ir_idcode
[4] = {0x1};
168 struct scan_field select_idcode
= {
170 .out_value
= ir_idcode
178 bool read
, write
, execute
;
182 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
183 int riscv_command_timeout_sec
= DEFAULT_COMMAND_TIMEOUT_SEC
;
185 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
186 int riscv_reset_timeout_sec
= DEFAULT_RESET_TIMEOUT_SEC
;
188 bool riscv_prefer_sba
;
194 /* In addition to the ones in the standard spec, we'll also expose additional
196 * The list is either NULL, or a series of ranges (inclusive), terminated with
199 /* Same, but for custom registers. */
200 range_t
*expose_custom
;
202 static uint32_t dtmcontrol_scan(struct target
*target
, uint32_t out
)
204 struct scan_field field
;
206 uint8_t out_value
[4];
208 buf_set_u32(out_value
, 0, 32, out
);
210 jtag_add_ir_scan(target
->tap
, &select_dtmcontrol
, TAP_IDLE
);
213 field
.out_value
= out_value
;
214 field
.in_value
= in_value
;
215 jtag_add_dr_scan(target
->tap
, 1, &field
, TAP_IDLE
);
217 /* Always return to dbus. */
218 jtag_add_ir_scan(target
->tap
, &select_dbus
, TAP_IDLE
);
220 int retval
= jtag_execute_queue();
221 if (retval
!= ERROR_OK
) {
222 LOG_ERROR("failed jtag scan: %d", retval
);
226 uint32_t in
= buf_get_u32(field
.in_value
, 0, 32);
227 LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out
, in
);
232 static struct target_type
*get_target_type(struct target
*target
)
234 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
237 LOG_ERROR("Target has not been initialized");
241 switch (info
->dtm_version
) {
243 return &riscv011_target
;
245 return &riscv013_target
;
247 LOG_ERROR("Unsupported DTM version: %d", info
->dtm_version
);
252 static int riscv_init_target(struct command_context
*cmd_ctx
,
253 struct target
*target
)
255 LOG_DEBUG("riscv_init_target()");
256 target
->arch_info
= calloc(1, sizeof(riscv_info_t
));
257 if (!target
->arch_info
)
259 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
260 riscv_info_init(target
, info
);
261 info
->cmd_ctx
= cmd_ctx
;
263 select_dtmcontrol
.num_bits
= target
->tap
->ir_length
;
264 select_dbus
.num_bits
= target
->tap
->ir_length
;
265 select_idcode
.num_bits
= target
->tap
->ir_length
;
267 riscv_semihosting_init(target
);
269 target
->debug_reason
= DBG_REASON_DBGRQ
;
274 static void riscv_deinit_target(struct target
*target
)
276 LOG_DEBUG("riscv_deinit_target()");
277 struct target_type
*tt
= get_target_type(target
);
279 tt
->deinit_target(target
);
280 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
281 free(info
->reg_names
);
284 /* Free the shared structure use for most registers. */
285 if (target
->reg_cache
) {
286 if (target
->reg_cache
->reg_list
) {
287 if (target
->reg_cache
->reg_list
[0].arch_info
)
288 free(target
->reg_cache
->reg_list
[0].arch_info
);
289 /* Free the ones we allocated separately. */
290 for (unsigned i
= GDB_REGNO_COUNT
; i
< target
->reg_cache
->num_regs
; i
++)
291 free(target
->reg_cache
->reg_list
[i
].arch_info
);
292 free(target
->reg_cache
->reg_list
);
294 free(target
->reg_cache
);
296 target
->arch_info
= NULL
;
299 static int oldriscv_halt(struct target
*target
)
301 struct target_type
*tt
= get_target_type(target
);
302 return tt
->halt(target
);
305 static void trigger_from_breakpoint(struct trigger
*trigger
,
306 const struct breakpoint
*breakpoint
)
308 trigger
->address
= breakpoint
->address
;
309 trigger
->length
= breakpoint
->length
;
310 trigger
->mask
= ~0LL;
311 trigger
->read
= false;
312 trigger
->write
= false;
313 trigger
->execute
= true;
314 /* unique_id is unique across both breakpoints and watchpoints. */
315 trigger
->unique_id
= breakpoint
->unique_id
;
318 static int maybe_add_trigger_t1(struct target
*target
, unsigned hartid
,
319 struct trigger
*trigger
, uint64_t tdata1
)
323 const uint32_t bpcontrol_x
= 1<<0;
324 const uint32_t bpcontrol_w
= 1<<1;
325 const uint32_t bpcontrol_r
= 1<<2;
326 const uint32_t bpcontrol_u
= 1<<3;
327 const uint32_t bpcontrol_s
= 1<<4;
328 const uint32_t bpcontrol_h
= 1<<5;
329 const uint32_t bpcontrol_m
= 1<<6;
330 const uint32_t bpcontrol_bpmatch
= 0xf << 7;
331 const uint32_t bpcontrol_bpaction
= 0xff << 11;
333 if (tdata1
& (bpcontrol_r
| bpcontrol_w
| bpcontrol_x
)) {
334 /* Trigger is already in use, presumably by user code. */
335 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
338 tdata1
= set_field(tdata1
, bpcontrol_r
, trigger
->read
);
339 tdata1
= set_field(tdata1
, bpcontrol_w
, trigger
->write
);
340 tdata1
= set_field(tdata1
, bpcontrol_x
, trigger
->execute
);
341 tdata1
= set_field(tdata1
, bpcontrol_u
,
342 !!(r
->misa
[hartid
] & (1 << ('U' - 'A'))));
343 tdata1
= set_field(tdata1
, bpcontrol_s
,
344 !!(r
->misa
[hartid
] & (1 << ('S' - 'A'))));
345 tdata1
= set_field(tdata1
, bpcontrol_h
,
346 !!(r
->misa
[hartid
] & (1 << ('H' - 'A'))));
347 tdata1
|= bpcontrol_m
;
348 tdata1
= set_field(tdata1
, bpcontrol_bpmatch
, 0); /* exact match */
349 tdata1
= set_field(tdata1
, bpcontrol_bpaction
, 0); /* cause bp exception */
351 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, tdata1
);
353 riscv_reg_t tdata1_rb
;
354 if (riscv_get_register_on_hart(target
, &tdata1_rb
, hartid
,
355 GDB_REGNO_TDATA1
) != ERROR_OK
)
357 LOG_DEBUG("tdata1=0x%" PRIx64
, tdata1_rb
);
359 if (tdata1
!= tdata1_rb
) {
360 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
361 PRIx64
" to tdata1 it contains 0x%" PRIx64
,
363 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
364 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
367 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA2
, trigger
->address
);
372 static int maybe_add_trigger_t2(struct target
*target
, unsigned hartid
,
373 struct trigger
*trigger
, uint64_t tdata1
)
377 /* tselect is already set */
378 if (tdata1
& (MCONTROL_EXECUTE
| MCONTROL_STORE
| MCONTROL_LOAD
)) {
379 /* Trigger is already in use, presumably by user code. */
380 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
383 /* address/data match trigger */
384 tdata1
|= MCONTROL_DMODE(riscv_xlen(target
));
385 tdata1
= set_field(tdata1
, MCONTROL_ACTION
,
386 MCONTROL_ACTION_DEBUG_MODE
);
387 tdata1
= set_field(tdata1
, MCONTROL_MATCH
, MCONTROL_MATCH_EQUAL
);
388 tdata1
|= MCONTROL_M
;
389 if (r
->misa
[hartid
] & (1 << ('H' - 'A')))
390 tdata1
|= MCONTROL_H
;
391 if (r
->misa
[hartid
] & (1 << ('S' - 'A')))
392 tdata1
|= MCONTROL_S
;
393 if (r
->misa
[hartid
] & (1 << ('U' - 'A')))
394 tdata1
|= MCONTROL_U
;
396 if (trigger
->execute
)
397 tdata1
|= MCONTROL_EXECUTE
;
399 tdata1
|= MCONTROL_LOAD
;
401 tdata1
|= MCONTROL_STORE
;
403 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, tdata1
);
406 int result
= riscv_get_register_on_hart(target
, &tdata1_rb
, hartid
, GDB_REGNO_TDATA1
);
407 if (result
!= ERROR_OK
)
409 LOG_DEBUG("tdata1=0x%" PRIx64
, tdata1_rb
);
411 if (tdata1
!= tdata1_rb
) {
412 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
413 PRIx64
" to tdata1 it contains 0x%" PRIx64
,
415 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
416 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
419 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA2
, trigger
->address
);
424 static int add_trigger(struct target
*target
, struct trigger
*trigger
)
428 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
431 /* In RTOS mode, we need to set the same trigger in the same slot on every
432 * hart, to keep up the illusion that each hart is a thread running on the
435 /* Otherwise, we just set the trigger on the one hart this target deals
438 riscv_reg_t tselect
[RISCV_MAX_HARTS
];
441 for (int hartid
= 0; hartid
< riscv_count_harts(target
); ++hartid
) {
442 if (!riscv_hart_enabled(target
, hartid
))
446 int result
= riscv_get_register_on_hart(target
, &tselect
[hartid
],
447 hartid
, GDB_REGNO_TSELECT
);
448 if (result
!= ERROR_OK
)
451 assert(first_hart
>= 0);
454 for (i
= 0; i
< r
->trigger_count
[first_hart
]; i
++) {
455 if (r
->trigger_unique_id
[i
] != -1)
458 riscv_set_register_on_hart(target
, first_hart
, GDB_REGNO_TSELECT
, i
);
461 int result
= riscv_get_register_on_hart(target
, &tdata1
, first_hart
,
463 if (result
!= ERROR_OK
)
465 int type
= get_field(tdata1
, MCONTROL_TYPE(riscv_xlen(target
)));
468 for (int hartid
= first_hart
; hartid
< riscv_count_harts(target
); ++hartid
) {
469 if (!riscv_hart_enabled(target
, hartid
))
471 if (hartid
> first_hart
)
472 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, i
);
475 result
= maybe_add_trigger_t1(target
, hartid
, trigger
, tdata1
);
478 result
= maybe_add_trigger_t2(target
, hartid
, trigger
, tdata1
);
481 LOG_DEBUG("trigger %d has unknown type %d", i
, type
);
485 if (result
!= ERROR_OK
)
489 if (result
!= ERROR_OK
)
492 LOG_DEBUG("[%d] Using trigger %d (type %d) for bp %d", target
->coreid
,
493 i
, type
, trigger
->unique_id
);
494 r
->trigger_unique_id
[i
] = trigger
->unique_id
;
498 for (int hartid
= first_hart
; hartid
< riscv_count_harts(target
); ++hartid
) {
499 if (!riscv_hart_enabled(target
, hartid
))
501 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
,
505 if (i
>= r
->trigger_count
[first_hart
]) {
506 LOG_ERROR("Couldn't find an available hardware trigger.");
507 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
513 int riscv_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
515 LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR
, target
->coreid
, breakpoint
->address
);
517 if (breakpoint
->type
== BKPT_SOFT
) {
518 /** @todo check RVC for size/alignment */
519 if (!(breakpoint
->length
== 4 || breakpoint
->length
== 2)) {
520 LOG_ERROR("Invalid breakpoint length %d", breakpoint
->length
);
524 if (0 != (breakpoint
->address
% 2)) {
525 LOG_ERROR("Invalid breakpoint alignment for address 0x%" TARGET_PRIxADDR
, breakpoint
->address
);
529 if (target_read_memory(target
, breakpoint
->address
, 2, breakpoint
->length
/ 2,
530 breakpoint
->orig_instr
) != ERROR_OK
) {
531 LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR
,
532 breakpoint
->address
);
537 buf_set_u32(buff
, 0, breakpoint
->length
* CHAR_BIT
, breakpoint
->length
== 4 ? ebreak() : ebreak_c());
538 int const retval
= target_write_memory(target
, breakpoint
->address
, 2, breakpoint
->length
/ 2, buff
);
540 if (retval
!= ERROR_OK
) {
541 LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%"
542 TARGET_PRIxADDR
, breakpoint
->length
, breakpoint
->address
);
546 } else if (breakpoint
->type
== BKPT_HARD
) {
547 struct trigger trigger
;
548 trigger_from_breakpoint(&trigger
, breakpoint
);
549 int const result
= add_trigger(target
, &trigger
);
550 if (result
!= ERROR_OK
)
553 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
554 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
557 breakpoint
->set
= true;
561 static int remove_trigger(struct target
*target
, struct trigger
*trigger
)
565 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
569 for (int hartid
= 0; hartid
< riscv_count_harts(target
); ++hartid
) {
570 if (!riscv_hart_enabled(target
, hartid
))
572 if (first_hart
< 0) {
577 assert(first_hart
>= 0);
580 for (i
= 0; i
< r
->trigger_count
[first_hart
]; i
++) {
581 if (r
->trigger_unique_id
[i
] == trigger
->unique_id
)
584 if (i
>= r
->trigger_count
[first_hart
]) {
585 LOG_ERROR("Couldn't find the hardware resources used by hardware "
589 LOG_DEBUG("[%d] Stop using resource %d for bp %d", target
->coreid
, i
,
591 for (int hartid
= first_hart
; hartid
< riscv_count_harts(target
); ++hartid
) {
592 if (!riscv_hart_enabled(target
, hartid
))
595 int result
= riscv_get_register_on_hart(target
, &tselect
, hartid
, GDB_REGNO_TSELECT
);
596 if (result
!= ERROR_OK
)
598 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, i
);
599 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
600 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, tselect
);
602 r
->trigger_unique_id
[i
] = -1;
607 int riscv_remove_breakpoint(struct target
*target
,
608 struct breakpoint
*breakpoint
)
610 if (breakpoint
->type
== BKPT_SOFT
) {
611 if (target_write_memory(target
, breakpoint
->address
, 2, breakpoint
->length
/ 2,
612 breakpoint
->orig_instr
) != ERROR_OK
) {
613 LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
614 "0x%" TARGET_PRIxADDR
, breakpoint
->length
, breakpoint
->address
);
618 } else if (breakpoint
->type
== BKPT_HARD
) {
619 struct trigger trigger
;
620 trigger_from_breakpoint(&trigger
, breakpoint
);
621 int result
= remove_trigger(target
, &trigger
);
622 if (result
!= ERROR_OK
)
626 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
627 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
630 breakpoint
->set
= false;
635 static void trigger_from_watchpoint(struct trigger
*trigger
,
636 const struct watchpoint
*watchpoint
)
638 trigger
->address
= watchpoint
->address
;
639 trigger
->length
= watchpoint
->length
;
640 trigger
->mask
= watchpoint
->mask
;
641 trigger
->value
= watchpoint
->value
;
642 trigger
->read
= (watchpoint
->rw
== WPT_READ
|| watchpoint
->rw
== WPT_ACCESS
);
643 trigger
->write
= (watchpoint
->rw
== WPT_WRITE
|| watchpoint
->rw
== WPT_ACCESS
);
644 trigger
->execute
= false;
645 /* unique_id is unique across both breakpoints and watchpoints. */
646 trigger
->unique_id
= watchpoint
->unique_id
;
649 int riscv_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
651 struct trigger trigger
;
652 trigger_from_watchpoint(&trigger
, watchpoint
);
654 int result
= add_trigger(target
, &trigger
);
655 if (result
!= ERROR_OK
)
657 watchpoint
->set
= true;
662 int riscv_remove_watchpoint(struct target
*target
,
663 struct watchpoint
*watchpoint
)
665 LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR
, target
->coreid
, watchpoint
->address
);
667 struct trigger trigger
;
668 trigger_from_watchpoint(&trigger
, watchpoint
);
670 int result
= remove_trigger(target
, &trigger
);
671 if (result
!= ERROR_OK
)
673 watchpoint
->set
= false;
678 /* Sets *hit_watchpoint to the first watchpoint identified as causing the
681 * The GDB server uses this information to tell GDB what data address has
682 * been hit, which enables GDB to print the hit variable along with its old
684 int riscv_hit_watchpoint(struct target
*target
, struct watchpoint
**hit_watchpoint
)
686 struct watchpoint
*wp
= target
->watchpoints
;
688 LOG_DEBUG("Current hartid = %d", riscv_current_hartid(target
));
690 /*TODO instead of disassembling the instruction that we think caused the
691 * trigger, check the hit bit of each watchpoint first. The hit bit is
692 * simpler and more reliable to check but as it is optional and relatively
693 * new, not all hardware will implement it */
695 riscv_get_register(target
, &dpc
, GDB_REGNO_DPC
);
696 const uint8_t length
= 4;
697 LOG_DEBUG("dpc is 0x%" PRIx64
, dpc
);
699 /* fetch the instruction at dpc */
700 uint8_t buffer
[length
];
701 if (target_read_buffer(target
, dpc
, length
, buffer
) != ERROR_OK
) {
702 LOG_ERROR("Failed to read instruction at dpc 0x%" PRIx64
, dpc
);
706 uint32_t instruction
= 0;
708 for (int i
= 0; i
< length
; i
++) {
709 LOG_DEBUG("Next byte is %x", buffer
[i
]);
710 instruction
+= (buffer
[i
] << 8 * i
);
712 LOG_DEBUG("Full instruction is %x", instruction
);
714 /* find out which memory address is accessed by the instruction at dpc */
715 /* opcode is first 7 bits of the instruction */
716 uint8_t opcode
= instruction
& 0x7F;
719 riscv_reg_t mem_addr
;
721 if (opcode
== MATCH_LB
|| opcode
== MATCH_SB
) {
722 rs1
= (instruction
& 0xf8000) >> 15;
723 riscv_get_register(target
, &mem_addr
, rs1
);
725 if (opcode
== MATCH_SB
) {
726 LOG_DEBUG("%x is store instruction", instruction
);
727 imm
= ((instruction
& 0xf80) >> 7) | ((instruction
& 0xfe000000) >> 20);
729 LOG_DEBUG("%x is load instruction", instruction
);
730 imm
= (instruction
& 0xfff00000) >> 20;
732 /* sign extend 12-bit imm to 16-bits */
736 LOG_DEBUG("memory address=0x%" PRIx64
, mem_addr
);
738 LOG_DEBUG("%x is not a RV32I load or store", instruction
);
743 /*TODO support length/mask */
744 if (wp
->address
== mem_addr
) {
745 *hit_watchpoint
= wp
;
746 LOG_DEBUG("Hit address=%" TARGET_PRIxADDR
, wp
->address
);
752 /* No match found - either we hit a watchpoint caused by an instruction that
753 * this function does not yet disassemble, or we hit a breakpoint.
755 * OpenOCD will behave as if this function had never been implemented i.e.
756 * report the halt to GDB with no address information. */
761 static int oldriscv_step(struct target
*target
, int current
, uint32_t address
,
762 int handle_breakpoints
)
764 struct target_type
*tt
= get_target_type(target
);
765 return tt
->step(target
, current
, address
, handle_breakpoints
);
768 static int old_or_new_riscv_step(
769 struct target
*target
,
771 target_addr_t address
,
772 int handle_breakpoints
775 LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints
);
776 if (r
->is_halted
== NULL
)
777 return oldriscv_step(target
, current
, address
, handle_breakpoints
);
779 return riscv_openocd_step(target
, current
, address
, handle_breakpoints
);
783 static int riscv_examine(struct target
*target
)
785 LOG_DEBUG("riscv_examine()");
786 if (target_was_examined(target
)) {
787 LOG_DEBUG("Target was already examined.");
791 /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
793 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
794 uint32_t dtmcontrol
= dtmcontrol_scan(target
, 0);
795 LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol
);
796 info
->dtm_version
= get_field(dtmcontrol
, DTMCONTROL_VERSION
);
797 LOG_DEBUG(" version=0x%x", info
->dtm_version
);
799 struct target_type
*tt
= get_target_type(target
);
803 int result
= tt
->init_target(info
->cmd_ctx
, target
);
804 if (result
!= ERROR_OK
)
807 return tt
->examine(target
);
810 static int oldriscv_poll(struct target
*target
)
812 struct target_type
*tt
= get_target_type(target
);
813 return tt
->poll(target
);
816 static int old_or_new_riscv_poll(struct target
*target
)
819 if (r
->is_halted
== NULL
)
820 return oldriscv_poll(target
);
822 return riscv_openocd_poll(target
);
825 static int old_or_new_riscv_halt(struct target
*target
)
828 if (r
->is_halted
== NULL
)
829 return oldriscv_halt(target
);
831 return riscv_openocd_halt(target
);
834 static int riscv_assert_reset(struct target
*target
)
836 LOG_DEBUG("[%d]", target
->coreid
);
837 struct target_type
*tt
= get_target_type(target
);
838 riscv_invalidate_register_cache(target
);
839 return tt
->assert_reset(target
);
842 static int riscv_deassert_reset(struct target
*target
)
844 LOG_DEBUG("[%d]", target
->coreid
);
845 struct target_type
*tt
= get_target_type(target
);
846 return tt
->deassert_reset(target
);
850 static int oldriscv_resume(struct target
*target
, int current
, uint32_t address
,
851 int handle_breakpoints
, int debug_execution
)
853 struct target_type
*tt
= get_target_type(target
);
854 return tt
->resume(target
, current
, address
, handle_breakpoints
,
858 static int old_or_new_riscv_resume(
859 struct target
*target
,
861 target_addr_t address
,
862 int handle_breakpoints
,
865 LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints
);
867 struct target_list
*targets
= target
->head
;
868 int result
= ERROR_OK
;
870 struct target
*t
= targets
->target
;
871 riscv_info_t
*r
= riscv_info(t
);
872 if (r
->is_halted
== NULL
) {
873 if (oldriscv_resume(t
, current
, address
, handle_breakpoints
,
874 debug_execution
) != ERROR_OK
)
877 if (riscv_openocd_resume(t
, current
, address
,
878 handle_breakpoints
, debug_execution
) != ERROR_OK
)
881 targets
= targets
->next
;
887 if (r
->is_halted
== NULL
)
888 return oldriscv_resume(target
, current
, address
, handle_breakpoints
, debug_execution
);
890 return riscv_openocd_resume(target
, current
, address
, handle_breakpoints
, debug_execution
);
893 static int riscv_select_current_hart(struct target
*target
)
896 if (riscv_rtos_enabled(target
)) {
897 if (r
->rtos_hartid
== -1)
898 r
->rtos_hartid
= target
->rtos
->current_threadid
- 1;
899 return riscv_set_current_hartid(target
, r
->rtos_hartid
);
901 return riscv_set_current_hartid(target
, target
->coreid
);
904 static int riscv_read_memory(struct target
*target
, target_addr_t address
,
905 uint32_t size
, uint32_t count
, uint8_t *buffer
)
907 if (riscv_select_current_hart(target
) != ERROR_OK
)
909 struct target_type
*tt
= get_target_type(target
);
910 return tt
->read_memory(target
, address
, size
, count
, buffer
);
913 static int riscv_write_memory(struct target
*target
, target_addr_t address
,
914 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
916 if (riscv_select_current_hart(target
) != ERROR_OK
)
918 struct target_type
*tt
= get_target_type(target
);
919 return tt
->write_memory(target
, address
, size
, count
, buffer
);
922 static int riscv_get_gdb_reg_list_internal(struct target
*target
,
923 struct reg
**reg_list
[], int *reg_list_size
,
924 enum target_register_class reg_class
, bool read
)
927 LOG_DEBUG("rtos_hartid=%d, current_hartid=%d, reg_class=%d, read=%d",
928 r
->rtos_hartid
, r
->current_hartid
, reg_class
, read
);
930 if (!target
->reg_cache
) {
931 LOG_ERROR("Target not initialized. Return ERROR_FAIL.");
935 if (riscv_select_current_hart(target
) != ERROR_OK
)
939 case REG_CLASS_GENERAL
:
943 *reg_list_size
= target
->reg_cache
->num_regs
;
946 LOG_ERROR("Unsupported reg_class: %d", reg_class
);
950 *reg_list
= calloc(*reg_list_size
, sizeof(struct reg
*));
954 for (int i
= 0; i
< *reg_list_size
; i
++) {
955 assert(!target
->reg_cache
->reg_list
[i
].valid
||
956 target
->reg_cache
->reg_list
[i
].size
> 0);
957 (*reg_list
)[i
] = &target
->reg_cache
->reg_list
[i
];
958 if (read
&& !target
->reg_cache
->reg_list
[i
].valid
) {
959 if (target
->reg_cache
->reg_list
[i
].type
->get(
960 &target
->reg_cache
->reg_list
[i
]) != ERROR_OK
)
961 /* This function is called when first connecting to gdb,
962 * resulting in an attempt to read all kinds of registers which
963 * probably will fail. Ignore these failures, and when
964 * encountered stop reading to save time. */
972 static int riscv_get_gdb_reg_list(struct target
*target
,
973 struct reg
**reg_list
[], int *reg_list_size
,
974 enum target_register_class reg_class
)
976 return riscv_get_gdb_reg_list_internal(target
, reg_list
, reg_list_size
,
980 static int riscv_arch_state(struct target
*target
)
982 struct target_type
*tt
= get_target_type(target
);
983 return tt
->arch_state(target
);
986 /* Algorithm must end with a software breakpoint instruction. */
987 static int riscv_run_algorithm(struct target
*target
, int num_mem_params
,
988 struct mem_param
*mem_params
, int num_reg_params
,
989 struct reg_param
*reg_params
, target_addr_t entry_point
,
990 target_addr_t exit_point
, int timeout_ms
, void *arch_info
)
992 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
994 if (num_mem_params
> 0) {
995 LOG_ERROR("Memory parameters are not supported for RISC-V algorithms.");
999 if (target
->state
!= TARGET_HALTED
) {
1000 LOG_WARNING("target not halted");
1001 return ERROR_TARGET_NOT_HALTED
;
1004 /* Save registers */
1005 struct reg
*reg_pc
= register_get_by_name(target
->reg_cache
, "pc", 1);
1006 if (!reg_pc
|| reg_pc
->type
->get(reg_pc
) != ERROR_OK
)
1008 uint64_t saved_pc
= buf_get_u64(reg_pc
->value
, 0, reg_pc
->size
);
1010 uint64_t saved_regs
[32];
1011 for (int i
= 0; i
< num_reg_params
; i
++) {
1012 if (reg_params
[i
].direction
== PARAM_IN
)
1015 LOG_DEBUG("save %s", reg_params
[i
].reg_name
);
1016 struct reg
*r
= register_get_by_name(target
->reg_cache
, reg_params
[i
].reg_name
, 0);
1018 LOG_ERROR("Couldn't find register named '%s'", reg_params
[i
].reg_name
);
1022 if (r
->size
!= reg_params
[i
].size
) {
1023 LOG_ERROR("Register %s is %d bits instead of %d bits.",
1024 reg_params
[i
].reg_name
, r
->size
, reg_params
[i
].size
);
1028 if (r
->number
> GDB_REGNO_XPR31
) {
1029 LOG_ERROR("Only GPRs can be use as argument registers.");
1033 if (r
->type
->get(r
) != ERROR_OK
)
1035 saved_regs
[r
->number
] = buf_get_u64(r
->value
, 0, r
->size
);
1036 if (r
->type
->set(r
, reg_params
[i
].value
) != ERROR_OK
)
1041 /* Disable Interrupts before attempting to run the algorithm. */
1042 uint64_t current_mstatus
;
1043 uint8_t mstatus_bytes
[8];
1045 LOG_DEBUG("Disabling Interrupts");
1046 struct reg
*reg_mstatus
= register_get_by_name(target
->reg_cache
,
1049 LOG_ERROR("Couldn't find mstatus!");
1053 reg_mstatus
->type
->get(reg_mstatus
);
1054 current_mstatus
= buf_get_u64(reg_mstatus
->value
, 0, reg_mstatus
->size
);
1055 uint64_t ie_mask
= MSTATUS_MIE
| MSTATUS_HIE
| MSTATUS_SIE
| MSTATUS_UIE
;
1056 buf_set_u64(mstatus_bytes
, 0, info
->xlen
[0], set_field(current_mstatus
,
1059 reg_mstatus
->type
->set(reg_mstatus
, mstatus_bytes
);
1062 LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR
, entry_point
);
1063 if (oldriscv_resume(target
, 0, entry_point
, 0, 0) != ERROR_OK
)
1066 int64_t start
= timeval_ms();
1067 while (target
->state
!= TARGET_HALTED
) {
1068 LOG_DEBUG("poll()");
1069 int64_t now
= timeval_ms();
1070 if (now
- start
> timeout_ms
) {
1071 LOG_ERROR("Algorithm timed out after %d ms.", timeout_ms
);
1072 LOG_ERROR(" now = 0x%08x", (uint32_t) now
);
1073 LOG_ERROR(" start = 0x%08x", (uint32_t) start
);
1074 oldriscv_halt(target
);
1075 old_or_new_riscv_poll(target
);
1076 return ERROR_TARGET_TIMEOUT
;
1079 int result
= old_or_new_riscv_poll(target
);
1080 if (result
!= ERROR_OK
)
1084 if (reg_pc
->type
->get(reg_pc
) != ERROR_OK
)
1086 uint64_t final_pc
= buf_get_u64(reg_pc
->value
, 0, reg_pc
->size
);
1087 if (final_pc
!= exit_point
) {
1088 LOG_ERROR("PC ended up at 0x%" PRIx64
" instead of 0x%"
1089 TARGET_PRIxADDR
, final_pc
, exit_point
);
1093 /* Restore Interrupts */
1094 LOG_DEBUG("Restoring Interrupts");
1095 buf_set_u64(mstatus_bytes
, 0, info
->xlen
[0], current_mstatus
);
1096 reg_mstatus
->type
->set(reg_mstatus
, mstatus_bytes
);
1098 /* Restore registers */
1100 buf_set_u64(buf
, 0, info
->xlen
[0], saved_pc
);
1101 if (reg_pc
->type
->set(reg_pc
, buf
) != ERROR_OK
)
1104 for (int i
= 0; i
< num_reg_params
; i
++) {
1105 LOG_DEBUG("restore %s", reg_params
[i
].reg_name
);
1106 struct reg
*r
= register_get_by_name(target
->reg_cache
, reg_params
[i
].reg_name
, 0);
1107 buf_set_u64(buf
, 0, info
->xlen
[0], saved_regs
[r
->number
]);
1108 if (r
->type
->set(r
, buf
) != ERROR_OK
)
1115 /* Should run code on the target to perform CRC of
1116 memory. Not yet implemented.
1119 static int riscv_checksum_memory(struct target
*target
,
1120 target_addr_t address
, uint32_t count
,
1123 *checksum
= 0xFFFFFFFF;
1124 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1127 /*** OpenOCD Helper Functions ***/
1129 enum riscv_poll_hart
{
1131 RPH_DISCOVERED_HALTED
,
1132 RPH_DISCOVERED_RUNNING
,
1135 static enum riscv_poll_hart
riscv_poll_hart(struct target
*target
, int hartid
)
1138 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
1141 LOG_DEBUG("polling hart %d, target->state=%d", hartid
, target
->state
);
1143 /* If OpenOCD thinks we're running but this hart is halted then it's time
1144 * to raise an event. */
1145 bool halted
= riscv_is_halted(target
);
1146 if (target
->state
!= TARGET_HALTED
&& halted
) {
1147 LOG_DEBUG(" triggered a halt");
1149 return RPH_DISCOVERED_HALTED
;
1150 } else if (target
->state
!= TARGET_RUNNING
&& !halted
) {
1151 LOG_DEBUG(" triggered running");
1152 target
->state
= TARGET_RUNNING
;
1153 return RPH_DISCOVERED_RUNNING
;
1156 return RPH_NO_CHANGE
;
1159 int set_debug_reason(struct target
*target
, int hartid
)
1161 switch (riscv_halt_reason(target
, hartid
)) {
1162 case RISCV_HALT_BREAKPOINT
:
1163 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1165 case RISCV_HALT_TRIGGER
:
1166 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1168 case RISCV_HALT_INTERRUPT
:
1169 target
->debug_reason
= DBG_REASON_DBGRQ
;
1171 case RISCV_HALT_SINGLESTEP
:
1172 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1174 case RISCV_HALT_UNKNOWN
:
1175 target
->debug_reason
= DBG_REASON_UNDEFINED
;
1177 case RISCV_HALT_ERROR
:
1183 /*** OpenOCD Interface ***/
1184 int riscv_openocd_poll(struct target
*target
)
1186 LOG_DEBUG("polling all harts");
1187 int halted_hart
= -1;
1188 if (riscv_rtos_enabled(target
)) {
1189 /* Check every hart for an event. */
1190 for (int i
= 0; i
< riscv_count_harts(target
); ++i
) {
1191 enum riscv_poll_hart out
= riscv_poll_hart(target
, i
);
1194 case RPH_DISCOVERED_RUNNING
:
1196 case RPH_DISCOVERED_HALTED
:
1203 if (halted_hart
== -1) {
1204 LOG_DEBUG(" no harts just halted, target->state=%d", target
->state
);
1207 LOG_DEBUG(" hart %d halted", halted_hart
);
1209 /* If we're here then at least one hart triggered. That means
1210 * we want to go and halt _every_ hart in the system, as that's
1211 * the invariant we hold here. Some harts might have already
1212 * halted (as we're either in single-step mode or they also
1213 * triggered a breakpoint), so don't attempt to halt those
1215 for (int i
= 0; i
< riscv_count_harts(target
); ++i
)
1216 riscv_halt_one_hart(target
, i
);
1218 } else if (target
->smp
) {
1219 bool halt_discovered
= false;
1220 bool newly_halted
[128] = {0};
1222 for (struct target_list
*list
= target
->head
; list
!= NULL
;
1223 list
= list
->next
, i
++) {
1224 struct target
*t
= list
->target
;
1225 riscv_info_t
*r
= riscv_info(t
);
1226 assert(i
< DIM(newly_halted
));
1227 enum riscv_poll_hart out
= riscv_poll_hart(t
, r
->current_hartid
);
1231 case RPH_DISCOVERED_RUNNING
:
1232 t
->state
= TARGET_RUNNING
;
1234 case RPH_DISCOVERED_HALTED
:
1235 halt_discovered
= true;
1236 newly_halted
[i
] = true;
1237 t
->state
= TARGET_HALTED
;
1238 if (set_debug_reason(t
, r
->current_hartid
) != ERROR_OK
)
1246 if (halt_discovered
) {
1247 LOG_DEBUG("Halt other targets in this SMP group.");
1249 for (struct target_list
*list
= target
->head
; list
!= NULL
;
1250 list
= list
->next
, i
++) {
1251 struct target
*t
= list
->target
;
1252 riscv_info_t
*r
= riscv_info(t
);
1253 if (t
->state
!= TARGET_HALTED
) {
1254 if (riscv_halt_one_hart(t
, r
->current_hartid
) != ERROR_OK
)
1256 t
->state
= TARGET_HALTED
;
1257 if (set_debug_reason(t
, r
->current_hartid
) != ERROR_OK
)
1259 newly_halted
[i
] = true;
1263 /* Now that we have all our ducks in a row, tell the higher layers
1264 * what just happened. */
1266 for (struct target_list
*list
= target
->head
; list
!= NULL
;
1267 list
= list
->next
, i
++) {
1268 struct target
*t
= list
->target
;
1269 if (newly_halted
[i
])
1270 target_call_event_callbacks(t
, TARGET_EVENT_HALTED
);
1276 enum riscv_poll_hart out
= riscv_poll_hart(target
,
1277 riscv_current_hartid(target
));
1278 if (out
== RPH_NO_CHANGE
|| out
== RPH_DISCOVERED_RUNNING
)
1280 else if (out
== RPH_ERROR
)
1283 halted_hart
= riscv_current_hartid(target
);
1284 LOG_DEBUG(" hart %d halted", halted_hart
);
1287 target
->state
= TARGET_HALTED
;
1288 if (set_debug_reason(target
, halted_hart
) != ERROR_OK
)
1291 if (riscv_rtos_enabled(target
)) {
1292 target
->rtos
->current_threadid
= halted_hart
+ 1;
1293 target
->rtos
->current_thread
= halted_hart
+ 1;
1294 riscv_set_rtos_hartid(target
, halted_hart
);
1297 target
->state
= TARGET_HALTED
;
1299 if (target
->debug_reason
== DBG_REASON_BREAKPOINT
) {
1301 if (riscv_semihosting(target
, &retval
) != 0)
1305 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1309 int riscv_openocd_halt(struct target
*target
)
1314 LOG_DEBUG("[%d] halting all harts", target
->coreid
);
1317 LOG_DEBUG("Halt other targets in this SMP group.");
1318 struct target_list
*targets
= target
->head
;
1321 struct target
*t
= targets
->target
;
1322 targets
= targets
->next
;
1323 if (t
->state
!= TARGET_HALTED
) {
1324 if (riscv_halt_all_harts(t
) != ERROR_OK
)
1325 result
= ERROR_FAIL
;
1329 result
= riscv_halt_all_harts(target
);
1332 if (riscv_rtos_enabled(target
)) {
1333 if (r
->rtos_hartid
!= -1) {
1334 LOG_DEBUG("halt requested on RTOS hartid %d", r
->rtos_hartid
);
1335 target
->rtos
->current_threadid
= r
->rtos_hartid
+ 1;
1336 target
->rtos
->current_thread
= r
->rtos_hartid
+ 1;
1338 LOG_DEBUG("halt requested, but no known RTOS hartid");
1341 target
->state
= TARGET_HALTED
;
1342 target
->debug_reason
= DBG_REASON_DBGRQ
;
1343 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1347 int riscv_openocd_resume(
1348 struct target
*target
,
1350 target_addr_t address
,
1351 int handle_breakpoints
,
1352 int debug_execution
)
1354 LOG_DEBUG("debug_reason=%d", target
->debug_reason
);
1357 riscv_set_register(target
, GDB_REGNO_PC
, address
);
1359 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
1360 /* To be able to run off a trigger, disable all the triggers, step, and
1361 * then resume as usual. */
1362 struct watchpoint
*watchpoint
= target
->watchpoints
;
1363 bool trigger_temporarily_cleared
[RISCV_MAX_HWBPS
] = {0};
1366 int result
= ERROR_OK
;
1367 while (watchpoint
&& result
== ERROR_OK
) {
1368 LOG_DEBUG("watchpoint %d: set=%d", i
, watchpoint
->set
);
1369 trigger_temporarily_cleared
[i
] = watchpoint
->set
;
1370 if (watchpoint
->set
)
1371 result
= riscv_remove_watchpoint(target
, watchpoint
);
1372 watchpoint
= watchpoint
->next
;
1376 if (result
== ERROR_OK
)
1377 result
= riscv_step_rtos_hart(target
);
1379 watchpoint
= target
->watchpoints
;
1381 while (watchpoint
) {
1382 LOG_DEBUG("watchpoint %d: cleared=%d", i
, trigger_temporarily_cleared
[i
]);
1383 if (trigger_temporarily_cleared
[i
]) {
1384 if (result
== ERROR_OK
)
1385 result
= riscv_add_watchpoint(target
, watchpoint
);
1387 riscv_add_watchpoint(target
, watchpoint
);
1389 watchpoint
= watchpoint
->next
;
1393 if (result
!= ERROR_OK
)
1397 int out
= riscv_resume_all_harts(target
);
1398 if (out
!= ERROR_OK
) {
1399 LOG_ERROR("unable to resume all harts");
1403 register_cache_invalidate(target
->reg_cache
);
1404 target
->state
= TARGET_RUNNING
;
1405 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1409 int riscv_openocd_step(
1410 struct target
*target
,
1412 target_addr_t address
,
1413 int handle_breakpoints
1415 LOG_DEBUG("stepping rtos hart");
1418 riscv_set_register(target
, GDB_REGNO_PC
, address
);
1420 int out
= riscv_step_rtos_hart(target
);
1421 if (out
!= ERROR_OK
) {
1422 LOG_ERROR("unable to step rtos hart");
1426 register_cache_invalidate(target
->reg_cache
);
1427 target
->state
= TARGET_RUNNING
;
1428 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1429 target
->state
= TARGET_HALTED
;
1430 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1431 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1435 /* Command Handlers */
1436 COMMAND_HANDLER(riscv_set_command_timeout_sec
)
1438 if (CMD_ARGC
!= 1) {
1439 LOG_ERROR("Command takes exactly 1 parameter");
1440 return ERROR_COMMAND_SYNTAX_ERROR
;
1442 int timeout
= atoi(CMD_ARGV
[0]);
1444 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV
[0]);
1448 riscv_command_timeout_sec
= timeout
;
1453 COMMAND_HANDLER(riscv_set_reset_timeout_sec
)
1455 if (CMD_ARGC
!= 1) {
1456 LOG_ERROR("Command takes exactly 1 parameter");
1457 return ERROR_COMMAND_SYNTAX_ERROR
;
1459 int timeout
= atoi(CMD_ARGV
[0]);
1461 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV
[0]);
1465 riscv_reset_timeout_sec
= timeout
;
1469 COMMAND_HANDLER(riscv_test_compliance
) {
1471 struct target
*target
= get_current_target(CMD_CTX
);
1476 LOG_ERROR("Command does not take any parameters.");
1477 return ERROR_COMMAND_SYNTAX_ERROR
;
1480 if (r
->test_compliance
) {
1481 return r
->test_compliance(target
);
1483 LOG_ERROR("This target does not support this command (may implement an older version of the spec).");
1488 COMMAND_HANDLER(riscv_set_prefer_sba
)
1490 if (CMD_ARGC
!= 1) {
1491 LOG_ERROR("Command takes exactly 1 parameter");
1492 return ERROR_COMMAND_SYNTAX_ERROR
;
1494 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_prefer_sba
);
1498 void parse_error(const char *string
, char c
, unsigned position
)
1500 char buf
[position
+2];
1501 for (unsigned i
= 0; i
< position
; i
++)
1503 buf
[position
] = '^';
1504 buf
[position
+ 1] = 0;
1506 LOG_ERROR("Parse error at character %c in:", c
);
1507 LOG_ERROR("%s", string
);
1508 LOG_ERROR("%s", buf
);
1511 int parse_ranges(range_t
**ranges
, const char **argv
)
1513 for (unsigned pass
= 0; pass
< 2; pass
++) {
1516 bool parse_low
= true;
1518 for (unsigned i
= 0; i
== 0 || argv
[0][i
-1]; i
++) {
1519 char c
= argv
[0][i
];
1521 /* Ignore whitespace. */
1529 } else if (c
== '-') {
1531 } else if (c
== ',' || c
== 0) {
1533 (*ranges
)[range
].low
= low
;
1534 (*ranges
)[range
].high
= low
;
1539 parse_error(argv
[0], c
, i
);
1540 return ERROR_COMMAND_SYNTAX_ERROR
;
1547 } else if (c
== ',' || c
== 0) {
1550 (*ranges
)[range
].low
= low
;
1551 (*ranges
)[range
].high
= high
;
1557 parse_error(argv
[0], c
, i
);
1558 return ERROR_COMMAND_SYNTAX_ERROR
;
1566 *ranges
= calloc(range
+ 2, sizeof(range_t
));
1568 (*ranges
)[range
].low
= 1;
1569 (*ranges
)[range
].high
= 0;
1576 COMMAND_HANDLER(riscv_set_expose_csrs
)
1578 if (CMD_ARGC
!= 1) {
1579 LOG_ERROR("Command takes exactly 1 parameter");
1580 return ERROR_COMMAND_SYNTAX_ERROR
;
1583 return parse_ranges(&expose_csr
, CMD_ARGV
);
1586 COMMAND_HANDLER(riscv_set_expose_custom
)
1588 if (CMD_ARGC
!= 1) {
1589 LOG_ERROR("Command takes exactly 1 parameter");
1590 return ERROR_COMMAND_SYNTAX_ERROR
;
1593 return parse_ranges(&expose_custom
, CMD_ARGV
);
1596 COMMAND_HANDLER(riscv_authdata_read
)
1598 if (CMD_ARGC
!= 0) {
1599 LOG_ERROR("Command takes no parameters");
1600 return ERROR_COMMAND_SYNTAX_ERROR
;
1603 struct target
*target
= get_current_target(CMD_CTX
);
1605 LOG_ERROR("target is NULL!");
1611 LOG_ERROR("riscv_info is NULL!");
1615 if (r
->authdata_read
) {
1617 if (r
->authdata_read(target
, &value
) != ERROR_OK
)
1619 command_print(CMD_CTX
, "0x%" PRIx32
, value
);
1622 LOG_ERROR("authdata_read is not implemented for this target.");
1627 COMMAND_HANDLER(riscv_authdata_write
)
1629 if (CMD_ARGC
!= 1) {
1630 LOG_ERROR("Command takes exactly 1 argument");
1631 return ERROR_COMMAND_SYNTAX_ERROR
;
1634 struct target
*target
= get_current_target(CMD_CTX
);
1638 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], value
);
1640 if (r
->authdata_write
) {
1641 return r
->authdata_write(target
, value
);
1643 LOG_ERROR("authdata_write is not implemented for this target.");
1648 COMMAND_HANDLER(riscv_dmi_read
)
1650 if (CMD_ARGC
!= 1) {
1651 LOG_ERROR("Command takes 1 parameter");
1652 return ERROR_COMMAND_SYNTAX_ERROR
;
1655 struct target
*target
= get_current_target(CMD_CTX
);
1657 LOG_ERROR("target is NULL!");
1663 LOG_ERROR("riscv_info is NULL!");
1668 uint32_t address
, value
;
1669 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
1670 if (r
->dmi_read(target
, &value
, address
) != ERROR_OK
)
1672 command_print(CMD_CTX
, "0x%" PRIx32
, value
);
1675 LOG_ERROR("dmi_read is not implemented for this target.");
1681 COMMAND_HANDLER(riscv_dmi_write
)
1683 if (CMD_ARGC
!= 2) {
1684 LOG_ERROR("Command takes exactly 2 arguments");
1685 return ERROR_COMMAND_SYNTAX_ERROR
;
1688 struct target
*target
= get_current_target(CMD_CTX
);
1691 uint32_t address
, value
;
1692 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
1693 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
1696 return r
->dmi_write(target
, address
, value
);
1698 LOG_ERROR("dmi_write is not implemented for this target.");
1703 COMMAND_HANDLER(riscv_test_sba_config_reg
)
1705 if (CMD_ARGC
!= 4) {
1706 LOG_ERROR("Command takes exactly 4 arguments");
1707 return ERROR_COMMAND_SYNTAX_ERROR
;
1710 struct target
*target
= get_current_target(CMD_CTX
);
1713 target_addr_t legal_address
;
1715 target_addr_t illegal_address
;
1716 bool run_sbbusyerror_test
;
1718 COMMAND_PARSE_NUMBER(target_addr
, CMD_ARGV
[0], legal_address
);
1719 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], num_words
);
1720 COMMAND_PARSE_NUMBER(target_addr
, CMD_ARGV
[2], illegal_address
);
1721 COMMAND_PARSE_ON_OFF(CMD_ARGV
[3], run_sbbusyerror_test
);
1723 if (r
->test_sba_config_reg
) {
1724 return r
->test_sba_config_reg(target
, legal_address
, num_words
,
1725 illegal_address
, run_sbbusyerror_test
);
1727 LOG_ERROR("test_sba_config_reg is not implemented for this target.");
1732 COMMAND_HANDLER(riscv_reset_delays
)
1737 LOG_ERROR("Command takes at most one argument");
1738 return ERROR_COMMAND_SYNTAX_ERROR
;
1742 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], wait
);
1744 struct target
*target
= get_current_target(CMD_CTX
);
1746 r
->reset_delays_wait
= wait
;
1750 COMMAND_HANDLER(riscv_set_ir
)
1752 if (CMD_ARGC
!= 2) {
1753 LOG_ERROR("Command takes exactly 2 arguments");
1754 return ERROR_COMMAND_SYNTAX_ERROR
;
1758 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
1760 if (!strcmp(CMD_ARGV
[0], "idcode")) {
1761 buf_set_u32(ir_idcode
, 0, 32, value
);
1763 } else if (!strcmp(CMD_ARGV
[0], "dtmcs")) {
1764 buf_set_u32(ir_dtmcontrol
, 0, 32, value
);
1766 } else if (!strcmp(CMD_ARGV
[0], "dmi")) {
1767 buf_set_u32(ir_dbus
, 0, 32, value
);
1774 static const struct command_registration riscv_exec_command_handlers
[] = {
1776 .name
= "test_compliance",
1777 .handler
= riscv_test_compliance
,
1778 .mode
= COMMAND_EXEC
,
1779 .usage
= "riscv test_compliance",
1780 .help
= "Runs a basic compliance test suite against the RISC-V Debug Spec."
1783 .name
= "set_command_timeout_sec",
1784 .handler
= riscv_set_command_timeout_sec
,
1785 .mode
= COMMAND_ANY
,
1786 .usage
= "riscv set_command_timeout_sec [sec]",
1787 .help
= "Set the wall-clock timeout (in seconds) for individual commands"
1790 .name
= "set_reset_timeout_sec",
1791 .handler
= riscv_set_reset_timeout_sec
,
1792 .mode
= COMMAND_ANY
,
1793 .usage
= "riscv set_reset_timeout_sec [sec]",
1794 .help
= "Set the wall-clock timeout (in seconds) after reset is deasserted"
1797 .name
= "set_prefer_sba",
1798 .handler
= riscv_set_prefer_sba
,
1799 .mode
= COMMAND_ANY
,
1800 .usage
= "riscv set_prefer_sba on|off",
1801 .help
= "When on, prefer to use System Bus Access to access memory. "
1802 "When off, prefer to use the Program Buffer to access memory."
1805 .name
= "expose_csrs",
1806 .handler
= riscv_set_expose_csrs
,
1807 .mode
= COMMAND_ANY
,
1808 .usage
= "riscv expose_csrs n0[-m0][,n1[-m1]]...",
1809 .help
= "Configure a list of inclusive ranges for CSRs to expose in "
1810 "addition to the standard ones. This must be executed before "
1814 .name
= "expose_custom",
1815 .handler
= riscv_set_expose_custom
,
1816 .mode
= COMMAND_ANY
,
1817 .usage
= "riscv expose_custom n0[-m0][,n1[-m1]]...",
1818 .help
= "Configure a list of inclusive ranges for custom registers to "
1819 "expose. custom0 is accessed as abstract register number 0xc000, "
1820 "etc. This must be executed before `init`."
1823 .name
= "authdata_read",
1824 .handler
= riscv_authdata_read
,
1825 .mode
= COMMAND_ANY
,
1826 .usage
= "riscv authdata_read",
1827 .help
= "Return the 32-bit value read from authdata."
1830 .name
= "authdata_write",
1831 .handler
= riscv_authdata_write
,
1832 .mode
= COMMAND_ANY
,
1833 .usage
= "riscv authdata_write value",
1834 .help
= "Write the 32-bit value to authdata."
1838 .handler
= riscv_dmi_read
,
1839 .mode
= COMMAND_ANY
,
1840 .usage
= "riscv dmi_read address",
1841 .help
= "Perform a 32-bit DMI read at address, returning the value."
1844 .name
= "dmi_write",
1845 .handler
= riscv_dmi_write
,
1846 .mode
= COMMAND_ANY
,
1847 .usage
= "riscv dmi_write address value",
1848 .help
= "Perform a 32-bit DMI write of value at address."
1851 .name
= "test_sba_config_reg",
1852 .handler
= riscv_test_sba_config_reg
,
1853 .mode
= COMMAND_ANY
,
1854 .usage
= "riscv test_sba_config_reg legal_address num_words"
1855 "illegal_address run_sbbusyerror_test[on/off]",
1856 .help
= "Perform a series of tests on the SBCS register."
1857 "Inputs are a legal, 128-byte aligned address and a number of words to"
1858 "read/write starting at that address (i.e., address range [legal address,"
1859 "legal_address+word_size*num_words) must be legally readable/writable)"
1860 ", an illegal, 128-byte aligned address for error flag/handling cases,"
1861 "and whether sbbusyerror test should be run."
1864 .name
= "reset_delays",
1865 .handler
= riscv_reset_delays
,
1866 .mode
= COMMAND_ANY
,
1867 .usage
= "reset_delays [wait]",
1868 .help
= "OpenOCD learns how many Run-Test/Idle cycles are required "
1869 "between scans to avoid encountering the target being busy. This "
1870 "command resets those learned values after `wait` scans. It's only "
1871 "useful for testing OpenOCD itself."
1875 .handler
= riscv_set_ir
,
1876 .mode
= COMMAND_ANY
,
1877 .usage
= "riscv set_ir_idcode [idcode|dtmcs|dmi] value",
1878 .help
= "Set IR value for specified JTAG register."
1880 COMMAND_REGISTRATION_DONE
1883 extern __COMMAND_HANDLER(handle_common_semihosting_command
);
1884 extern __COMMAND_HANDLER(handle_common_semihosting_fileio_command
);
1885 extern __COMMAND_HANDLER(handle_common_semihosting_resumable_exit_command
);
1886 extern __COMMAND_HANDLER(handle_common_semihosting_cmdline
);
1889 * To be noted that RISC-V targets use the same semihosting commands as
1892 * The main reason is compatibility with existing tools. For example the
1893 * Eclipse OpenOCD/SEGGER J-Link/QEMU plug-ins have several widgets to
1894 * configure semihosting, which generate commands like `arm semihosting
1896 * A secondary reason is the fact that the protocol used is exactly the
1897 * one specified by ARM. If RISC-V will ever define its own semihosting
1898 * protocol, then a command like `riscv semihosting enable` will make
1899 * sense, but for now all semihosting commands are prefixed with `arm`.
1901 static const struct command_registration arm_exec_command_handlers
[] = {
1904 .handler
= handle_common_semihosting_command
,
1905 .mode
= COMMAND_EXEC
,
1906 .usage
= "['enable'|'disable']",
1907 .help
= "activate support for semihosting operations",
1910 "semihosting_cmdline",
1911 .handler
= handle_common_semihosting_cmdline
,
1912 .mode
= COMMAND_EXEC
,
1913 .usage
= "arguments",
1914 .help
= "command line arguments to be passed to program",
1917 "semihosting_fileio",
1918 .handler
= handle_common_semihosting_fileio_command
,
1919 .mode
= COMMAND_EXEC
,
1920 .usage
= "['enable'|'disable']",
1921 .help
= "activate support for semihosting fileio operations",
1924 "semihosting_resexit",
1925 .handler
= handle_common_semihosting_resumable_exit_command
,
1926 .mode
= COMMAND_EXEC
,
1927 .usage
= "['enable'|'disable']",
1928 .help
= "activate support for semihosting resumable exit",
1930 COMMAND_REGISTRATION_DONE
1933 const struct command_registration riscv_command_handlers
[] = {
1936 .mode
= COMMAND_ANY
,
1937 .help
= "RISC-V Command Group",
1939 .chain
= riscv_exec_command_handlers
1943 .mode
= COMMAND_ANY
,
1944 .help
= "ARM Command Group",
1946 .chain
= arm_exec_command_handlers
1948 COMMAND_REGISTRATION_DONE
1951 unsigned riscv_address_bits(struct target
*target
)
1953 return riscv_xlen(target
);
1956 struct target_type riscv_target
= {
1959 .init_target
= riscv_init_target
,
1960 .deinit_target
= riscv_deinit_target
,
1961 .examine
= riscv_examine
,
1963 /* poll current target status */
1964 .poll
= old_or_new_riscv_poll
,
1966 .halt
= old_or_new_riscv_halt
,
1967 .resume
= old_or_new_riscv_resume
,
1968 .step
= old_or_new_riscv_step
,
1970 .assert_reset
= riscv_assert_reset
,
1971 .deassert_reset
= riscv_deassert_reset
,
1973 .read_memory
= riscv_read_memory
,
1974 .write_memory
= riscv_write_memory
,
1976 .checksum_memory
= riscv_checksum_memory
,
1978 .get_gdb_reg_list
= riscv_get_gdb_reg_list
,
1980 .add_breakpoint
= riscv_add_breakpoint
,
1981 .remove_breakpoint
= riscv_remove_breakpoint
,
1983 .add_watchpoint
= riscv_add_watchpoint
,
1984 .remove_watchpoint
= riscv_remove_watchpoint
,
1985 .hit_watchpoint
= riscv_hit_watchpoint
,
1987 .arch_state
= riscv_arch_state
,
1989 .run_algorithm
= riscv_run_algorithm
,
1991 .commands
= riscv_command_handlers
,
1993 .address_bits
= riscv_address_bits
1996 /*** RISC-V Interface ***/
1998 void riscv_info_init(struct target
*target
, riscv_info_t
*r
)
2000 memset(r
, 0, sizeof(*r
));
2002 r
->registers_initialized
= false;
2003 r
->current_hartid
= target
->coreid
;
2005 memset(r
->trigger_unique_id
, 0xff, sizeof(r
->trigger_unique_id
));
2007 for (size_t h
= 0; h
< RISCV_MAX_HARTS
; ++h
) {
2010 for (size_t e
= 0; e
< RISCV_MAX_REGISTERS
; ++e
)
2011 r
->valid_saved_registers
[h
][e
] = false;
2015 int riscv_halt_all_harts(struct target
*target
)
2017 for (int i
= 0; i
< riscv_count_harts(target
); ++i
) {
2018 if (!riscv_hart_enabled(target
, i
))
2021 riscv_halt_one_hart(target
, i
);
2024 riscv_invalidate_register_cache(target
);
2029 int riscv_halt_one_hart(struct target
*target
, int hartid
)
2032 LOG_DEBUG("halting hart %d", hartid
);
2033 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
2035 if (riscv_is_halted(target
)) {
2036 LOG_DEBUG(" hart %d requested halt, but was already halted", hartid
);
2040 int result
= r
->halt_current_hart(target
);
2041 register_cache_invalidate(target
->reg_cache
);
2045 int riscv_resume_all_harts(struct target
*target
)
2047 for (int i
= 0; i
< riscv_count_harts(target
); ++i
) {
2048 if (!riscv_hart_enabled(target
, i
))
2051 riscv_resume_one_hart(target
, i
);
2054 riscv_invalidate_register_cache(target
);
2058 int riscv_resume_one_hart(struct target
*target
, int hartid
)
2061 LOG_DEBUG("resuming hart %d", hartid
);
2062 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
2064 if (!riscv_is_halted(target
)) {
2065 LOG_DEBUG(" hart %d requested resume, but was already resumed", hartid
);
2069 r
->on_resume(target
);
2070 return r
->resume_current_hart(target
);
2073 int riscv_step_rtos_hart(struct target
*target
)
2076 int hartid
= r
->current_hartid
;
2077 if (riscv_rtos_enabled(target
)) {
2078 hartid
= r
->rtos_hartid
;
2080 LOG_DEBUG("GDB has asked me to step \"any\" thread, so I'm stepping hart 0.");
2084 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
2086 LOG_DEBUG("stepping hart %d", hartid
);
2088 if (!riscv_is_halted(target
)) {
2089 LOG_ERROR("Hart isn't halted before single step!");
2092 riscv_invalidate_register_cache(target
);
2094 if (r
->step_current_hart(target
) != ERROR_OK
)
2096 riscv_invalidate_register_cache(target
);
2098 if (!riscv_is_halted(target
)) {
2099 LOG_ERROR("Hart was not halted after single step!");
2105 bool riscv_supports_extension(struct target
*target
, int hartid
, char letter
)
2109 if (letter
>= 'a' && letter
<= 'z')
2111 else if (letter
>= 'A' && letter
<= 'Z')
2115 return r
->misa
[hartid
] & (1 << num
);
2118 int riscv_xlen(const struct target
*target
)
2120 return riscv_xlen_of_hart(target
, riscv_current_hartid(target
));
2123 int riscv_xlen_of_hart(const struct target
*target
, int hartid
)
2126 assert(r
->xlen
[hartid
] != -1);
2127 return r
->xlen
[hartid
];
2130 extern struct rtos_type riscv_rtos
;
2131 bool riscv_rtos_enabled(const struct target
*target
)
2136 int riscv_set_current_hartid(struct target
*target
, int hartid
)
2139 if (!r
->select_current_hart
)
2142 int previous_hartid
= riscv_current_hartid(target
);
2143 r
->current_hartid
= hartid
;
2144 assert(riscv_hart_enabled(target
, hartid
));
2145 LOG_DEBUG("setting hartid to %d, was %d", hartid
, previous_hartid
);
2146 if (r
->select_current_hart(target
) != ERROR_OK
)
2149 /* This might get called during init, in which case we shouldn't be
2150 * setting up the register cache. */
2151 if (target_was_examined(target
) && riscv_rtos_enabled(target
))
2152 riscv_invalidate_register_cache(target
);
2157 void riscv_invalidate_register_cache(struct target
*target
)
2161 LOG_DEBUG("[%d]", target
->coreid
);
2162 register_cache_invalidate(target
->reg_cache
);
2163 for (size_t i
= 0; i
< target
->reg_cache
->num_regs
; ++i
) {
2164 struct reg
*reg
= &target
->reg_cache
->reg_list
[i
];
2168 r
->registers_initialized
= true;
2171 int riscv_current_hartid(const struct target
*target
)
2174 return r
->current_hartid
;
2177 void riscv_set_all_rtos_harts(struct target
*target
)
2180 r
->rtos_hartid
= -1;
2183 void riscv_set_rtos_hartid(struct target
*target
, int hartid
)
2185 LOG_DEBUG("setting RTOS hartid %d", hartid
);
2187 r
->rtos_hartid
= hartid
;
2190 int riscv_count_harts(struct target
*target
)
2197 return r
->hart_count
;
2200 bool riscv_has_register(struct target
*target
, int hartid
, int regid
)
2206 * This function is called when the debug user wants to change the value of a
2207 * register. The new value may be cached, and may not be written until the hart
2209 int riscv_set_register(struct target
*target
, enum gdb_regno r
, riscv_reg_t v
)
2211 return riscv_set_register_on_hart(target
, riscv_current_hartid(target
), r
, v
);
2214 int riscv_set_register_on_hart(struct target
*target
, int hartid
,
2215 enum gdb_regno regid
, uint64_t value
)
2218 LOG_DEBUG("{%d} %s <- %" PRIx64
, hartid
, gdb_regno_name(regid
), value
);
2219 assert(r
->set_register
);
2220 return r
->set_register(target
, hartid
, regid
, value
);
2223 int riscv_get_register(struct target
*target
, riscv_reg_t
*value
,
2226 return riscv_get_register_on_hart(target
, value
,
2227 riscv_current_hartid(target
), r
);
2230 int riscv_get_register_on_hart(struct target
*target
, riscv_reg_t
*value
,
2231 int hartid
, enum gdb_regno regid
)
2235 struct reg
*reg
= &target
->reg_cache
->reg_list
[regid
];
2237 if (reg
&& reg
->valid
&& hartid
== riscv_current_hartid(target
)) {
2238 *value
= buf_get_u64(reg
->value
, 0, reg
->size
);
2242 int result
= r
->get_register(target
, value
, hartid
, regid
);
2244 LOG_DEBUG("{%d} %s: %" PRIx64
, hartid
, gdb_regno_name(regid
), *value
);
2248 bool riscv_is_halted(struct target
*target
)
2251 assert(r
->is_halted
);
2252 return r
->is_halted(target
);
2255 enum riscv_halt_reason
riscv_halt_reason(struct target
*target
, int hartid
)
2258 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
2259 return RISCV_HALT_ERROR
;
2260 if (!riscv_is_halted(target
)) {
2261 LOG_ERROR("Hart is not halted!");
2262 return RISCV_HALT_UNKNOWN
;
2264 return r
->halt_reason(target
);
2267 size_t riscv_debug_buffer_size(struct target
*target
)
2270 return r
->debug_buffer_size
[riscv_current_hartid(target
)];
2273 int riscv_write_debug_buffer(struct target
*target
, int index
, riscv_insn_t insn
)
2276 r
->write_debug_buffer(target
, index
, insn
);
2280 riscv_insn_t
riscv_read_debug_buffer(struct target
*target
, int index
)
2283 return r
->read_debug_buffer(target
, index
);
2286 int riscv_execute_debug_buffer(struct target
*target
)
2289 return r
->execute_debug_buffer(target
);
2292 void riscv_fill_dmi_write_u64(struct target
*target
, char *buf
, int a
, uint64_t d
)
2295 r
->fill_dmi_write_u64(target
, buf
, a
, d
);
2298 void riscv_fill_dmi_read_u64(struct target
*target
, char *buf
, int a
)
2301 r
->fill_dmi_read_u64(target
, buf
, a
);
2304 void riscv_fill_dmi_nop_u64(struct target
*target
, char *buf
)
2307 r
->fill_dmi_nop_u64(target
, buf
);
2310 int riscv_dmi_write_u64_bits(struct target
*target
)
2313 return r
->dmi_write_u64_bits(target
);
2316 bool riscv_hart_enabled(struct target
*target
, int hartid
)
2318 /* FIXME: Add a hart mask to the RTOS. */
2319 if (riscv_rtos_enabled(target
))
2320 return hartid
< riscv_count_harts(target
);
2322 return hartid
== target
->coreid
;
2326 * Count triggers, and initialize trigger_count for each hart.
2327 * trigger_count is initialized even if this function fails to discover
2329 * Disable any hardware triggers that have dmode set. We can't have set them
2330 * ourselves. Maybe they're left over from some killed debug session.
2332 int riscv_enumerate_triggers(struct target
*target
)
2336 if (r
->triggers_enumerated
)
2339 r
->triggers_enumerated
= true; /* At the very least we tried. */
2341 for (int hartid
= 0; hartid
< riscv_count_harts(target
); ++hartid
) {
2342 if (!riscv_hart_enabled(target
, hartid
))
2345 riscv_reg_t tselect
;
2346 int result
= riscv_get_register_on_hart(target
, &tselect
, hartid
,
2348 if (result
!= ERROR_OK
)
2351 for (unsigned t
= 0; t
< RISCV_MAX_TRIGGERS
; ++t
) {
2352 r
->trigger_count
[hartid
] = t
;
2354 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, t
);
2355 uint64_t tselect_rb
;
2356 result
= riscv_get_register_on_hart(target
, &tselect_rb
, hartid
,
2358 if (result
!= ERROR_OK
)
2360 /* Mask off the top bit, which is used as tdrmode in old
2361 * implementations. */
2362 tselect_rb
&= ~(1ULL << (riscv_xlen(target
)-1));
2363 if (tselect_rb
!= t
)
2366 result
= riscv_get_register_on_hart(target
, &tdata1
, hartid
,
2368 if (result
!= ERROR_OK
)
2371 int type
= get_field(tdata1
, MCONTROL_TYPE(riscv_xlen(target
)));
2374 /* On these older cores we don't support software using
2376 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
2379 if (tdata1
& MCONTROL_DMODE(riscv_xlen(target
)))
2380 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
2385 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, tselect
);
2387 LOG_INFO("[%d] Found %d triggers", hartid
, r
->trigger_count
[hartid
]);
2393 const char *gdb_regno_name(enum gdb_regno regno
)
2395 static char buf
[32];
2398 case GDB_REGNO_ZERO
:
2406 case GDB_REGNO_FPR0
:
2408 case GDB_REGNO_FPR31
:
2410 case GDB_REGNO_CSR0
:
2412 case GDB_REGNO_TSELECT
:
2414 case GDB_REGNO_TDATA1
:
2416 case GDB_REGNO_TDATA2
:
2418 case GDB_REGNO_MISA
:
2422 case GDB_REGNO_DCSR
:
2424 case GDB_REGNO_DSCRATCH
:
2426 case GDB_REGNO_MSTATUS
:
2428 case GDB_REGNO_PRIV
:
2431 if (regno
<= GDB_REGNO_XPR31
)
2432 sprintf(buf
, "x%d", regno
- GDB_REGNO_ZERO
);
2433 else if (regno
>= GDB_REGNO_CSR0
&& regno
<= GDB_REGNO_CSR4095
)
2434 sprintf(buf
, "csr%d", regno
- GDB_REGNO_CSR0
);
2435 else if (regno
>= GDB_REGNO_FPR0
&& regno
<= GDB_REGNO_FPR31
)
2436 sprintf(buf
, "f%d", regno
- GDB_REGNO_FPR0
);
2438 sprintf(buf
, "gdb_regno_%d", regno
);
2443 static int register_get(struct reg
*reg
)
2445 riscv_reg_info_t
*reg_info
= reg
->arch_info
;
2446 struct target
*target
= reg_info
->target
;
2448 int result
= riscv_get_register(target
, &value
, reg
->number
);
2449 if (result
!= ERROR_OK
)
2451 buf_set_u64(reg
->value
, 0, reg
->size
, value
);
2452 /* CSRs (and possibly other extension) registers may change value at any
2454 if (reg
->number
<= GDB_REGNO_XPR31
||
2455 (reg
->number
>= GDB_REGNO_FPR0
&& reg
->number
<= GDB_REGNO_FPR31
) ||
2456 reg
->number
== GDB_REGNO_PC
)
2458 LOG_DEBUG("[%d]{%d} read 0x%" PRIx64
" from %s (valid=%d)",
2459 target
->coreid
, riscv_current_hartid(target
), value
, reg
->name
,
2464 static int register_set(struct reg
*reg
, uint8_t *buf
)
2466 riscv_reg_info_t
*reg_info
= reg
->arch_info
;
2467 struct target
*target
= reg_info
->target
;
2469 uint64_t value
= buf_get_u64(buf
, 0, reg
->size
);
2471 LOG_DEBUG("[%d]{%d} write 0x%" PRIx64
" to %s (valid=%d)",
2472 target
->coreid
, riscv_current_hartid(target
), value
, reg
->name
,
2474 struct reg
*r
= &target
->reg_cache
->reg_list
[reg
->number
];
2475 /* CSRs (and possibly other extension) registers may change value at any
2477 if (reg
->number
<= GDB_REGNO_XPR31
||
2478 (reg
->number
>= GDB_REGNO_FPR0
&& reg
->number
<= GDB_REGNO_FPR31
) ||
2479 reg
->number
== GDB_REGNO_PC
)
2481 memcpy(r
->value
, buf
, (r
->size
+ 7) / 8);
2483 riscv_set_register(target
, reg
->number
, value
);
2487 static struct reg_arch_type riscv_reg_arch_type
= {
2488 .get
= register_get
,
2497 static int cmp_csr_info(const void *p1
, const void *p2
)
2499 return (int) (((struct csr_info
*)p1
)->number
) - (int) (((struct csr_info
*)p2
)->number
);
2502 int riscv_init_registers(struct target
*target
)
2506 if (target
->reg_cache
) {
2507 if (target
->reg_cache
->reg_list
)
2508 free(target
->reg_cache
->reg_list
);
2509 free(target
->reg_cache
);
2512 target
->reg_cache
= calloc(1, sizeof(*target
->reg_cache
));
2513 target
->reg_cache
->name
= "RISC-V Registers";
2514 target
->reg_cache
->num_regs
= GDB_REGNO_COUNT
;
2516 if (expose_custom
) {
2517 for (unsigned i
= 0; expose_custom
[i
].low
<= expose_custom
[i
].high
; i
++) {
2518 for (unsigned number
= expose_custom
[i
].low
;
2519 number
<= expose_custom
[i
].high
;
2521 target
->reg_cache
->num_regs
++;
2525 LOG_DEBUG("create register cache for %d registers",
2526 target
->reg_cache
->num_regs
);
2528 target
->reg_cache
->reg_list
=
2529 calloc(target
->reg_cache
->num_regs
, sizeof(struct reg
));
2531 const unsigned int max_reg_name_len
= 12;
2532 if (info
->reg_names
)
2533 free(info
->reg_names
);
2535 calloc(target
->reg_cache
->num_regs
, max_reg_name_len
);
2536 char *reg_name
= info
->reg_names
;
2538 static struct reg_feature feature_cpu
= {
2539 .name
= "org.gnu.gdb.riscv.cpu"
2541 static struct reg_feature feature_fpu
= {
2542 .name
= "org.gnu.gdb.riscv.fpu"
2544 static struct reg_feature feature_csr
= {
2545 .name
= "org.gnu.gdb.riscv.csr"
2547 static struct reg_feature feature_virtual
= {
2548 .name
= "org.gnu.gdb.riscv.virtual"
2550 static struct reg_feature feature_custom
= {
2551 .name
= "org.gnu.gdb.riscv.custom"
2554 static struct reg_data_type type_ieee_single
= {
2555 .type
= REG_TYPE_IEEE_SINGLE
,
2558 static struct reg_data_type type_ieee_double
= {
2559 .type
= REG_TYPE_IEEE_DOUBLE
,
2562 struct csr_info csr_info
[] = {
2563 #define DECLARE_CSR(name, number) { number, #name },
2564 #include "encoding.h"
2567 /* encoding.h does not contain the registers in sorted order. */
2568 qsort(csr_info
, DIM(csr_info
), sizeof(*csr_info
), cmp_csr_info
);
2569 unsigned csr_info_index
= 0;
2571 unsigned custom_range_index
= 0;
2572 int custom_within_range
= 0;
2574 riscv_reg_info_t
*shared_reg_info
= calloc(1, sizeof(riscv_reg_info_t
));
2575 shared_reg_info
->target
= target
;
2577 /* When gdb requests register N, gdb_get_register_packet() assumes that this
2578 * is register at index N in reg_list. So if there are certain registers
2579 * that don't exist, we need to leave holes in the list (or renumber, but
2580 * it would be nice not to have yet another set of numbers to translate
2582 for (uint32_t number
= 0; number
< target
->reg_cache
->num_regs
; number
++) {
2583 struct reg
*r
= &target
->reg_cache
->reg_list
[number
];
2587 r
->type
= &riscv_reg_arch_type
;
2588 r
->arch_info
= shared_reg_info
;
2590 r
->size
= riscv_xlen(target
);
2591 /* r->size is set in riscv_invalidate_register_cache, maybe because the
2592 * target is in theory allowed to change XLEN on us. But I expect a lot
2593 * of other things to break in that case as well. */
2594 if (number
<= GDB_REGNO_XPR31
) {
2595 r
->caller_save
= true;
2597 case GDB_REGNO_ZERO
:
2694 r
->group
= "general";
2695 r
->feature
= &feature_cpu
;
2696 } else if (number
== GDB_REGNO_PC
) {
2697 r
->caller_save
= true;
2698 sprintf(reg_name
, "pc");
2699 r
->group
= "general";
2700 r
->feature
= &feature_cpu
;
2701 } else if (number
>= GDB_REGNO_FPR0
&& number
<= GDB_REGNO_FPR31
) {
2702 r
->caller_save
= true;
2703 if (riscv_supports_extension(target
, riscv_current_hartid(target
),
2705 r
->reg_data_type
= &type_ieee_double
;
2707 } else if (riscv_supports_extension(target
,
2708 riscv_current_hartid(target
), 'F')) {
2709 r
->reg_data_type
= &type_ieee_single
;
2793 case GDB_REGNO_FS10
:
2796 case GDB_REGNO_FS11
:
2805 case GDB_REGNO_FT10
:
2808 case GDB_REGNO_FT11
:
2813 r
->feature
= &feature_fpu
;
2814 } else if (number
>= GDB_REGNO_CSR0
&& number
<= GDB_REGNO_CSR4095
) {
2816 r
->feature
= &feature_csr
;
2817 unsigned csr_number
= number
- GDB_REGNO_CSR0
;
2819 while (csr_info
[csr_info_index
].number
< csr_number
&&
2820 csr_info_index
< DIM(csr_info
) - 1) {
2823 if (csr_info
[csr_info_index
].number
== csr_number
) {
2824 r
->name
= csr_info
[csr_info_index
].name
;
2826 sprintf(reg_name
, "csr%d", csr_number
);
2827 /* Assume unnamed registers don't exist, unless we have some
2828 * configuration that tells us otherwise. That's important
2829 * because eg. Eclipse crashes if a target has too many
2830 * registers, and apparently has no way of only showing a
2831 * subset of registers in any case. */
2835 switch (csr_number
) {
2839 r
->exist
= riscv_supports_extension(target
,
2840 riscv_current_hartid(target
), 'F');
2842 r
->feature
= &feature_fpu
;
2848 case CSR_SCOUNTEREN
:
2854 r
->exist
= riscv_supports_extension(target
,
2855 riscv_current_hartid(target
), 'S');
2859 /* "In systems with only M-mode, or with both M-mode and
2860 * U-mode but without U-mode trap support, the medeleg and
2861 * mideleg registers should not exist." */
2862 r
->exist
= riscv_supports_extension(target
, riscv_current_hartid(target
), 'S') ||
2863 riscv_supports_extension(target
, riscv_current_hartid(target
), 'N');
2869 case CSR_HPMCOUNTER3H
:
2870 case CSR_HPMCOUNTER4H
:
2871 case CSR_HPMCOUNTER5H
:
2872 case CSR_HPMCOUNTER6H
:
2873 case CSR_HPMCOUNTER7H
:
2874 case CSR_HPMCOUNTER8H
:
2875 case CSR_HPMCOUNTER9H
:
2876 case CSR_HPMCOUNTER10H
:
2877 case CSR_HPMCOUNTER11H
:
2878 case CSR_HPMCOUNTER12H
:
2879 case CSR_HPMCOUNTER13H
:
2880 case CSR_HPMCOUNTER14H
:
2881 case CSR_HPMCOUNTER15H
:
2882 case CSR_HPMCOUNTER16H
:
2883 case CSR_HPMCOUNTER17H
:
2884 case CSR_HPMCOUNTER18H
:
2885 case CSR_HPMCOUNTER19H
:
2886 case CSR_HPMCOUNTER20H
:
2887 case CSR_HPMCOUNTER21H
:
2888 case CSR_HPMCOUNTER22H
:
2889 case CSR_HPMCOUNTER23H
:
2890 case CSR_HPMCOUNTER24H
:
2891 case CSR_HPMCOUNTER25H
:
2892 case CSR_HPMCOUNTER26H
:
2893 case CSR_HPMCOUNTER27H
:
2894 case CSR_HPMCOUNTER28H
:
2895 case CSR_HPMCOUNTER29H
:
2896 case CSR_HPMCOUNTER30H
:
2897 case CSR_HPMCOUNTER31H
:
2900 case CSR_MHPMCOUNTER3H
:
2901 case CSR_MHPMCOUNTER4H
:
2902 case CSR_MHPMCOUNTER5H
:
2903 case CSR_MHPMCOUNTER6H
:
2904 case CSR_MHPMCOUNTER7H
:
2905 case CSR_MHPMCOUNTER8H
:
2906 case CSR_MHPMCOUNTER9H
:
2907 case CSR_MHPMCOUNTER10H
:
2908 case CSR_MHPMCOUNTER11H
:
2909 case CSR_MHPMCOUNTER12H
:
2910 case CSR_MHPMCOUNTER13H
:
2911 case CSR_MHPMCOUNTER14H
:
2912 case CSR_MHPMCOUNTER15H
:
2913 case CSR_MHPMCOUNTER16H
:
2914 case CSR_MHPMCOUNTER17H
:
2915 case CSR_MHPMCOUNTER18H
:
2916 case CSR_MHPMCOUNTER19H
:
2917 case CSR_MHPMCOUNTER20H
:
2918 case CSR_MHPMCOUNTER21H
:
2919 case CSR_MHPMCOUNTER22H
:
2920 case CSR_MHPMCOUNTER23H
:
2921 case CSR_MHPMCOUNTER24H
:
2922 case CSR_MHPMCOUNTER25H
:
2923 case CSR_MHPMCOUNTER26H
:
2924 case CSR_MHPMCOUNTER27H
:
2925 case CSR_MHPMCOUNTER28H
:
2926 case CSR_MHPMCOUNTER29H
:
2927 case CSR_MHPMCOUNTER30H
:
2928 case CSR_MHPMCOUNTER31H
:
2929 r
->exist
= riscv_xlen(target
) == 32;
2933 if (!r
->exist
&& expose_csr
) {
2934 for (unsigned i
= 0; expose_csr
[i
].low
<= expose_csr
[i
].high
; i
++) {
2935 if (csr_number
>= expose_csr
[i
].low
&& csr_number
<= expose_csr
[i
].high
) {
2936 LOG_INFO("Exposing additional CSR %d", csr_number
);
2943 } else if (number
== GDB_REGNO_PRIV
) {
2944 sprintf(reg_name
, "priv");
2945 r
->group
= "general";
2946 r
->feature
= &feature_virtual
;
2950 /* Custom registers. */
2951 assert(expose_custom
);
2953 range_t
*range
= &expose_custom
[custom_range_index
];
2954 assert(range
->low
<= range
->high
);
2955 unsigned custom_number
= range
->low
+ custom_within_range
;
2957 r
->group
= "custom";
2958 r
->feature
= &feature_custom
;
2959 r
->arch_info
= calloc(1, sizeof(riscv_reg_info_t
));
2960 assert(r
->arch_info
);
2961 ((riscv_reg_info_t
*) r
->arch_info
)->target
= target
;
2962 ((riscv_reg_info_t
*) r
->arch_info
)->custom_number
= custom_number
;
2963 sprintf(reg_name
, "custom%d", custom_number
);
2965 custom_within_range
++;
2966 if (custom_within_range
> range
->high
- range
->low
) {
2967 custom_within_range
= 0;
2968 custom_range_index
++;
2974 reg_name
+= strlen(reg_name
) + 1;
2975 assert(reg_name
< info
->reg_names
+ target
->reg_cache
->num_regs
*
2977 r
->value
= &info
->reg_cache_values
[number
];