9 #include "target/target.h"
10 #include "target/algorithm.h"
11 #include "target/target_type.h"
13 #include "jtag/jtag.h"
14 #include "target/register.h"
15 #include "target/breakpoints.h"
16 #include "helper/time_support.h"
19 #include "rtos/rtos.h"
22 * Since almost everything can be accomplish by scanning the dbus register, all
23 * functions here assume dbus is already selected. The exception are functions
24 * called directly by OpenOCD, which can't assume anything about what's
25 * currently in IR. They should set IR to dbus explicitly.
31 * At the bottom of the stack are the OpenOCD JTAG functions:
36 * There are a few functions to just instantly shift a register and get its
42 * Because doing one scan and waiting for the result is slow, most functions
43 * batch up a bunch of dbus writes and then execute them all at once. They use
44 * the scans "class" for this:
49 * Usually you new(), call a bunch of add functions, then execute() and look
50 * at the results by calling scans_get...()
52 * Optimized functions will directly use the scans class above, but slightly
53 * lazier code will use the cache functions that in turn use the scans
58 * cache_set... update a local structure, which is then synced to the target
59 * with cache_write(). Only Debug RAM words that are actually changed are sent
60 * to the target. Afterwards use cache_get... to read results.
63 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
64 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
66 #define DIM(x) (sizeof(x)/sizeof(*x))
68 /* Constants for legacy SiFive hardware breakpoints. */
69 #define CSR_BPCONTROL_X (1<<0)
70 #define CSR_BPCONTROL_W (1<<1)
71 #define CSR_BPCONTROL_R (1<<2)
72 #define CSR_BPCONTROL_U (1<<3)
73 #define CSR_BPCONTROL_S (1<<4)
74 #define CSR_BPCONTROL_H (1<<5)
75 #define CSR_BPCONTROL_M (1<<6)
76 #define CSR_BPCONTROL_BPMATCH (0xf<<7)
77 #define CSR_BPCONTROL_BPACTION (0xff<<11)
79 #define DEBUG_ROM_START 0x800
80 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
81 #define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
82 #define DEBUG_RAM_START 0x400
84 #define SETHALTNOT 0x10c
86 /*** JTAG registers. ***/
88 #define DTMCONTROL 0x10
89 #define DTMCONTROL_DBUS_RESET (1<<16)
90 #define DTMCONTROL_IDLE (7<<10)
91 #define DTMCONTROL_ADDRBITS (0xf<<4)
92 #define DTMCONTROL_VERSION (0xf)
95 #define DBUS_OP_START 0
96 #define DBUS_OP_SIZE 2
103 DBUS_STATUS_SUCCESS
= 0,
104 DBUS_STATUS_FAILED
= 2,
107 #define DBUS_DATA_START 2
108 #define DBUS_DATA_SIZE 34
109 #define DBUS_ADDRESS_START 36
123 /*** Debug Bus registers. ***/
125 #define DMCONTROL 0x10
126 #define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
127 #define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
128 #define DMCONTROL_BUSERROR (7<<19)
129 #define DMCONTROL_SERIAL (3<<16)
130 #define DMCONTROL_AUTOINCREMENT (1<<15)
131 #define DMCONTROL_ACCESS (7<<12)
132 #define DMCONTROL_HARTID (0x3ff<<2)
133 #define DMCONTROL_NDRESET (1<<1)
134 #define DMCONTROL_FULLRESET 1
137 #define DMINFO_ABUSSIZE (0x7fU<<25)
138 #define DMINFO_SERIALCOUNT (0xf<<21)
139 #define DMINFO_ACCESS128 (1<<20)
140 #define DMINFO_ACCESS64 (1<<19)
141 #define DMINFO_ACCESS32 (1<<18)
142 #define DMINFO_ACCESS16 (1<<17)
143 #define DMINFO_ACCESS8 (1<<16)
144 #define DMINFO_DRAMSIZE (0x3f<<10)
145 #define DMINFO_AUTHENTICATED (1<<5)
146 #define DMINFO_AUTHBUSY (1<<4)
147 #define DMINFO_AUTHTYPE (3<<2)
148 #define DMINFO_VERSION 3
150 /*** Info about the core being debugged. ***/
152 #define DBUS_ADDRESS_UNKNOWN 0xffff
155 #define DRAM_CACHE_SIZE 16
157 uint8_t ir_dtmcontrol
[4] = {DTMCONTROL
};
158 struct scan_field select_dtmcontrol
= {
160 .out_value
= ir_dtmcontrol
162 uint8_t ir_dbus
[4] = {DBUS
};
163 struct scan_field select_dbus
= {
167 uint8_t ir_idcode
[4] = {0x1};
168 struct scan_field select_idcode
= {
170 .out_value
= ir_idcode
178 bool read
, write
, execute
;
182 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
183 int riscv_command_timeout_sec
= DEFAULT_COMMAND_TIMEOUT_SEC
;
185 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
186 int riscv_reset_timeout_sec
= DEFAULT_RESET_TIMEOUT_SEC
;
188 bool riscv_prefer_sba
;
194 /* In addition to the ones in the standard spec, we'll also expose additional
196 * The list is either NULL, or a series of ranges (inclusive), terminated with
199 /* Same, but for custom registers. */
200 range_t
*expose_custom
;
202 static uint32_t dtmcontrol_scan(struct target
*target
, uint32_t out
)
204 struct scan_field field
;
206 uint8_t out_value
[4];
208 buf_set_u32(out_value
, 0, 32, out
);
210 jtag_add_ir_scan(target
->tap
, &select_dtmcontrol
, TAP_IDLE
);
213 field
.out_value
= out_value
;
214 field
.in_value
= in_value
;
215 jtag_add_dr_scan(target
->tap
, 1, &field
, TAP_IDLE
);
217 /* Always return to dbus. */
218 jtag_add_ir_scan(target
->tap
, &select_dbus
, TAP_IDLE
);
220 int retval
= jtag_execute_queue();
221 if (retval
!= ERROR_OK
) {
222 LOG_ERROR("failed jtag scan: %d", retval
);
226 uint32_t in
= buf_get_u32(field
.in_value
, 0, 32);
227 LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out
, in
);
232 static struct target_type
*get_target_type(struct target
*target
)
234 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
237 LOG_ERROR("Target has not been initialized");
241 switch (info
->dtm_version
) {
243 return &riscv011_target
;
245 return &riscv013_target
;
247 LOG_ERROR("Unsupported DTM version: %d", info
->dtm_version
);
252 static int riscv_init_target(struct command_context
*cmd_ctx
,
253 struct target
*target
)
255 LOG_DEBUG("riscv_init_target()");
256 target
->arch_info
= calloc(1, sizeof(riscv_info_t
));
257 if (!target
->arch_info
)
259 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
260 riscv_info_init(target
, info
);
261 info
->cmd_ctx
= cmd_ctx
;
263 select_dtmcontrol
.num_bits
= target
->tap
->ir_length
;
264 select_dbus
.num_bits
= target
->tap
->ir_length
;
265 select_idcode
.num_bits
= target
->tap
->ir_length
;
267 riscv_semihosting_init(target
);
269 target
->debug_reason
= DBG_REASON_DBGRQ
;
274 static void riscv_free_registers(struct target
*target
)
276 /* Free the shared structure use for most registers. */
277 if (target
->reg_cache
) {
278 if (target
->reg_cache
->reg_list
) {
279 if (target
->reg_cache
->reg_list
[0].arch_info
)
280 free(target
->reg_cache
->reg_list
[0].arch_info
);
281 /* Free the ones we allocated separately. */
282 for (unsigned i
= GDB_REGNO_COUNT
; i
< target
->reg_cache
->num_regs
; i
++)
283 free(target
->reg_cache
->reg_list
[i
].arch_info
);
284 free(target
->reg_cache
->reg_list
);
286 free(target
->reg_cache
);
290 static void riscv_deinit_target(struct target
*target
)
292 LOG_DEBUG("riscv_deinit_target()");
293 struct target_type
*tt
= get_target_type(target
);
295 tt
->deinit_target(target
);
296 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
297 free(info
->reg_names
);
301 riscv_free_registers(target
);
303 target
->arch_info
= NULL
;
306 static int oldriscv_halt(struct target
*target
)
308 struct target_type
*tt
= get_target_type(target
);
309 return tt
->halt(target
);
312 static void trigger_from_breakpoint(struct trigger
*trigger
,
313 const struct breakpoint
*breakpoint
)
315 trigger
->address
= breakpoint
->address
;
316 trigger
->length
= breakpoint
->length
;
317 trigger
->mask
= ~0LL;
318 trigger
->read
= false;
319 trigger
->write
= false;
320 trigger
->execute
= true;
321 /* unique_id is unique across both breakpoints and watchpoints. */
322 trigger
->unique_id
= breakpoint
->unique_id
;
325 static int maybe_add_trigger_t1(struct target
*target
, unsigned hartid
,
326 struct trigger
*trigger
, uint64_t tdata1
)
330 const uint32_t bpcontrol_x
= 1<<0;
331 const uint32_t bpcontrol_w
= 1<<1;
332 const uint32_t bpcontrol_r
= 1<<2;
333 const uint32_t bpcontrol_u
= 1<<3;
334 const uint32_t bpcontrol_s
= 1<<4;
335 const uint32_t bpcontrol_h
= 1<<5;
336 const uint32_t bpcontrol_m
= 1<<6;
337 const uint32_t bpcontrol_bpmatch
= 0xf << 7;
338 const uint32_t bpcontrol_bpaction
= 0xff << 11;
340 if (tdata1
& (bpcontrol_r
| bpcontrol_w
| bpcontrol_x
)) {
341 /* Trigger is already in use, presumably by user code. */
342 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
345 tdata1
= set_field(tdata1
, bpcontrol_r
, trigger
->read
);
346 tdata1
= set_field(tdata1
, bpcontrol_w
, trigger
->write
);
347 tdata1
= set_field(tdata1
, bpcontrol_x
, trigger
->execute
);
348 tdata1
= set_field(tdata1
, bpcontrol_u
,
349 !!(r
->misa
[hartid
] & (1 << ('U' - 'A'))));
350 tdata1
= set_field(tdata1
, bpcontrol_s
,
351 !!(r
->misa
[hartid
] & (1 << ('S' - 'A'))));
352 tdata1
= set_field(tdata1
, bpcontrol_h
,
353 !!(r
->misa
[hartid
] & (1 << ('H' - 'A'))));
354 tdata1
|= bpcontrol_m
;
355 tdata1
= set_field(tdata1
, bpcontrol_bpmatch
, 0); /* exact match */
356 tdata1
= set_field(tdata1
, bpcontrol_bpaction
, 0); /* cause bp exception */
358 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, tdata1
);
360 riscv_reg_t tdata1_rb
;
361 if (riscv_get_register_on_hart(target
, &tdata1_rb
, hartid
,
362 GDB_REGNO_TDATA1
) != ERROR_OK
)
364 LOG_DEBUG("tdata1=0x%" PRIx64
, tdata1_rb
);
366 if (tdata1
!= tdata1_rb
) {
367 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
368 PRIx64
" to tdata1 it contains 0x%" PRIx64
,
370 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
371 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
374 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA2
, trigger
->address
);
379 static int maybe_add_trigger_t2(struct target
*target
, unsigned hartid
,
380 struct trigger
*trigger
, uint64_t tdata1
)
384 /* tselect is already set */
385 if (tdata1
& (MCONTROL_EXECUTE
| MCONTROL_STORE
| MCONTROL_LOAD
)) {
386 /* Trigger is already in use, presumably by user code. */
387 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
390 /* address/data match trigger */
391 tdata1
|= MCONTROL_DMODE(riscv_xlen(target
));
392 tdata1
= set_field(tdata1
, MCONTROL_ACTION
,
393 MCONTROL_ACTION_DEBUG_MODE
);
394 tdata1
= set_field(tdata1
, MCONTROL_MATCH
, MCONTROL_MATCH_EQUAL
);
395 tdata1
|= MCONTROL_M
;
396 if (r
->misa
[hartid
] & (1 << ('H' - 'A')))
397 tdata1
|= MCONTROL_H
;
398 if (r
->misa
[hartid
] & (1 << ('S' - 'A')))
399 tdata1
|= MCONTROL_S
;
400 if (r
->misa
[hartid
] & (1 << ('U' - 'A')))
401 tdata1
|= MCONTROL_U
;
403 if (trigger
->execute
)
404 tdata1
|= MCONTROL_EXECUTE
;
406 tdata1
|= MCONTROL_LOAD
;
408 tdata1
|= MCONTROL_STORE
;
410 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, tdata1
);
413 int result
= riscv_get_register_on_hart(target
, &tdata1_rb
, hartid
, GDB_REGNO_TDATA1
);
414 if (result
!= ERROR_OK
)
416 LOG_DEBUG("tdata1=0x%" PRIx64
, tdata1_rb
);
418 if (tdata1
!= tdata1_rb
) {
419 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
420 PRIx64
" to tdata1 it contains 0x%" PRIx64
,
422 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
423 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
426 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA2
, trigger
->address
);
431 static int add_trigger(struct target
*target
, struct trigger
*trigger
)
435 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
438 /* In RTOS mode, we need to set the same trigger in the same slot on every
439 * hart, to keep up the illusion that each hart is a thread running on the
442 /* Otherwise, we just set the trigger on the one hart this target deals
445 riscv_reg_t tselect
[RISCV_MAX_HARTS
];
448 for (int hartid
= 0; hartid
< riscv_count_harts(target
); ++hartid
) {
449 if (!riscv_hart_enabled(target
, hartid
))
453 int result
= riscv_get_register_on_hart(target
, &tselect
[hartid
],
454 hartid
, GDB_REGNO_TSELECT
);
455 if (result
!= ERROR_OK
)
458 assert(first_hart
>= 0);
461 for (i
= 0; i
< r
->trigger_count
[first_hart
]; i
++) {
462 if (r
->trigger_unique_id
[i
] != -1)
465 riscv_set_register_on_hart(target
, first_hart
, GDB_REGNO_TSELECT
, i
);
468 int result
= riscv_get_register_on_hart(target
, &tdata1
, first_hart
,
470 if (result
!= ERROR_OK
)
472 int type
= get_field(tdata1
, MCONTROL_TYPE(riscv_xlen(target
)));
475 for (int hartid
= first_hart
; hartid
< riscv_count_harts(target
); ++hartid
) {
476 if (!riscv_hart_enabled(target
, hartid
))
478 if (hartid
> first_hart
)
479 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, i
);
482 result
= maybe_add_trigger_t1(target
, hartid
, trigger
, tdata1
);
485 result
= maybe_add_trigger_t2(target
, hartid
, trigger
, tdata1
);
488 LOG_DEBUG("trigger %d has unknown type %d", i
, type
);
492 if (result
!= ERROR_OK
)
496 if (result
!= ERROR_OK
)
499 LOG_DEBUG("[%d] Using trigger %d (type %d) for bp %d", target
->coreid
,
500 i
, type
, trigger
->unique_id
);
501 r
->trigger_unique_id
[i
] = trigger
->unique_id
;
505 for (int hartid
= first_hart
; hartid
< riscv_count_harts(target
); ++hartid
) {
506 if (!riscv_hart_enabled(target
, hartid
))
508 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
,
512 if (i
>= r
->trigger_count
[first_hart
]) {
513 LOG_ERROR("Couldn't find an available hardware trigger.");
514 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
520 int riscv_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
522 LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR
, target
->coreid
, breakpoint
->address
);
524 if (breakpoint
->type
== BKPT_SOFT
) {
525 /** @todo check RVC for size/alignment */
526 if (!(breakpoint
->length
== 4 || breakpoint
->length
== 2)) {
527 LOG_ERROR("Invalid breakpoint length %d", breakpoint
->length
);
531 if (0 != (breakpoint
->address
% 2)) {
532 LOG_ERROR("Invalid breakpoint alignment for address 0x%" TARGET_PRIxADDR
, breakpoint
->address
);
536 if (target_read_memory(target
, breakpoint
->address
, 2, breakpoint
->length
/ 2,
537 breakpoint
->orig_instr
) != ERROR_OK
) {
538 LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR
,
539 breakpoint
->address
);
544 buf_set_u32(buff
, 0, breakpoint
->length
* CHAR_BIT
, breakpoint
->length
== 4 ? ebreak() : ebreak_c());
545 int const retval
= target_write_memory(target
, breakpoint
->address
, 2, breakpoint
->length
/ 2, buff
);
547 if (retval
!= ERROR_OK
) {
548 LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%"
549 TARGET_PRIxADDR
, breakpoint
->length
, breakpoint
->address
);
553 } else if (breakpoint
->type
== BKPT_HARD
) {
554 struct trigger trigger
;
555 trigger_from_breakpoint(&trigger
, breakpoint
);
556 int const result
= add_trigger(target
, &trigger
);
557 if (result
!= ERROR_OK
)
560 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
561 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
564 breakpoint
->set
= true;
568 static int remove_trigger(struct target
*target
, struct trigger
*trigger
)
572 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
576 for (int hartid
= 0; hartid
< riscv_count_harts(target
); ++hartid
) {
577 if (!riscv_hart_enabled(target
, hartid
))
579 if (first_hart
< 0) {
584 assert(first_hart
>= 0);
587 for (i
= 0; i
< r
->trigger_count
[first_hart
]; i
++) {
588 if (r
->trigger_unique_id
[i
] == trigger
->unique_id
)
591 if (i
>= r
->trigger_count
[first_hart
]) {
592 LOG_ERROR("Couldn't find the hardware resources used by hardware "
596 LOG_DEBUG("[%d] Stop using resource %d for bp %d", target
->coreid
, i
,
598 for (int hartid
= first_hart
; hartid
< riscv_count_harts(target
); ++hartid
) {
599 if (!riscv_hart_enabled(target
, hartid
))
602 int result
= riscv_get_register_on_hart(target
, &tselect
, hartid
, GDB_REGNO_TSELECT
);
603 if (result
!= ERROR_OK
)
605 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, i
);
606 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
607 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, tselect
);
609 r
->trigger_unique_id
[i
] = -1;
614 int riscv_remove_breakpoint(struct target
*target
,
615 struct breakpoint
*breakpoint
)
617 if (breakpoint
->type
== BKPT_SOFT
) {
618 if (target_write_memory(target
, breakpoint
->address
, 2, breakpoint
->length
/ 2,
619 breakpoint
->orig_instr
) != ERROR_OK
) {
620 LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
621 "0x%" TARGET_PRIxADDR
, breakpoint
->length
, breakpoint
->address
);
625 } else if (breakpoint
->type
== BKPT_HARD
) {
626 struct trigger trigger
;
627 trigger_from_breakpoint(&trigger
, breakpoint
);
628 int result
= remove_trigger(target
, &trigger
);
629 if (result
!= ERROR_OK
)
633 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
634 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
637 breakpoint
->set
= false;
642 static void trigger_from_watchpoint(struct trigger
*trigger
,
643 const struct watchpoint
*watchpoint
)
645 trigger
->address
= watchpoint
->address
;
646 trigger
->length
= watchpoint
->length
;
647 trigger
->mask
= watchpoint
->mask
;
648 trigger
->value
= watchpoint
->value
;
649 trigger
->read
= (watchpoint
->rw
== WPT_READ
|| watchpoint
->rw
== WPT_ACCESS
);
650 trigger
->write
= (watchpoint
->rw
== WPT_WRITE
|| watchpoint
->rw
== WPT_ACCESS
);
651 trigger
->execute
= false;
652 /* unique_id is unique across both breakpoints and watchpoints. */
653 trigger
->unique_id
= watchpoint
->unique_id
;
656 int riscv_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
658 struct trigger trigger
;
659 trigger_from_watchpoint(&trigger
, watchpoint
);
661 int result
= add_trigger(target
, &trigger
);
662 if (result
!= ERROR_OK
)
664 watchpoint
->set
= true;
669 int riscv_remove_watchpoint(struct target
*target
,
670 struct watchpoint
*watchpoint
)
672 LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR
, target
->coreid
, watchpoint
->address
);
674 struct trigger trigger
;
675 trigger_from_watchpoint(&trigger
, watchpoint
);
677 int result
= remove_trigger(target
, &trigger
);
678 if (result
!= ERROR_OK
)
680 watchpoint
->set
= false;
685 /* Sets *hit_watchpoint to the first watchpoint identified as causing the
688 * The GDB server uses this information to tell GDB what data address has
689 * been hit, which enables GDB to print the hit variable along with its old
691 int riscv_hit_watchpoint(struct target
*target
, struct watchpoint
**hit_watchpoint
)
693 struct watchpoint
*wp
= target
->watchpoints
;
695 LOG_DEBUG("Current hartid = %d", riscv_current_hartid(target
));
697 /*TODO instead of disassembling the instruction that we think caused the
698 * trigger, check the hit bit of each watchpoint first. The hit bit is
699 * simpler and more reliable to check but as it is optional and relatively
700 * new, not all hardware will implement it */
702 riscv_get_register(target
, &dpc
, GDB_REGNO_DPC
);
703 const uint8_t length
= 4;
704 LOG_DEBUG("dpc is 0x%" PRIx64
, dpc
);
706 /* fetch the instruction at dpc */
707 uint8_t buffer
[length
];
708 if (target_read_buffer(target
, dpc
, length
, buffer
) != ERROR_OK
) {
709 LOG_ERROR("Failed to read instruction at dpc 0x%" PRIx64
, dpc
);
713 uint32_t instruction
= 0;
715 for (int i
= 0; i
< length
; i
++) {
716 LOG_DEBUG("Next byte is %x", buffer
[i
]);
717 instruction
+= (buffer
[i
] << 8 * i
);
719 LOG_DEBUG("Full instruction is %x", instruction
);
721 /* find out which memory address is accessed by the instruction at dpc */
722 /* opcode is first 7 bits of the instruction */
723 uint8_t opcode
= instruction
& 0x7F;
726 riscv_reg_t mem_addr
;
728 if (opcode
== MATCH_LB
|| opcode
== MATCH_SB
) {
729 rs1
= (instruction
& 0xf8000) >> 15;
730 riscv_get_register(target
, &mem_addr
, rs1
);
732 if (opcode
== MATCH_SB
) {
733 LOG_DEBUG("%x is store instruction", instruction
);
734 imm
= ((instruction
& 0xf80) >> 7) | ((instruction
& 0xfe000000) >> 20);
736 LOG_DEBUG("%x is load instruction", instruction
);
737 imm
= (instruction
& 0xfff00000) >> 20;
739 /* sign extend 12-bit imm to 16-bits */
743 LOG_DEBUG("memory address=0x%" PRIx64
, mem_addr
);
745 LOG_DEBUG("%x is not a RV32I load or store", instruction
);
750 /*TODO support length/mask */
751 if (wp
->address
== mem_addr
) {
752 *hit_watchpoint
= wp
;
753 LOG_DEBUG("Hit address=%" TARGET_PRIxADDR
, wp
->address
);
759 /* No match found - either we hit a watchpoint caused by an instruction that
760 * this function does not yet disassemble, or we hit a breakpoint.
762 * OpenOCD will behave as if this function had never been implemented i.e.
763 * report the halt to GDB with no address information. */
768 static int oldriscv_step(struct target
*target
, int current
, uint32_t address
,
769 int handle_breakpoints
)
771 struct target_type
*tt
= get_target_type(target
);
772 return tt
->step(target
, current
, address
, handle_breakpoints
);
775 static int old_or_new_riscv_step(
776 struct target
*target
,
778 target_addr_t address
,
779 int handle_breakpoints
782 LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints
);
783 if (r
->is_halted
== NULL
)
784 return oldriscv_step(target
, current
, address
, handle_breakpoints
);
786 return riscv_openocd_step(target
, current
, address
, handle_breakpoints
);
790 static int riscv_examine(struct target
*target
)
792 LOG_DEBUG("riscv_examine()");
793 if (target_was_examined(target
)) {
794 LOG_DEBUG("Target was already examined.");
798 /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
800 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
801 uint32_t dtmcontrol
= dtmcontrol_scan(target
, 0);
802 LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol
);
803 info
->dtm_version
= get_field(dtmcontrol
, DTMCONTROL_VERSION
);
804 LOG_DEBUG(" version=0x%x", info
->dtm_version
);
806 struct target_type
*tt
= get_target_type(target
);
810 int result
= tt
->init_target(info
->cmd_ctx
, target
);
811 if (result
!= ERROR_OK
)
814 return tt
->examine(target
);
817 static int oldriscv_poll(struct target
*target
)
819 struct target_type
*tt
= get_target_type(target
);
820 return tt
->poll(target
);
823 static int old_or_new_riscv_poll(struct target
*target
)
826 if (r
->is_halted
== NULL
)
827 return oldriscv_poll(target
);
829 return riscv_openocd_poll(target
);
832 static int old_or_new_riscv_halt(struct target
*target
)
835 if (r
->is_halted
== NULL
)
836 return oldriscv_halt(target
);
838 return riscv_openocd_halt(target
);
841 static int riscv_assert_reset(struct target
*target
)
843 LOG_DEBUG("[%d]", target
->coreid
);
844 struct target_type
*tt
= get_target_type(target
);
845 riscv_invalidate_register_cache(target
);
846 return tt
->assert_reset(target
);
849 static int riscv_deassert_reset(struct target
*target
)
851 LOG_DEBUG("[%d]", target
->coreid
);
852 struct target_type
*tt
= get_target_type(target
);
853 return tt
->deassert_reset(target
);
857 static int oldriscv_resume(struct target
*target
, int current
, uint32_t address
,
858 int handle_breakpoints
, int debug_execution
)
860 struct target_type
*tt
= get_target_type(target
);
861 return tt
->resume(target
, current
, address
, handle_breakpoints
,
865 static int old_or_new_riscv_resume(
866 struct target
*target
,
868 target_addr_t address
,
869 int handle_breakpoints
,
872 LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints
);
874 struct target_list
*targets
= target
->head
;
875 int result
= ERROR_OK
;
877 struct target
*t
= targets
->target
;
878 riscv_info_t
*r
= riscv_info(t
);
879 if (r
->is_halted
== NULL
) {
880 if (oldriscv_resume(t
, current
, address
, handle_breakpoints
,
881 debug_execution
) != ERROR_OK
)
884 if (riscv_openocd_resume(t
, current
, address
,
885 handle_breakpoints
, debug_execution
) != ERROR_OK
)
888 targets
= targets
->next
;
894 if (r
->is_halted
== NULL
)
895 return oldriscv_resume(target
, current
, address
, handle_breakpoints
, debug_execution
);
897 return riscv_openocd_resume(target
, current
, address
, handle_breakpoints
, debug_execution
);
900 static int riscv_select_current_hart(struct target
*target
)
903 if (riscv_rtos_enabled(target
)) {
904 if (r
->rtos_hartid
== -1)
905 r
->rtos_hartid
= target
->rtos
->current_threadid
- 1;
906 return riscv_set_current_hartid(target
, r
->rtos_hartid
);
908 return riscv_set_current_hartid(target
, target
->coreid
);
911 static int riscv_read_memory(struct target
*target
, target_addr_t address
,
912 uint32_t size
, uint32_t count
, uint8_t *buffer
)
914 if (riscv_select_current_hart(target
) != ERROR_OK
)
916 struct target_type
*tt
= get_target_type(target
);
917 return tt
->read_memory(target
, address
, size
, count
, buffer
);
920 static int riscv_write_memory(struct target
*target
, target_addr_t address
,
921 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
923 if (riscv_select_current_hart(target
) != ERROR_OK
)
925 struct target_type
*tt
= get_target_type(target
);
926 return tt
->write_memory(target
, address
, size
, count
, buffer
);
929 static int riscv_get_gdb_reg_list_internal(struct target
*target
,
930 struct reg
**reg_list
[], int *reg_list_size
,
931 enum target_register_class reg_class
, bool read
)
934 LOG_DEBUG("rtos_hartid=%d, current_hartid=%d, reg_class=%d, read=%d",
935 r
->rtos_hartid
, r
->current_hartid
, reg_class
, read
);
937 if (!target
->reg_cache
) {
938 LOG_ERROR("Target not initialized. Return ERROR_FAIL.");
942 if (riscv_select_current_hart(target
) != ERROR_OK
)
946 case REG_CLASS_GENERAL
:
950 *reg_list_size
= target
->reg_cache
->num_regs
;
953 LOG_ERROR("Unsupported reg_class: %d", reg_class
);
957 *reg_list
= calloc(*reg_list_size
, sizeof(struct reg
*));
961 for (int i
= 0; i
< *reg_list_size
; i
++) {
962 assert(!target
->reg_cache
->reg_list
[i
].valid
||
963 target
->reg_cache
->reg_list
[i
].size
> 0);
964 (*reg_list
)[i
] = &target
->reg_cache
->reg_list
[i
];
965 if (read
&& !target
->reg_cache
->reg_list
[i
].valid
) {
966 if (target
->reg_cache
->reg_list
[i
].type
->get(
967 &target
->reg_cache
->reg_list
[i
]) != ERROR_OK
)
968 /* This function is called when first connecting to gdb,
969 * resulting in an attempt to read all kinds of registers which
970 * probably will fail. Ignore these failures, and when
971 * encountered stop reading to save time. */
979 static int riscv_get_gdb_reg_list(struct target
*target
,
980 struct reg
**reg_list
[], int *reg_list_size
,
981 enum target_register_class reg_class
)
983 return riscv_get_gdb_reg_list_internal(target
, reg_list
, reg_list_size
,
987 static int riscv_arch_state(struct target
*target
)
989 struct target_type
*tt
= get_target_type(target
);
990 return tt
->arch_state(target
);
993 /* Algorithm must end with a software breakpoint instruction. */
994 static int riscv_run_algorithm(struct target
*target
, int num_mem_params
,
995 struct mem_param
*mem_params
, int num_reg_params
,
996 struct reg_param
*reg_params
, target_addr_t entry_point
,
997 target_addr_t exit_point
, int timeout_ms
, void *arch_info
)
999 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
1001 if (num_mem_params
> 0) {
1002 LOG_ERROR("Memory parameters are not supported for RISC-V algorithms.");
1006 if (target
->state
!= TARGET_HALTED
) {
1007 LOG_WARNING("target not halted");
1008 return ERROR_TARGET_NOT_HALTED
;
1011 /* Save registers */
1012 struct reg
*reg_pc
= register_get_by_name(target
->reg_cache
, "pc", 1);
1013 if (!reg_pc
|| reg_pc
->type
->get(reg_pc
) != ERROR_OK
)
1015 uint64_t saved_pc
= buf_get_u64(reg_pc
->value
, 0, reg_pc
->size
);
1017 uint64_t saved_regs
[32];
1018 for (int i
= 0; i
< num_reg_params
; i
++) {
1019 if (reg_params
[i
].direction
== PARAM_IN
)
1022 LOG_DEBUG("save %s", reg_params
[i
].reg_name
);
1023 struct reg
*r
= register_get_by_name(target
->reg_cache
, reg_params
[i
].reg_name
, 0);
1025 LOG_ERROR("Couldn't find register named '%s'", reg_params
[i
].reg_name
);
1029 if (r
->size
!= reg_params
[i
].size
) {
1030 LOG_ERROR("Register %s is %d bits instead of %d bits.",
1031 reg_params
[i
].reg_name
, r
->size
, reg_params
[i
].size
);
1035 if (r
->number
> GDB_REGNO_XPR31
) {
1036 LOG_ERROR("Only GPRs can be use as argument registers.");
1040 if (r
->type
->get(r
) != ERROR_OK
)
1042 saved_regs
[r
->number
] = buf_get_u64(r
->value
, 0, r
->size
);
1043 if (r
->type
->set(r
, reg_params
[i
].value
) != ERROR_OK
)
1048 /* Disable Interrupts before attempting to run the algorithm. */
1049 uint64_t current_mstatus
;
1050 uint8_t mstatus_bytes
[8];
1052 LOG_DEBUG("Disabling Interrupts");
1053 struct reg
*reg_mstatus
= register_get_by_name(target
->reg_cache
,
1056 LOG_ERROR("Couldn't find mstatus!");
1060 reg_mstatus
->type
->get(reg_mstatus
);
1061 current_mstatus
= buf_get_u64(reg_mstatus
->value
, 0, reg_mstatus
->size
);
1062 uint64_t ie_mask
= MSTATUS_MIE
| MSTATUS_HIE
| MSTATUS_SIE
| MSTATUS_UIE
;
1063 buf_set_u64(mstatus_bytes
, 0, info
->xlen
[0], set_field(current_mstatus
,
1066 reg_mstatus
->type
->set(reg_mstatus
, mstatus_bytes
);
1069 LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR
, entry_point
);
1070 if (oldriscv_resume(target
, 0, entry_point
, 0, 0) != ERROR_OK
)
1073 int64_t start
= timeval_ms();
1074 while (target
->state
!= TARGET_HALTED
) {
1075 LOG_DEBUG("poll()");
1076 int64_t now
= timeval_ms();
1077 if (now
- start
> timeout_ms
) {
1078 LOG_ERROR("Algorithm timed out after %d ms.", timeout_ms
);
1079 LOG_ERROR(" now = 0x%08x", (uint32_t) now
);
1080 LOG_ERROR(" start = 0x%08x", (uint32_t) start
);
1081 oldriscv_halt(target
);
1082 old_or_new_riscv_poll(target
);
1083 return ERROR_TARGET_TIMEOUT
;
1086 int result
= old_or_new_riscv_poll(target
);
1087 if (result
!= ERROR_OK
)
1091 if (reg_pc
->type
->get(reg_pc
) != ERROR_OK
)
1093 uint64_t final_pc
= buf_get_u64(reg_pc
->value
, 0, reg_pc
->size
);
1094 if (final_pc
!= exit_point
) {
1095 LOG_ERROR("PC ended up at 0x%" PRIx64
" instead of 0x%"
1096 TARGET_PRIxADDR
, final_pc
, exit_point
);
1100 /* Restore Interrupts */
1101 LOG_DEBUG("Restoring Interrupts");
1102 buf_set_u64(mstatus_bytes
, 0, info
->xlen
[0], current_mstatus
);
1103 reg_mstatus
->type
->set(reg_mstatus
, mstatus_bytes
);
1105 /* Restore registers */
1107 buf_set_u64(buf
, 0, info
->xlen
[0], saved_pc
);
1108 if (reg_pc
->type
->set(reg_pc
, buf
) != ERROR_OK
)
1111 for (int i
= 0; i
< num_reg_params
; i
++) {
1112 LOG_DEBUG("restore %s", reg_params
[i
].reg_name
);
1113 struct reg
*r
= register_get_by_name(target
->reg_cache
, reg_params
[i
].reg_name
, 0);
1114 buf_set_u64(buf
, 0, info
->xlen
[0], saved_regs
[r
->number
]);
1115 if (r
->type
->set(r
, buf
) != ERROR_OK
)
1122 /* Should run code on the target to perform CRC of
1123 memory. Not yet implemented.
1126 static int riscv_checksum_memory(struct target
*target
,
1127 target_addr_t address
, uint32_t count
,
1130 *checksum
= 0xFFFFFFFF;
1131 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1134 /*** OpenOCD Helper Functions ***/
1136 enum riscv_poll_hart
{
1138 RPH_DISCOVERED_HALTED
,
1139 RPH_DISCOVERED_RUNNING
,
1142 static enum riscv_poll_hart
riscv_poll_hart(struct target
*target
, int hartid
)
1145 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
1148 LOG_DEBUG("polling hart %d, target->state=%d", hartid
, target
->state
);
1150 /* If OpenOCD thinks we're running but this hart is halted then it's time
1151 * to raise an event. */
1152 bool halted
= riscv_is_halted(target
);
1153 if (target
->state
!= TARGET_HALTED
&& halted
) {
1154 LOG_DEBUG(" triggered a halt");
1156 return RPH_DISCOVERED_HALTED
;
1157 } else if (target
->state
!= TARGET_RUNNING
&& !halted
) {
1158 LOG_DEBUG(" triggered running");
1159 target
->state
= TARGET_RUNNING
;
1160 return RPH_DISCOVERED_RUNNING
;
1163 return RPH_NO_CHANGE
;
1166 int set_debug_reason(struct target
*target
, int hartid
)
1168 switch (riscv_halt_reason(target
, hartid
)) {
1169 case RISCV_HALT_BREAKPOINT
:
1170 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1172 case RISCV_HALT_TRIGGER
:
1173 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1175 case RISCV_HALT_INTERRUPT
:
1176 target
->debug_reason
= DBG_REASON_DBGRQ
;
1178 case RISCV_HALT_SINGLESTEP
:
1179 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1181 case RISCV_HALT_UNKNOWN
:
1182 target
->debug_reason
= DBG_REASON_UNDEFINED
;
1184 case RISCV_HALT_ERROR
:
1190 /*** OpenOCD Interface ***/
1191 int riscv_openocd_poll(struct target
*target
)
1193 LOG_DEBUG("polling all harts");
1194 int halted_hart
= -1;
1195 if (riscv_rtos_enabled(target
)) {
1196 /* Check every hart for an event. */
1197 for (int i
= 0; i
< riscv_count_harts(target
); ++i
) {
1198 enum riscv_poll_hart out
= riscv_poll_hart(target
, i
);
1201 case RPH_DISCOVERED_RUNNING
:
1203 case RPH_DISCOVERED_HALTED
:
1210 if (halted_hart
== -1) {
1211 LOG_DEBUG(" no harts just halted, target->state=%d", target
->state
);
1214 LOG_DEBUG(" hart %d halted", halted_hart
);
1216 /* If we're here then at least one hart triggered. That means
1217 * we want to go and halt _every_ hart in the system, as that's
1218 * the invariant we hold here. Some harts might have already
1219 * halted (as we're either in single-step mode or they also
1220 * triggered a breakpoint), so don't attempt to halt those
1222 for (int i
= 0; i
< riscv_count_harts(target
); ++i
)
1223 riscv_halt_one_hart(target
, i
);
1225 } else if (target
->smp
) {
1226 bool halt_discovered
= false;
1227 bool newly_halted
[128] = {0};
1229 for (struct target_list
*list
= target
->head
; list
!= NULL
;
1230 list
= list
->next
, i
++) {
1231 struct target
*t
= list
->target
;
1232 riscv_info_t
*r
= riscv_info(t
);
1233 assert(i
< DIM(newly_halted
));
1234 enum riscv_poll_hart out
= riscv_poll_hart(t
, r
->current_hartid
);
1238 case RPH_DISCOVERED_RUNNING
:
1239 t
->state
= TARGET_RUNNING
;
1241 case RPH_DISCOVERED_HALTED
:
1242 halt_discovered
= true;
1243 newly_halted
[i
] = true;
1244 t
->state
= TARGET_HALTED
;
1245 if (set_debug_reason(t
, r
->current_hartid
) != ERROR_OK
)
1253 if (halt_discovered
) {
1254 LOG_DEBUG("Halt other targets in this SMP group.");
1256 for (struct target_list
*list
= target
->head
; list
!= NULL
;
1257 list
= list
->next
, i
++) {
1258 struct target
*t
= list
->target
;
1259 riscv_info_t
*r
= riscv_info(t
);
1260 if (t
->state
!= TARGET_HALTED
) {
1261 if (riscv_halt_one_hart(t
, r
->current_hartid
) != ERROR_OK
)
1263 t
->state
= TARGET_HALTED
;
1264 if (set_debug_reason(t
, r
->current_hartid
) != ERROR_OK
)
1266 newly_halted
[i
] = true;
1270 /* Now that we have all our ducks in a row, tell the higher layers
1271 * what just happened. */
1273 for (struct target_list
*list
= target
->head
; list
!= NULL
;
1274 list
= list
->next
, i
++) {
1275 struct target
*t
= list
->target
;
1276 if (newly_halted
[i
])
1277 target_call_event_callbacks(t
, TARGET_EVENT_HALTED
);
1283 enum riscv_poll_hart out
= riscv_poll_hart(target
,
1284 riscv_current_hartid(target
));
1285 if (out
== RPH_NO_CHANGE
|| out
== RPH_DISCOVERED_RUNNING
)
1287 else if (out
== RPH_ERROR
)
1290 halted_hart
= riscv_current_hartid(target
);
1291 LOG_DEBUG(" hart %d halted", halted_hart
);
1294 target
->state
= TARGET_HALTED
;
1295 if (set_debug_reason(target
, halted_hart
) != ERROR_OK
)
1298 if (riscv_rtos_enabled(target
)) {
1299 target
->rtos
->current_threadid
= halted_hart
+ 1;
1300 target
->rtos
->current_thread
= halted_hart
+ 1;
1301 riscv_set_rtos_hartid(target
, halted_hart
);
1304 target
->state
= TARGET_HALTED
;
1306 if (target
->debug_reason
== DBG_REASON_BREAKPOINT
) {
1308 if (riscv_semihosting(target
, &retval
) != 0)
1312 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1316 int riscv_openocd_halt(struct target
*target
)
1321 LOG_DEBUG("[%d] halting all harts", target
->coreid
);
1324 LOG_DEBUG("Halt other targets in this SMP group.");
1325 struct target_list
*targets
= target
->head
;
1328 struct target
*t
= targets
->target
;
1329 targets
= targets
->next
;
1330 if (t
->state
!= TARGET_HALTED
) {
1331 if (riscv_halt_all_harts(t
) != ERROR_OK
)
1332 result
= ERROR_FAIL
;
1336 result
= riscv_halt_all_harts(target
);
1339 if (riscv_rtos_enabled(target
)) {
1340 if (r
->rtos_hartid
!= -1) {
1341 LOG_DEBUG("halt requested on RTOS hartid %d", r
->rtos_hartid
);
1342 target
->rtos
->current_threadid
= r
->rtos_hartid
+ 1;
1343 target
->rtos
->current_thread
= r
->rtos_hartid
+ 1;
1345 LOG_DEBUG("halt requested, but no known RTOS hartid");
1348 target
->state
= TARGET_HALTED
;
1349 target
->debug_reason
= DBG_REASON_DBGRQ
;
1350 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1354 int riscv_openocd_resume(
1355 struct target
*target
,
1357 target_addr_t address
,
1358 int handle_breakpoints
,
1359 int debug_execution
)
1361 LOG_DEBUG("debug_reason=%d", target
->debug_reason
);
1364 riscv_set_register(target
, GDB_REGNO_PC
, address
);
1366 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
1367 /* To be able to run off a trigger, disable all the triggers, step, and
1368 * then resume as usual. */
1369 struct watchpoint
*watchpoint
= target
->watchpoints
;
1370 bool trigger_temporarily_cleared
[RISCV_MAX_HWBPS
] = {0};
1373 int result
= ERROR_OK
;
1374 while (watchpoint
&& result
== ERROR_OK
) {
1375 LOG_DEBUG("watchpoint %d: set=%d", i
, watchpoint
->set
);
1376 trigger_temporarily_cleared
[i
] = watchpoint
->set
;
1377 if (watchpoint
->set
)
1378 result
= riscv_remove_watchpoint(target
, watchpoint
);
1379 watchpoint
= watchpoint
->next
;
1383 if (result
== ERROR_OK
)
1384 result
= riscv_step_rtos_hart(target
);
1386 watchpoint
= target
->watchpoints
;
1388 while (watchpoint
) {
1389 LOG_DEBUG("watchpoint %d: cleared=%d", i
, trigger_temporarily_cleared
[i
]);
1390 if (trigger_temporarily_cleared
[i
]) {
1391 if (result
== ERROR_OK
)
1392 result
= riscv_add_watchpoint(target
, watchpoint
);
1394 riscv_add_watchpoint(target
, watchpoint
);
1396 watchpoint
= watchpoint
->next
;
1400 if (result
!= ERROR_OK
)
1404 int out
= riscv_resume_all_harts(target
);
1405 if (out
!= ERROR_OK
) {
1406 LOG_ERROR("unable to resume all harts");
1410 register_cache_invalidate(target
->reg_cache
);
1411 target
->state
= TARGET_RUNNING
;
1412 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1416 int riscv_openocd_step(
1417 struct target
*target
,
1419 target_addr_t address
,
1420 int handle_breakpoints
1422 LOG_DEBUG("stepping rtos hart");
1425 riscv_set_register(target
, GDB_REGNO_PC
, address
);
1427 int out
= riscv_step_rtos_hart(target
);
1428 if (out
!= ERROR_OK
) {
1429 LOG_ERROR("unable to step rtos hart");
1433 register_cache_invalidate(target
->reg_cache
);
1434 target
->state
= TARGET_RUNNING
;
1435 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1436 target
->state
= TARGET_HALTED
;
1437 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1438 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1442 /* Command Handlers */
1443 COMMAND_HANDLER(riscv_set_command_timeout_sec
)
1445 if (CMD_ARGC
!= 1) {
1446 LOG_ERROR("Command takes exactly 1 parameter");
1447 return ERROR_COMMAND_SYNTAX_ERROR
;
1449 int timeout
= atoi(CMD_ARGV
[0]);
1451 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV
[0]);
1455 riscv_command_timeout_sec
= timeout
;
1460 COMMAND_HANDLER(riscv_set_reset_timeout_sec
)
1462 if (CMD_ARGC
!= 1) {
1463 LOG_ERROR("Command takes exactly 1 parameter");
1464 return ERROR_COMMAND_SYNTAX_ERROR
;
1466 int timeout
= atoi(CMD_ARGV
[0]);
1468 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV
[0]);
1472 riscv_reset_timeout_sec
= timeout
;
1476 COMMAND_HANDLER(riscv_test_compliance
) {
1478 struct target
*target
= get_current_target(CMD_CTX
);
1483 LOG_ERROR("Command does not take any parameters.");
1484 return ERROR_COMMAND_SYNTAX_ERROR
;
1487 if (r
->test_compliance
) {
1488 return r
->test_compliance(target
);
1490 LOG_ERROR("This target does not support this command (may implement an older version of the spec).");
1495 COMMAND_HANDLER(riscv_set_prefer_sba
)
1497 if (CMD_ARGC
!= 1) {
1498 LOG_ERROR("Command takes exactly 1 parameter");
1499 return ERROR_COMMAND_SYNTAX_ERROR
;
1501 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_prefer_sba
);
1505 void parse_error(const char *string
, char c
, unsigned position
)
1507 char buf
[position
+2];
1508 for (unsigned i
= 0; i
< position
; i
++)
1510 buf
[position
] = '^';
1511 buf
[position
+ 1] = 0;
1513 LOG_ERROR("Parse error at character %c in:", c
);
1514 LOG_ERROR("%s", string
);
1515 LOG_ERROR("%s", buf
);
1518 int parse_ranges(range_t
**ranges
, const char **argv
)
1520 for (unsigned pass
= 0; pass
< 2; pass
++) {
1523 bool parse_low
= true;
1525 for (unsigned i
= 0; i
== 0 || argv
[0][i
-1]; i
++) {
1526 char c
= argv
[0][i
];
1528 /* Ignore whitespace. */
1536 } else if (c
== '-') {
1538 } else if (c
== ',' || c
== 0) {
1540 (*ranges
)[range
].low
= low
;
1541 (*ranges
)[range
].high
= low
;
1546 parse_error(argv
[0], c
, i
);
1547 return ERROR_COMMAND_SYNTAX_ERROR
;
1554 } else if (c
== ',' || c
== 0) {
1557 (*ranges
)[range
].low
= low
;
1558 (*ranges
)[range
].high
= high
;
1564 parse_error(argv
[0], c
, i
);
1565 return ERROR_COMMAND_SYNTAX_ERROR
;
1573 *ranges
= calloc(range
+ 2, sizeof(range_t
));
1575 (*ranges
)[range
].low
= 1;
1576 (*ranges
)[range
].high
= 0;
1583 COMMAND_HANDLER(riscv_set_expose_csrs
)
1585 if (CMD_ARGC
!= 1) {
1586 LOG_ERROR("Command takes exactly 1 parameter");
1587 return ERROR_COMMAND_SYNTAX_ERROR
;
1590 return parse_ranges(&expose_csr
, CMD_ARGV
);
1593 COMMAND_HANDLER(riscv_set_expose_custom
)
1595 if (CMD_ARGC
!= 1) {
1596 LOG_ERROR("Command takes exactly 1 parameter");
1597 return ERROR_COMMAND_SYNTAX_ERROR
;
1600 return parse_ranges(&expose_custom
, CMD_ARGV
);
1603 COMMAND_HANDLER(riscv_authdata_read
)
1605 if (CMD_ARGC
!= 0) {
1606 LOG_ERROR("Command takes no parameters");
1607 return ERROR_COMMAND_SYNTAX_ERROR
;
1610 struct target
*target
= get_current_target(CMD_CTX
);
1612 LOG_ERROR("target is NULL!");
1618 LOG_ERROR("riscv_info is NULL!");
1622 if (r
->authdata_read
) {
1624 if (r
->authdata_read(target
, &value
) != ERROR_OK
)
1626 command_print(CMD_CTX
, "0x%" PRIx32
, value
);
1629 LOG_ERROR("authdata_read is not implemented for this target.");
1634 COMMAND_HANDLER(riscv_authdata_write
)
1636 if (CMD_ARGC
!= 1) {
1637 LOG_ERROR("Command takes exactly 1 argument");
1638 return ERROR_COMMAND_SYNTAX_ERROR
;
1641 struct target
*target
= get_current_target(CMD_CTX
);
1645 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], value
);
1647 if (r
->authdata_write
) {
1648 return r
->authdata_write(target
, value
);
1650 LOG_ERROR("authdata_write is not implemented for this target.");
1655 COMMAND_HANDLER(riscv_dmi_read
)
1657 if (CMD_ARGC
!= 1) {
1658 LOG_ERROR("Command takes 1 parameter");
1659 return ERROR_COMMAND_SYNTAX_ERROR
;
1662 struct target
*target
= get_current_target(CMD_CTX
);
1664 LOG_ERROR("target is NULL!");
1670 LOG_ERROR("riscv_info is NULL!");
1675 uint32_t address
, value
;
1676 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
1677 if (r
->dmi_read(target
, &value
, address
) != ERROR_OK
)
1679 command_print(CMD_CTX
, "0x%" PRIx32
, value
);
1682 LOG_ERROR("dmi_read is not implemented for this target.");
1688 COMMAND_HANDLER(riscv_dmi_write
)
1690 if (CMD_ARGC
!= 2) {
1691 LOG_ERROR("Command takes exactly 2 arguments");
1692 return ERROR_COMMAND_SYNTAX_ERROR
;
1695 struct target
*target
= get_current_target(CMD_CTX
);
1698 uint32_t address
, value
;
1699 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
1700 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
1703 return r
->dmi_write(target
, address
, value
);
1705 LOG_ERROR("dmi_write is not implemented for this target.");
1710 COMMAND_HANDLER(riscv_test_sba_config_reg
)
1712 if (CMD_ARGC
!= 4) {
1713 LOG_ERROR("Command takes exactly 4 arguments");
1714 return ERROR_COMMAND_SYNTAX_ERROR
;
1717 struct target
*target
= get_current_target(CMD_CTX
);
1720 target_addr_t legal_address
;
1722 target_addr_t illegal_address
;
1723 bool run_sbbusyerror_test
;
1725 COMMAND_PARSE_NUMBER(target_addr
, CMD_ARGV
[0], legal_address
);
1726 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], num_words
);
1727 COMMAND_PARSE_NUMBER(target_addr
, CMD_ARGV
[2], illegal_address
);
1728 COMMAND_PARSE_ON_OFF(CMD_ARGV
[3], run_sbbusyerror_test
);
1730 if (r
->test_sba_config_reg
) {
1731 return r
->test_sba_config_reg(target
, legal_address
, num_words
,
1732 illegal_address
, run_sbbusyerror_test
);
1734 LOG_ERROR("test_sba_config_reg is not implemented for this target.");
1739 COMMAND_HANDLER(riscv_reset_delays
)
1744 LOG_ERROR("Command takes at most one argument");
1745 return ERROR_COMMAND_SYNTAX_ERROR
;
1749 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], wait
);
1751 struct target
*target
= get_current_target(CMD_CTX
);
1753 r
->reset_delays_wait
= wait
;
1757 COMMAND_HANDLER(riscv_set_ir
)
1759 if (CMD_ARGC
!= 2) {
1760 LOG_ERROR("Command takes exactly 2 arguments");
1761 return ERROR_COMMAND_SYNTAX_ERROR
;
1765 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
1767 if (!strcmp(CMD_ARGV
[0], "idcode")) {
1768 buf_set_u32(ir_idcode
, 0, 32, value
);
1770 } else if (!strcmp(CMD_ARGV
[0], "dtmcs")) {
1771 buf_set_u32(ir_dtmcontrol
, 0, 32, value
);
1773 } else if (!strcmp(CMD_ARGV
[0], "dmi")) {
1774 buf_set_u32(ir_dbus
, 0, 32, value
);
1781 static const struct command_registration riscv_exec_command_handlers
[] = {
1783 .name
= "test_compliance",
1784 .handler
= riscv_test_compliance
,
1785 .mode
= COMMAND_EXEC
,
1786 .usage
= "riscv test_compliance",
1787 .help
= "Runs a basic compliance test suite against the RISC-V Debug Spec."
1790 .name
= "set_command_timeout_sec",
1791 .handler
= riscv_set_command_timeout_sec
,
1792 .mode
= COMMAND_ANY
,
1793 .usage
= "riscv set_command_timeout_sec [sec]",
1794 .help
= "Set the wall-clock timeout (in seconds) for individual commands"
1797 .name
= "set_reset_timeout_sec",
1798 .handler
= riscv_set_reset_timeout_sec
,
1799 .mode
= COMMAND_ANY
,
1800 .usage
= "riscv set_reset_timeout_sec [sec]",
1801 .help
= "Set the wall-clock timeout (in seconds) after reset is deasserted"
1804 .name
= "set_prefer_sba",
1805 .handler
= riscv_set_prefer_sba
,
1806 .mode
= COMMAND_ANY
,
1807 .usage
= "riscv set_prefer_sba on|off",
1808 .help
= "When on, prefer to use System Bus Access to access memory. "
1809 "When off, prefer to use the Program Buffer to access memory."
1812 .name
= "expose_csrs",
1813 .handler
= riscv_set_expose_csrs
,
1814 .mode
= COMMAND_ANY
,
1815 .usage
= "riscv expose_csrs n0[-m0][,n1[-m1]]...",
1816 .help
= "Configure a list of inclusive ranges for CSRs to expose in "
1817 "addition to the standard ones. This must be executed before "
1821 .name
= "expose_custom",
1822 .handler
= riscv_set_expose_custom
,
1823 .mode
= COMMAND_ANY
,
1824 .usage
= "riscv expose_custom n0[-m0][,n1[-m1]]...",
1825 .help
= "Configure a list of inclusive ranges for custom registers to "
1826 "expose. custom0 is accessed as abstract register number 0xc000, "
1827 "etc. This must be executed before `init`."
1830 .name
= "authdata_read",
1831 .handler
= riscv_authdata_read
,
1832 .mode
= COMMAND_ANY
,
1833 .usage
= "riscv authdata_read",
1834 .help
= "Return the 32-bit value read from authdata."
1837 .name
= "authdata_write",
1838 .handler
= riscv_authdata_write
,
1839 .mode
= COMMAND_ANY
,
1840 .usage
= "riscv authdata_write value",
1841 .help
= "Write the 32-bit value to authdata."
1845 .handler
= riscv_dmi_read
,
1846 .mode
= COMMAND_ANY
,
1847 .usage
= "riscv dmi_read address",
1848 .help
= "Perform a 32-bit DMI read at address, returning the value."
1851 .name
= "dmi_write",
1852 .handler
= riscv_dmi_write
,
1853 .mode
= COMMAND_ANY
,
1854 .usage
= "riscv dmi_write address value",
1855 .help
= "Perform a 32-bit DMI write of value at address."
1858 .name
= "test_sba_config_reg",
1859 .handler
= riscv_test_sba_config_reg
,
1860 .mode
= COMMAND_ANY
,
1861 .usage
= "riscv test_sba_config_reg legal_address num_words"
1862 "illegal_address run_sbbusyerror_test[on/off]",
1863 .help
= "Perform a series of tests on the SBCS register."
1864 "Inputs are a legal, 128-byte aligned address and a number of words to"
1865 "read/write starting at that address (i.e., address range [legal address,"
1866 "legal_address+word_size*num_words) must be legally readable/writable)"
1867 ", an illegal, 128-byte aligned address for error flag/handling cases,"
1868 "and whether sbbusyerror test should be run."
1871 .name
= "reset_delays",
1872 .handler
= riscv_reset_delays
,
1873 .mode
= COMMAND_ANY
,
1874 .usage
= "reset_delays [wait]",
1875 .help
= "OpenOCD learns how many Run-Test/Idle cycles are required "
1876 "between scans to avoid encountering the target being busy. This "
1877 "command resets those learned values after `wait` scans. It's only "
1878 "useful for testing OpenOCD itself."
1882 .handler
= riscv_set_ir
,
1883 .mode
= COMMAND_ANY
,
1884 .usage
= "riscv set_ir_idcode [idcode|dtmcs|dmi] value",
1885 .help
= "Set IR value for specified JTAG register."
1887 COMMAND_REGISTRATION_DONE
1890 extern __COMMAND_HANDLER(handle_common_semihosting_command
);
1891 extern __COMMAND_HANDLER(handle_common_semihosting_fileio_command
);
1892 extern __COMMAND_HANDLER(handle_common_semihosting_resumable_exit_command
);
1893 extern __COMMAND_HANDLER(handle_common_semihosting_cmdline
);
1896 * To be noted that RISC-V targets use the same semihosting commands as
1899 * The main reason is compatibility with existing tools. For example the
1900 * Eclipse OpenOCD/SEGGER J-Link/QEMU plug-ins have several widgets to
1901 * configure semihosting, which generate commands like `arm semihosting
1903 * A secondary reason is the fact that the protocol used is exactly the
1904 * one specified by ARM. If RISC-V will ever define its own semihosting
1905 * protocol, then a command like `riscv semihosting enable` will make
1906 * sense, but for now all semihosting commands are prefixed with `arm`.
1908 static const struct command_registration arm_exec_command_handlers
[] = {
1910 .name
= "semihosting",
1911 .handler
= handle_common_semihosting_command
,
1912 .mode
= COMMAND_EXEC
,
1913 .usage
= "['enable'|'disable']",
1914 .help
= "activate support for semihosting operations",
1917 .name
= "semihosting_cmdline",
1918 .handler
= handle_common_semihosting_cmdline
,
1919 .mode
= COMMAND_EXEC
,
1920 .usage
= "arguments",
1921 .help
= "command line arguments to be passed to program",
1924 .name
= "semihosting_fileio",
1925 .handler
= handle_common_semihosting_fileio_command
,
1926 .mode
= COMMAND_EXEC
,
1927 .usage
= "['enable'|'disable']",
1928 .help
= "activate support for semihosting fileio operations",
1931 .name
= "semihosting_resexit",
1932 .handler
= handle_common_semihosting_resumable_exit_command
,
1933 .mode
= COMMAND_EXEC
,
1934 .usage
= "['enable'|'disable']",
1935 .help
= "activate support for semihosting resumable exit",
1937 COMMAND_REGISTRATION_DONE
1940 const struct command_registration riscv_command_handlers
[] = {
1943 .mode
= COMMAND_ANY
,
1944 .help
= "RISC-V Command Group",
1946 .chain
= riscv_exec_command_handlers
1950 .mode
= COMMAND_ANY
,
1951 .help
= "ARM Command Group",
1953 .chain
= arm_exec_command_handlers
1955 COMMAND_REGISTRATION_DONE
1958 unsigned riscv_address_bits(struct target
*target
)
1960 return riscv_xlen(target
);
1963 struct target_type riscv_target
= {
1966 .init_target
= riscv_init_target
,
1967 .deinit_target
= riscv_deinit_target
,
1968 .examine
= riscv_examine
,
1970 /* poll current target status */
1971 .poll
= old_or_new_riscv_poll
,
1973 .halt
= old_or_new_riscv_halt
,
1974 .resume
= old_or_new_riscv_resume
,
1975 .step
= old_or_new_riscv_step
,
1977 .assert_reset
= riscv_assert_reset
,
1978 .deassert_reset
= riscv_deassert_reset
,
1980 .read_memory
= riscv_read_memory
,
1981 .write_memory
= riscv_write_memory
,
1983 .checksum_memory
= riscv_checksum_memory
,
1985 .get_gdb_reg_list
= riscv_get_gdb_reg_list
,
1987 .add_breakpoint
= riscv_add_breakpoint
,
1988 .remove_breakpoint
= riscv_remove_breakpoint
,
1990 .add_watchpoint
= riscv_add_watchpoint
,
1991 .remove_watchpoint
= riscv_remove_watchpoint
,
1992 .hit_watchpoint
= riscv_hit_watchpoint
,
1994 .arch_state
= riscv_arch_state
,
1996 .run_algorithm
= riscv_run_algorithm
,
1998 .commands
= riscv_command_handlers
,
2000 .address_bits
= riscv_address_bits
2003 /*** RISC-V Interface ***/
2005 void riscv_info_init(struct target
*target
, riscv_info_t
*r
)
2007 memset(r
, 0, sizeof(*r
));
2009 r
->registers_initialized
= false;
2010 r
->current_hartid
= target
->coreid
;
2012 memset(r
->trigger_unique_id
, 0xff, sizeof(r
->trigger_unique_id
));
2014 for (size_t h
= 0; h
< RISCV_MAX_HARTS
; ++h
) {
2017 for (size_t e
= 0; e
< RISCV_MAX_REGISTERS
; ++e
)
2018 r
->valid_saved_registers
[h
][e
] = false;
2022 int riscv_halt_all_harts(struct target
*target
)
2024 for (int i
= 0; i
< riscv_count_harts(target
); ++i
) {
2025 if (!riscv_hart_enabled(target
, i
))
2028 riscv_halt_one_hart(target
, i
);
2031 riscv_invalidate_register_cache(target
);
2036 int riscv_halt_one_hart(struct target
*target
, int hartid
)
2039 LOG_DEBUG("halting hart %d", hartid
);
2040 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
2042 if (riscv_is_halted(target
)) {
2043 LOG_DEBUG(" hart %d requested halt, but was already halted", hartid
);
2047 int result
= r
->halt_current_hart(target
);
2048 register_cache_invalidate(target
->reg_cache
);
2052 int riscv_resume_all_harts(struct target
*target
)
2054 for (int i
= 0; i
< riscv_count_harts(target
); ++i
) {
2055 if (!riscv_hart_enabled(target
, i
))
2058 riscv_resume_one_hart(target
, i
);
2061 riscv_invalidate_register_cache(target
);
2065 int riscv_resume_one_hart(struct target
*target
, int hartid
)
2068 LOG_DEBUG("resuming hart %d", hartid
);
2069 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
2071 if (!riscv_is_halted(target
)) {
2072 LOG_DEBUG(" hart %d requested resume, but was already resumed", hartid
);
2076 r
->on_resume(target
);
2077 return r
->resume_current_hart(target
);
2080 int riscv_step_rtos_hart(struct target
*target
)
2083 int hartid
= r
->current_hartid
;
2084 if (riscv_rtos_enabled(target
)) {
2085 hartid
= r
->rtos_hartid
;
2087 LOG_DEBUG("GDB has asked me to step \"any\" thread, so I'm stepping hart 0.");
2091 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
2093 LOG_DEBUG("stepping hart %d", hartid
);
2095 if (!riscv_is_halted(target
)) {
2096 LOG_ERROR("Hart isn't halted before single step!");
2099 riscv_invalidate_register_cache(target
);
2101 if (r
->step_current_hart(target
) != ERROR_OK
)
2103 riscv_invalidate_register_cache(target
);
2105 if (!riscv_is_halted(target
)) {
2106 LOG_ERROR("Hart was not halted after single step!");
2112 bool riscv_supports_extension(struct target
*target
, int hartid
, char letter
)
2116 if (letter
>= 'a' && letter
<= 'z')
2118 else if (letter
>= 'A' && letter
<= 'Z')
2122 return r
->misa
[hartid
] & (1 << num
);
2125 int riscv_xlen(const struct target
*target
)
2127 return riscv_xlen_of_hart(target
, riscv_current_hartid(target
));
2130 int riscv_xlen_of_hart(const struct target
*target
, int hartid
)
2133 assert(r
->xlen
[hartid
] != -1);
2134 return r
->xlen
[hartid
];
2137 extern struct rtos_type riscv_rtos
;
2138 bool riscv_rtos_enabled(const struct target
*target
)
2143 int riscv_set_current_hartid(struct target
*target
, int hartid
)
2146 if (!r
->select_current_hart
)
2149 int previous_hartid
= riscv_current_hartid(target
);
2150 r
->current_hartid
= hartid
;
2151 assert(riscv_hart_enabled(target
, hartid
));
2152 LOG_DEBUG("setting hartid to %d, was %d", hartid
, previous_hartid
);
2153 if (r
->select_current_hart(target
) != ERROR_OK
)
2156 /* This might get called during init, in which case we shouldn't be
2157 * setting up the register cache. */
2158 if (target_was_examined(target
) && riscv_rtos_enabled(target
))
2159 riscv_invalidate_register_cache(target
);
2164 void riscv_invalidate_register_cache(struct target
*target
)
2168 LOG_DEBUG("[%d]", target
->coreid
);
2169 register_cache_invalidate(target
->reg_cache
);
2170 for (size_t i
= 0; i
< target
->reg_cache
->num_regs
; ++i
) {
2171 struct reg
*reg
= &target
->reg_cache
->reg_list
[i
];
2175 r
->registers_initialized
= true;
2178 int riscv_current_hartid(const struct target
*target
)
2181 return r
->current_hartid
;
2184 void riscv_set_all_rtos_harts(struct target
*target
)
2187 r
->rtos_hartid
= -1;
2190 void riscv_set_rtos_hartid(struct target
*target
, int hartid
)
2192 LOG_DEBUG("setting RTOS hartid %d", hartid
);
2194 r
->rtos_hartid
= hartid
;
2197 int riscv_count_harts(struct target
*target
)
2204 return r
->hart_count
;
2207 bool riscv_has_register(struct target
*target
, int hartid
, int regid
)
2213 * This function is called when the debug user wants to change the value of a
2214 * register. The new value may be cached, and may not be written until the hart
2216 int riscv_set_register(struct target
*target
, enum gdb_regno r
, riscv_reg_t v
)
2218 return riscv_set_register_on_hart(target
, riscv_current_hartid(target
), r
, v
);
2221 int riscv_set_register_on_hart(struct target
*target
, int hartid
,
2222 enum gdb_regno regid
, uint64_t value
)
2225 LOG_DEBUG("{%d} %s <- %" PRIx64
, hartid
, gdb_regno_name(regid
), value
);
2226 assert(r
->set_register
);
2227 return r
->set_register(target
, hartid
, regid
, value
);
2230 int riscv_get_register(struct target
*target
, riscv_reg_t
*value
,
2233 return riscv_get_register_on_hart(target
, value
,
2234 riscv_current_hartid(target
), r
);
2237 int riscv_get_register_on_hart(struct target
*target
, riscv_reg_t
*value
,
2238 int hartid
, enum gdb_regno regid
)
2242 struct reg
*reg
= &target
->reg_cache
->reg_list
[regid
];
2244 if (reg
&& reg
->valid
&& hartid
== riscv_current_hartid(target
)) {
2245 *value
= buf_get_u64(reg
->value
, 0, reg
->size
);
2249 int result
= r
->get_register(target
, value
, hartid
, regid
);
2251 LOG_DEBUG("{%d} %s: %" PRIx64
, hartid
, gdb_regno_name(regid
), *value
);
2255 bool riscv_is_halted(struct target
*target
)
2258 assert(r
->is_halted
);
2259 return r
->is_halted(target
);
2262 enum riscv_halt_reason
riscv_halt_reason(struct target
*target
, int hartid
)
2265 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
2266 return RISCV_HALT_ERROR
;
2267 if (!riscv_is_halted(target
)) {
2268 LOG_ERROR("Hart is not halted!");
2269 return RISCV_HALT_UNKNOWN
;
2271 return r
->halt_reason(target
);
2274 size_t riscv_debug_buffer_size(struct target
*target
)
2277 return r
->debug_buffer_size
[riscv_current_hartid(target
)];
2280 int riscv_write_debug_buffer(struct target
*target
, int index
, riscv_insn_t insn
)
2283 r
->write_debug_buffer(target
, index
, insn
);
2287 riscv_insn_t
riscv_read_debug_buffer(struct target
*target
, int index
)
2290 return r
->read_debug_buffer(target
, index
);
2293 int riscv_execute_debug_buffer(struct target
*target
)
2296 return r
->execute_debug_buffer(target
);
2299 void riscv_fill_dmi_write_u64(struct target
*target
, char *buf
, int a
, uint64_t d
)
2302 r
->fill_dmi_write_u64(target
, buf
, a
, d
);
2305 void riscv_fill_dmi_read_u64(struct target
*target
, char *buf
, int a
)
2308 r
->fill_dmi_read_u64(target
, buf
, a
);
2311 void riscv_fill_dmi_nop_u64(struct target
*target
, char *buf
)
2314 r
->fill_dmi_nop_u64(target
, buf
);
2317 int riscv_dmi_write_u64_bits(struct target
*target
)
2320 return r
->dmi_write_u64_bits(target
);
2323 bool riscv_hart_enabled(struct target
*target
, int hartid
)
2325 /* FIXME: Add a hart mask to the RTOS. */
2326 if (riscv_rtos_enabled(target
))
2327 return hartid
< riscv_count_harts(target
);
2329 return hartid
== target
->coreid
;
2333 * Count triggers, and initialize trigger_count for each hart.
2334 * trigger_count is initialized even if this function fails to discover
2336 * Disable any hardware triggers that have dmode set. We can't have set them
2337 * ourselves. Maybe they're left over from some killed debug session.
2339 int riscv_enumerate_triggers(struct target
*target
)
2343 if (r
->triggers_enumerated
)
2346 r
->triggers_enumerated
= true; /* At the very least we tried. */
2348 for (int hartid
= 0; hartid
< riscv_count_harts(target
); ++hartid
) {
2349 if (!riscv_hart_enabled(target
, hartid
))
2352 riscv_reg_t tselect
;
2353 int result
= riscv_get_register_on_hart(target
, &tselect
, hartid
,
2355 if (result
!= ERROR_OK
)
2358 for (unsigned t
= 0; t
< RISCV_MAX_TRIGGERS
; ++t
) {
2359 r
->trigger_count
[hartid
] = t
;
2361 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, t
);
2362 uint64_t tselect_rb
;
2363 result
= riscv_get_register_on_hart(target
, &tselect_rb
, hartid
,
2365 if (result
!= ERROR_OK
)
2367 /* Mask off the top bit, which is used as tdrmode in old
2368 * implementations. */
2369 tselect_rb
&= ~(1ULL << (riscv_xlen(target
)-1));
2370 if (tselect_rb
!= t
)
2373 result
= riscv_get_register_on_hart(target
, &tdata1
, hartid
,
2375 if (result
!= ERROR_OK
)
2378 int type
= get_field(tdata1
, MCONTROL_TYPE(riscv_xlen(target
)));
2381 /* On these older cores we don't support software using
2383 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
2386 if (tdata1
& MCONTROL_DMODE(riscv_xlen(target
)))
2387 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
2392 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, tselect
);
2394 LOG_INFO("[%d] Found %d triggers", hartid
, r
->trigger_count
[hartid
]);
2400 const char *gdb_regno_name(enum gdb_regno regno
)
2402 static char buf
[32];
2405 case GDB_REGNO_ZERO
:
2413 case GDB_REGNO_FPR0
:
2415 case GDB_REGNO_FPR31
:
2417 case GDB_REGNO_CSR0
:
2419 case GDB_REGNO_TSELECT
:
2421 case GDB_REGNO_TDATA1
:
2423 case GDB_REGNO_TDATA2
:
2425 case GDB_REGNO_MISA
:
2429 case GDB_REGNO_DCSR
:
2431 case GDB_REGNO_DSCRATCH
:
2433 case GDB_REGNO_MSTATUS
:
2435 case GDB_REGNO_PRIV
:
2438 if (regno
<= GDB_REGNO_XPR31
)
2439 sprintf(buf
, "x%d", regno
- GDB_REGNO_ZERO
);
2440 else if (regno
>= GDB_REGNO_CSR0
&& regno
<= GDB_REGNO_CSR4095
)
2441 sprintf(buf
, "csr%d", regno
- GDB_REGNO_CSR0
);
2442 else if (regno
>= GDB_REGNO_FPR0
&& regno
<= GDB_REGNO_FPR31
)
2443 sprintf(buf
, "f%d", regno
- GDB_REGNO_FPR0
);
2445 sprintf(buf
, "gdb_regno_%d", regno
);
2450 static int register_get(struct reg
*reg
)
2452 riscv_reg_info_t
*reg_info
= reg
->arch_info
;
2453 struct target
*target
= reg_info
->target
;
2455 int result
= riscv_get_register(target
, &value
, reg
->number
);
2456 if (result
!= ERROR_OK
)
2458 buf_set_u64(reg
->value
, 0, reg
->size
, value
);
2459 /* CSRs (and possibly other extension) registers may change value at any
2461 if (reg
->number
<= GDB_REGNO_XPR31
||
2462 (reg
->number
>= GDB_REGNO_FPR0
&& reg
->number
<= GDB_REGNO_FPR31
) ||
2463 reg
->number
== GDB_REGNO_PC
)
2465 LOG_DEBUG("[%d]{%d} read 0x%" PRIx64
" from %s (valid=%d)",
2466 target
->coreid
, riscv_current_hartid(target
), value
, reg
->name
,
2471 static int register_set(struct reg
*reg
, uint8_t *buf
)
2473 riscv_reg_info_t
*reg_info
= reg
->arch_info
;
2474 struct target
*target
= reg_info
->target
;
2476 uint64_t value
= buf_get_u64(buf
, 0, reg
->size
);
2478 LOG_DEBUG("[%d]{%d} write 0x%" PRIx64
" to %s (valid=%d)",
2479 target
->coreid
, riscv_current_hartid(target
), value
, reg
->name
,
2481 struct reg
*r
= &target
->reg_cache
->reg_list
[reg
->number
];
2482 /* CSRs (and possibly other extension) registers may change value at any
2484 if (reg
->number
<= GDB_REGNO_XPR31
||
2485 (reg
->number
>= GDB_REGNO_FPR0
&& reg
->number
<= GDB_REGNO_FPR31
) ||
2486 reg
->number
== GDB_REGNO_PC
)
2488 memcpy(r
->value
, buf
, (r
->size
+ 7) / 8);
2490 riscv_set_register(target
, reg
->number
, value
);
2494 static struct reg_arch_type riscv_reg_arch_type
= {
2495 .get
= register_get
,
2504 static int cmp_csr_info(const void *p1
, const void *p2
)
2506 return (int) (((struct csr_info
*)p1
)->number
) - (int) (((struct csr_info
*)p2
)->number
);
2509 int riscv_init_registers(struct target
*target
)
2513 riscv_free_registers(target
);
2515 target
->reg_cache
= calloc(1, sizeof(*target
->reg_cache
));
2516 target
->reg_cache
->name
= "RISC-V Registers";
2517 target
->reg_cache
->num_regs
= GDB_REGNO_COUNT
;
2519 if (expose_custom
) {
2520 for (unsigned i
= 0; expose_custom
[i
].low
<= expose_custom
[i
].high
; i
++) {
2521 for (unsigned number
= expose_custom
[i
].low
;
2522 number
<= expose_custom
[i
].high
;
2524 target
->reg_cache
->num_regs
++;
2528 LOG_DEBUG("create register cache for %d registers",
2529 target
->reg_cache
->num_regs
);
2531 target
->reg_cache
->reg_list
=
2532 calloc(target
->reg_cache
->num_regs
, sizeof(struct reg
));
2534 const unsigned int max_reg_name_len
= 12;
2535 if (info
->reg_names
)
2536 free(info
->reg_names
);
2538 calloc(target
->reg_cache
->num_regs
, max_reg_name_len
);
2539 char *reg_name
= info
->reg_names
;
2541 static struct reg_feature feature_cpu
= {
2542 .name
= "org.gnu.gdb.riscv.cpu"
2544 static struct reg_feature feature_fpu
= {
2545 .name
= "org.gnu.gdb.riscv.fpu"
2547 static struct reg_feature feature_csr
= {
2548 .name
= "org.gnu.gdb.riscv.csr"
2550 static struct reg_feature feature_virtual
= {
2551 .name
= "org.gnu.gdb.riscv.virtual"
2553 static struct reg_feature feature_custom
= {
2554 .name
= "org.gnu.gdb.riscv.custom"
2557 static struct reg_data_type type_ieee_single
= {
2558 .type
= REG_TYPE_IEEE_SINGLE
,
2561 static struct reg_data_type type_ieee_double
= {
2562 .type
= REG_TYPE_IEEE_DOUBLE
,
2565 struct csr_info csr_info
[] = {
2566 #define DECLARE_CSR(name, number) { number, #name },
2567 #include "encoding.h"
2570 /* encoding.h does not contain the registers in sorted order. */
2571 qsort(csr_info
, DIM(csr_info
), sizeof(*csr_info
), cmp_csr_info
);
2572 unsigned csr_info_index
= 0;
2574 unsigned custom_range_index
= 0;
2575 int custom_within_range
= 0;
2577 riscv_reg_info_t
*shared_reg_info
= calloc(1, sizeof(riscv_reg_info_t
));
2578 shared_reg_info
->target
= target
;
2580 /* When gdb requests register N, gdb_get_register_packet() assumes that this
2581 * is register at index N in reg_list. So if there are certain registers
2582 * that don't exist, we need to leave holes in the list (or renumber, but
2583 * it would be nice not to have yet another set of numbers to translate
2585 for (uint32_t number
= 0; number
< target
->reg_cache
->num_regs
; number
++) {
2586 struct reg
*r
= &target
->reg_cache
->reg_list
[number
];
2590 r
->type
= &riscv_reg_arch_type
;
2591 r
->arch_info
= shared_reg_info
;
2593 r
->size
= riscv_xlen(target
);
2594 /* r->size is set in riscv_invalidate_register_cache, maybe because the
2595 * target is in theory allowed to change XLEN on us. But I expect a lot
2596 * of other things to break in that case as well. */
2597 if (number
<= GDB_REGNO_XPR31
) {
2598 r
->caller_save
= true;
2600 case GDB_REGNO_ZERO
:
2697 r
->group
= "general";
2698 r
->feature
= &feature_cpu
;
2699 } else if (number
== GDB_REGNO_PC
) {
2700 r
->caller_save
= true;
2701 sprintf(reg_name
, "pc");
2702 r
->group
= "general";
2703 r
->feature
= &feature_cpu
;
2704 } else if (number
>= GDB_REGNO_FPR0
&& number
<= GDB_REGNO_FPR31
) {
2705 r
->caller_save
= true;
2706 if (riscv_supports_extension(target
, riscv_current_hartid(target
),
2708 r
->reg_data_type
= &type_ieee_double
;
2710 } else if (riscv_supports_extension(target
,
2711 riscv_current_hartid(target
), 'F')) {
2712 r
->reg_data_type
= &type_ieee_single
;
2796 case GDB_REGNO_FS10
:
2799 case GDB_REGNO_FS11
:
2808 case GDB_REGNO_FT10
:
2811 case GDB_REGNO_FT11
:
2816 r
->feature
= &feature_fpu
;
2817 } else if (number
>= GDB_REGNO_CSR0
&& number
<= GDB_REGNO_CSR4095
) {
2819 r
->feature
= &feature_csr
;
2820 unsigned csr_number
= number
- GDB_REGNO_CSR0
;
2822 while (csr_info
[csr_info_index
].number
< csr_number
&&
2823 csr_info_index
< DIM(csr_info
) - 1) {
2826 if (csr_info
[csr_info_index
].number
== csr_number
) {
2827 r
->name
= csr_info
[csr_info_index
].name
;
2829 sprintf(reg_name
, "csr%d", csr_number
);
2830 /* Assume unnamed registers don't exist, unless we have some
2831 * configuration that tells us otherwise. That's important
2832 * because eg. Eclipse crashes if a target has too many
2833 * registers, and apparently has no way of only showing a
2834 * subset of registers in any case. */
2838 switch (csr_number
) {
2842 r
->exist
= riscv_supports_extension(target
,
2843 riscv_current_hartid(target
), 'F');
2845 r
->feature
= &feature_fpu
;
2851 case CSR_SCOUNTEREN
:
2857 r
->exist
= riscv_supports_extension(target
,
2858 riscv_current_hartid(target
), 'S');
2862 /* "In systems with only M-mode, or with both M-mode and
2863 * U-mode but without U-mode trap support, the medeleg and
2864 * mideleg registers should not exist." */
2865 r
->exist
= riscv_supports_extension(target
, riscv_current_hartid(target
), 'S') ||
2866 riscv_supports_extension(target
, riscv_current_hartid(target
), 'N');
2872 case CSR_HPMCOUNTER3H
:
2873 case CSR_HPMCOUNTER4H
:
2874 case CSR_HPMCOUNTER5H
:
2875 case CSR_HPMCOUNTER6H
:
2876 case CSR_HPMCOUNTER7H
:
2877 case CSR_HPMCOUNTER8H
:
2878 case CSR_HPMCOUNTER9H
:
2879 case CSR_HPMCOUNTER10H
:
2880 case CSR_HPMCOUNTER11H
:
2881 case CSR_HPMCOUNTER12H
:
2882 case CSR_HPMCOUNTER13H
:
2883 case CSR_HPMCOUNTER14H
:
2884 case CSR_HPMCOUNTER15H
:
2885 case CSR_HPMCOUNTER16H
:
2886 case CSR_HPMCOUNTER17H
:
2887 case CSR_HPMCOUNTER18H
:
2888 case CSR_HPMCOUNTER19H
:
2889 case CSR_HPMCOUNTER20H
:
2890 case CSR_HPMCOUNTER21H
:
2891 case CSR_HPMCOUNTER22H
:
2892 case CSR_HPMCOUNTER23H
:
2893 case CSR_HPMCOUNTER24H
:
2894 case CSR_HPMCOUNTER25H
:
2895 case CSR_HPMCOUNTER26H
:
2896 case CSR_HPMCOUNTER27H
:
2897 case CSR_HPMCOUNTER28H
:
2898 case CSR_HPMCOUNTER29H
:
2899 case CSR_HPMCOUNTER30H
:
2900 case CSR_HPMCOUNTER31H
:
2903 case CSR_MHPMCOUNTER3H
:
2904 case CSR_MHPMCOUNTER4H
:
2905 case CSR_MHPMCOUNTER5H
:
2906 case CSR_MHPMCOUNTER6H
:
2907 case CSR_MHPMCOUNTER7H
:
2908 case CSR_MHPMCOUNTER8H
:
2909 case CSR_MHPMCOUNTER9H
:
2910 case CSR_MHPMCOUNTER10H
:
2911 case CSR_MHPMCOUNTER11H
:
2912 case CSR_MHPMCOUNTER12H
:
2913 case CSR_MHPMCOUNTER13H
:
2914 case CSR_MHPMCOUNTER14H
:
2915 case CSR_MHPMCOUNTER15H
:
2916 case CSR_MHPMCOUNTER16H
:
2917 case CSR_MHPMCOUNTER17H
:
2918 case CSR_MHPMCOUNTER18H
:
2919 case CSR_MHPMCOUNTER19H
:
2920 case CSR_MHPMCOUNTER20H
:
2921 case CSR_MHPMCOUNTER21H
:
2922 case CSR_MHPMCOUNTER22H
:
2923 case CSR_MHPMCOUNTER23H
:
2924 case CSR_MHPMCOUNTER24H
:
2925 case CSR_MHPMCOUNTER25H
:
2926 case CSR_MHPMCOUNTER26H
:
2927 case CSR_MHPMCOUNTER27H
:
2928 case CSR_MHPMCOUNTER28H
:
2929 case CSR_MHPMCOUNTER29H
:
2930 case CSR_MHPMCOUNTER30H
:
2931 case CSR_MHPMCOUNTER31H
:
2932 r
->exist
= riscv_xlen(target
) == 32;
2936 if (!r
->exist
&& expose_csr
) {
2937 for (unsigned i
= 0; expose_csr
[i
].low
<= expose_csr
[i
].high
; i
++) {
2938 if (csr_number
>= expose_csr
[i
].low
&& csr_number
<= expose_csr
[i
].high
) {
2939 LOG_INFO("Exposing additional CSR %d", csr_number
);
2946 } else if (number
== GDB_REGNO_PRIV
) {
2947 sprintf(reg_name
, "priv");
2948 r
->group
= "general";
2949 r
->feature
= &feature_virtual
;
2953 /* Custom registers. */
2954 assert(expose_custom
);
2956 range_t
*range
= &expose_custom
[custom_range_index
];
2957 assert(range
->low
<= range
->high
);
2958 unsigned custom_number
= range
->low
+ custom_within_range
;
2960 r
->group
= "custom";
2961 r
->feature
= &feature_custom
;
2962 r
->arch_info
= calloc(1, sizeof(riscv_reg_info_t
));
2963 assert(r
->arch_info
);
2964 ((riscv_reg_info_t
*) r
->arch_info
)->target
= target
;
2965 ((riscv_reg_info_t
*) r
->arch_info
)->custom_number
= custom_number
;
2966 sprintf(reg_name
, "custom%d", custom_number
);
2968 custom_within_range
++;
2969 if (custom_within_range
> range
->high
- range
->low
) {
2970 custom_within_range
= 0;
2971 custom_range_index
++;
2977 reg_name
+= strlen(reg_name
) + 1;
2978 assert(reg_name
< info
->reg_names
+ target
->reg_cache
->num_regs
*
2980 r
->value
= &info
->reg_cache_values
[number
];