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33de63e2d98ab3958ac57086dac241cec6985ef2
[openocd.git] / src / target / openrisc / or1k.c
1 /***************************************************************************
2 * Copyright (C) 2011 by Julius Baxter *
3 * julius@opencores.org *
4 * *
5 * Copyright (C) 2013 by Marek Czerski *
6 * ma.czerski@gmail.com *
7 * *
8 * Copyright (C) 2013 by Franck Jullien *
9 * elec4fun@gmail.com *
10 * *
11 * *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
16 * *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
21 ***************************************************************************/
22
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include <jtag/jtag.h>
28 #include <target/register.h>
29 #include <target/target.h>
30 #include <target/breakpoints.h>
31 #include <target/target_type.h>
32 #include <helper/time_support.h>
33 #include <helper/fileio.h>
34 #include "or1k_tap.h"
35 #include "or1k.h"
36 #include "or1k_du.h"
37
38 LIST_HEAD(tap_list);
39 LIST_HEAD(du_list);
40
41 static int or1k_remove_breakpoint(struct target *target,
42 struct breakpoint *breakpoint);
43
44 static int or1k_read_core_reg(struct target *target, int num);
45 static int or1k_write_core_reg(struct target *target, int num);
46
47 static struct or1k_core_reg *or1k_core_reg_list_arch_info;
48
49 static const struct or1k_core_reg_init or1k_init_reg_list[] = {
50 {"r0" , GROUP0 + 1024, "org.gnu.gdb.or1k.group0", NULL},
51 {"r1" , GROUP0 + 1025, "org.gnu.gdb.or1k.group0", NULL},
52 {"r2" , GROUP0 + 1026, "org.gnu.gdb.or1k.group0", NULL},
53 {"r3" , GROUP0 + 1027, "org.gnu.gdb.or1k.group0", NULL},
54 {"r4" , GROUP0 + 1028, "org.gnu.gdb.or1k.group0", NULL},
55 {"r5" , GROUP0 + 1029, "org.gnu.gdb.or1k.group0", NULL},
56 {"r6" , GROUP0 + 1030, "org.gnu.gdb.or1k.group0", NULL},
57 {"r7" , GROUP0 + 1031, "org.gnu.gdb.or1k.group0", NULL},
58 {"r8" , GROUP0 + 1032, "org.gnu.gdb.or1k.group0", NULL},
59 {"r9" , GROUP0 + 1033, "org.gnu.gdb.or1k.group0", NULL},
60 {"r10" , GROUP0 + 1034, "org.gnu.gdb.or1k.group0", NULL},
61 {"r11" , GROUP0 + 1035, "org.gnu.gdb.or1k.group0", NULL},
62 {"r12" , GROUP0 + 1036, "org.gnu.gdb.or1k.group0", NULL},
63 {"r13" , GROUP0 + 1037, "org.gnu.gdb.or1k.group0", NULL},
64 {"r14" , GROUP0 + 1038, "org.gnu.gdb.or1k.group0", NULL},
65 {"r15" , GROUP0 + 1039, "org.gnu.gdb.or1k.group0", NULL},
66 {"r16" , GROUP0 + 1040, "org.gnu.gdb.or1k.group0", NULL},
67 {"r17" , GROUP0 + 1041, "org.gnu.gdb.or1k.group0", NULL},
68 {"r18" , GROUP0 + 1042, "org.gnu.gdb.or1k.group0", NULL},
69 {"r19" , GROUP0 + 1043, "org.gnu.gdb.or1k.group0", NULL},
70 {"r20" , GROUP0 + 1044, "org.gnu.gdb.or1k.group0", NULL},
71 {"r21" , GROUP0 + 1045, "org.gnu.gdb.or1k.group0", NULL},
72 {"r22" , GROUP0 + 1046, "org.gnu.gdb.or1k.group0", NULL},
73 {"r23" , GROUP0 + 1047, "org.gnu.gdb.or1k.group0", NULL},
74 {"r24" , GROUP0 + 1048, "org.gnu.gdb.or1k.group0", NULL},
75 {"r25" , GROUP0 + 1049, "org.gnu.gdb.or1k.group0", NULL},
76 {"r26" , GROUP0 + 1050, "org.gnu.gdb.or1k.group0", NULL},
77 {"r27" , GROUP0 + 1051, "org.gnu.gdb.or1k.group0", NULL},
78 {"r28" , GROUP0 + 1052, "org.gnu.gdb.or1k.group0", NULL},
79 {"r29" , GROUP0 + 1053, "org.gnu.gdb.or1k.group0", NULL},
80 {"r30" , GROUP0 + 1054, "org.gnu.gdb.or1k.group0", NULL},
81 {"r31" , GROUP0 + 1055, "org.gnu.gdb.or1k.group0", NULL},
82 {"ppc" , GROUP0 + 18, "org.gnu.gdb.or1k.group0", NULL},
83 {"npc" , GROUP0 + 16, "org.gnu.gdb.or1k.group0", NULL},
84 {"sr" , GROUP0 + 17, "org.gnu.gdb.or1k.group0", NULL},
85 {"vr" , GROUP0 + 0, "org.gnu.gdb.or1k.group0", "system"},
86 {"upr" , GROUP0 + 1, "org.gnu.gdb.or1k.group0", "system"},
87 {"cpucfgr" , GROUP0 + 2, "org.gnu.gdb.or1k.group0", "system"},
88 {"dmmucfgr" , GROUP0 + 3, "org.gnu.gdb.or1k.group0", "system"},
89 {"immucfgr" , GROUP0 + 4, "org.gnu.gdb.or1k.group0", "system"},
90 {"dccfgr" , GROUP0 + 5, "org.gnu.gdb.or1k.group0", "system"},
91 {"iccfgr" , GROUP0 + 6, "org.gnu.gdb.or1k.group0", "system"},
92 {"dcfgr" , GROUP0 + 7, "org.gnu.gdb.or1k.group0", "system"},
93 {"pccfgr" , GROUP0 + 8, "org.gnu.gdb.or1k.group0", "system"},
94 {"fpcsr" , GROUP0 + 20, "org.gnu.gdb.or1k.group0", "system"},
95 {"epcr0" , GROUP0 + 32, "org.gnu.gdb.or1k.group0", "system"},
96 {"epcr1" , GROUP0 + 33, "org.gnu.gdb.or1k.group0", "system"},
97 {"epcr2" , GROUP0 + 34, "org.gnu.gdb.or1k.group0", "system"},
98 {"epcr3" , GROUP0 + 35, "org.gnu.gdb.or1k.group0", "system"},
99 {"epcr4" , GROUP0 + 36, "org.gnu.gdb.or1k.group0", "system"},
100 {"epcr5" , GROUP0 + 37, "org.gnu.gdb.or1k.group0", "system"},
101 {"epcr6" , GROUP0 + 38, "org.gnu.gdb.or1k.group0", "system"},
102 {"epcr7" , GROUP0 + 39, "org.gnu.gdb.or1k.group0", "system"},
103 {"epcr8" , GROUP0 + 40, "org.gnu.gdb.or1k.group0", "system"},
104 {"epcr9" , GROUP0 + 41, "org.gnu.gdb.or1k.group0", "system"},
105 {"epcr10" , GROUP0 + 42, "org.gnu.gdb.or1k.group0", "system"},
106 {"epcr11" , GROUP0 + 43, "org.gnu.gdb.or1k.group0", "system"},
107 {"epcr12" , GROUP0 + 44, "org.gnu.gdb.or1k.group0", "system"},
108 {"epcr13" , GROUP0 + 45, "org.gnu.gdb.or1k.group0", "system"},
109 {"epcr14" , GROUP0 + 46, "org.gnu.gdb.or1k.group0", "system"},
110 {"epcr15" , GROUP0 + 47, "org.gnu.gdb.or1k.group0", "system"},
111 {"eear0" , GROUP0 + 48, "org.gnu.gdb.or1k.group0", "system"},
112 {"eear1" , GROUP0 + 49, "org.gnu.gdb.or1k.group0", "system"},
113 {"eear2" , GROUP0 + 50, "org.gnu.gdb.or1k.group0", "system"},
114 {"eear3" , GROUP0 + 51, "org.gnu.gdb.or1k.group0", "system"},
115 {"eear4" , GROUP0 + 52, "org.gnu.gdb.or1k.group0", "system"},
116 {"eear5" , GROUP0 + 53, "org.gnu.gdb.or1k.group0", "system"},
117 {"eear6" , GROUP0 + 54, "org.gnu.gdb.or1k.group0", "system"},
118 {"eear7" , GROUP0 + 55, "org.gnu.gdb.or1k.group0", "system"},
119 {"eear8" , GROUP0 + 56, "org.gnu.gdb.or1k.group0", "system"},
120 {"eear9" , GROUP0 + 57, "org.gnu.gdb.or1k.group0", "system"},
121 {"eear10" , GROUP0 + 58, "org.gnu.gdb.or1k.group0", "system"},
122 {"eear11" , GROUP0 + 59, "org.gnu.gdb.or1k.group0", "system"},
123 {"eear12" , GROUP0 + 60, "org.gnu.gdb.or1k.group0", "system"},
124 {"eear13" , GROUP0 + 61, "org.gnu.gdb.or1k.group0", "system"},
125 {"eear14" , GROUP0 + 62, "org.gnu.gdb.or1k.group0", "system"},
126 {"eear15" , GROUP0 + 63, "org.gnu.gdb.or1k.group0", "system"},
127 {"esr0" , GROUP0 + 64, "org.gnu.gdb.or1k.group0", "system"},
128 {"esr1" , GROUP0 + 65, "org.gnu.gdb.or1k.group0", "system"},
129 {"esr2" , GROUP0 + 66, "org.gnu.gdb.or1k.group0", "system"},
130 {"esr3" , GROUP0 + 67, "org.gnu.gdb.or1k.group0", "system"},
131 {"esr4" , GROUP0 + 68, "org.gnu.gdb.or1k.group0", "system"},
132 {"esr5" , GROUP0 + 69, "org.gnu.gdb.or1k.group0", "system"},
133 {"esr6" , GROUP0 + 70, "org.gnu.gdb.or1k.group0", "system"},
134 {"esr7" , GROUP0 + 71, "org.gnu.gdb.or1k.group0", "system"},
135 {"esr8" , GROUP0 + 72, "org.gnu.gdb.or1k.group0", "system"},
136 {"esr9" , GROUP0 + 73, "org.gnu.gdb.or1k.group0", "system"},
137 {"esr10" , GROUP0 + 74, "org.gnu.gdb.or1k.group0", "system"},
138 {"esr11" , GROUP0 + 75, "org.gnu.gdb.or1k.group0", "system"},
139 {"esr12" , GROUP0 + 76, "org.gnu.gdb.or1k.group0", "system"},
140 {"esr13" , GROUP0 + 77, "org.gnu.gdb.or1k.group0", "system"},
141 {"esr14" , GROUP0 + 78, "org.gnu.gdb.or1k.group0", "system"},
142 {"esr15" , GROUP0 + 79, "org.gnu.gdb.or1k.group0", "system"},
143
144 {"dmmuucr" , GROUP1 + 0, "org.gnu.gdb.or1k.group1", "dmmu"},
145 {"dmmuupr" , GROUP1 + 1, "org.gnu.gdb.or1k.group1", "dmmu"},
146 {"dtlbeir" , GROUP1 + 2, "org.gnu.gdb.or1k.group1", "dmmu"},
147 {"datbmr0" , GROUP1 + 4, "org.gnu.gdb.or1k.group1", "dmmu"},
148 {"datbmr1" , GROUP1 + 5, "org.gnu.gdb.or1k.group1", "dmmu"},
149 {"datbmr2" , GROUP1 + 6, "org.gnu.gdb.or1k.group1", "dmmu"},
150 {"datbmr3" , GROUP1 + 7, "org.gnu.gdb.or1k.group1", "dmmu"},
151 {"datbtr0" , GROUP1 + 8, "org.gnu.gdb.or1k.group1", "dmmu"},
152 {"datbtr1" , GROUP1 + 9, "org.gnu.gdb.or1k.group1", "dmmu"},
153 {"datbtr2" , GROUP1 + 10, "org.gnu.gdb.or1k.group1", "dmmu"},
154 {"datbtr3" , GROUP1 + 11, "org.gnu.gdb.or1k.group1", "dmmu"},
155
156 {"immucr" , GROUP2 + 0, "org.gnu.gdb.or1k.group2", "immu"},
157 {"immupr" , GROUP2 + 1, "org.gnu.gdb.or1k.group2", "immu"},
158 {"itlbeir" , GROUP2 + 2, "org.gnu.gdb.or1k.group2", "immu"},
159 {"iatbmr0" , GROUP2 + 4, "org.gnu.gdb.or1k.group2", "immu"},
160 {"iatbmr1" , GROUP2 + 5, "org.gnu.gdb.or1k.group2", "immu"},
161 {"iatbmr2" , GROUP2 + 6, "org.gnu.gdb.or1k.group2", "immu"},
162 {"iatbmr3" , GROUP2 + 7, "org.gnu.gdb.or1k.group2", "immu"},
163 {"iatbtr0" , GROUP2 + 8, "org.gnu.gdb.or1k.group2", "immu"},
164 {"iatbtr1" , GROUP2 + 9, "org.gnu.gdb.or1k.group2", "immu"},
165 {"iatbtr2" , GROUP2 + 10, "org.gnu.gdb.or1k.group2", "immu"},
166 {"iatbtr3" , GROUP2 + 11, "org.gnu.gdb.or1k.group2", "immu"},
167
168 {"dccr" , GROUP3 + 0, "org.gnu.gdb.or1k.group3", "dcache"},
169 {"dcbpr" , GROUP3 + 1, "org.gnu.gdb.or1k.group3", "dcache"},
170 {"dcbfr" , GROUP3 + 2, "org.gnu.gdb.or1k.group3", "dcache"},
171 {"dcbir" , GROUP3 + 3, "org.gnu.gdb.or1k.group3", "dcache"},
172 {"dcbwr" , GROUP3 + 4, "org.gnu.gdb.or1k.group3", "dcache"},
173 {"dcblr" , GROUP3 + 5, "org.gnu.gdb.or1k.group3", "dcache"},
174
175 {"iccr" , GROUP4 + 0, "org.gnu.gdb.or1k.group4", "icache"},
176 {"icbpr" , GROUP4 + 1, "org.gnu.gdb.or1k.group4", "icache"},
177 {"icbir" , GROUP4 + 2, "org.gnu.gdb.or1k.group4", "icache"},
178 {"icblr" , GROUP4 + 3, "org.gnu.gdb.or1k.group4", "icache"},
179
180 {"maclo" , GROUP5 + 0, "org.gnu.gdb.or1k.group5", "mac"},
181 {"machi" , GROUP5 + 1, "org.gnu.gdb.or1k.group5", "mac"},
182
183 {"dvr0" , GROUP6 + 0, "org.gnu.gdb.or1k.group6", "debug"},
184 {"dvr1" , GROUP6 + 1, "org.gnu.gdb.or1k.group6", "debug"},
185 {"dvr2" , GROUP6 + 2, "org.gnu.gdb.or1k.group6", "debug"},
186 {"dvr3" , GROUP6 + 3, "org.gnu.gdb.or1k.group6", "debug"},
187 {"dvr4" , GROUP6 + 4, "org.gnu.gdb.or1k.group6", "debug"},
188 {"dvr5" , GROUP6 + 5, "org.gnu.gdb.or1k.group6", "debug"},
189 {"dvr6" , GROUP6 + 6, "org.gnu.gdb.or1k.group6", "debug"},
190 {"dvr7" , GROUP6 + 7, "org.gnu.gdb.or1k.group6", "debug"},
191 {"dcr0" , GROUP6 + 8, "org.gnu.gdb.or1k.group6", "debug"},
192 {"dcr1" , GROUP6 + 9, "org.gnu.gdb.or1k.group6", "debug"},
193 {"dcr2" , GROUP6 + 10, "org.gnu.gdb.or1k.group6", "debug"},
194 {"dcr3" , GROUP6 + 11, "org.gnu.gdb.or1k.group6", "debug"},
195 {"dcr4" , GROUP6 + 12, "org.gnu.gdb.or1k.group6", "debug"},
196 {"dcr5" , GROUP6 + 13, "org.gnu.gdb.or1k.group6", "debug"},
197 {"dcr6" , GROUP6 + 14, "org.gnu.gdb.or1k.group6", "debug"},
198 {"dcr7" , GROUP6 + 15, "org.gnu.gdb.or1k.group6", "debug"},
199 {"dmr1" , GROUP6 + 16, "org.gnu.gdb.or1k.group6", "debug"},
200 {"dmr2" , GROUP6 + 17, "org.gnu.gdb.or1k.group6", "debug"},
201 {"dcwr0" , GROUP6 + 18, "org.gnu.gdb.or1k.group6", "debug"},
202 {"dcwr1" , GROUP6 + 19, "org.gnu.gdb.or1k.group6", "debug"},
203 {"dsr" , GROUP6 + 20, "org.gnu.gdb.or1k.group6", "debug"},
204 {"drr" , GROUP6 + 21, "org.gnu.gdb.or1k.group6", "debug"},
205
206 {"pccr0" , GROUP7 + 0, "org.gnu.gdb.or1k.group7", "perf"},
207 {"pccr1" , GROUP7 + 1, "org.gnu.gdb.or1k.group7", "perf"},
208 {"pccr2" , GROUP7 + 2, "org.gnu.gdb.or1k.group7", "perf"},
209 {"pccr3" , GROUP7 + 3, "org.gnu.gdb.or1k.group7", "perf"},
210 {"pccr4" , GROUP7 + 4, "org.gnu.gdb.or1k.group7", "perf"},
211 {"pccr5" , GROUP7 + 5, "org.gnu.gdb.or1k.group7", "perf"},
212 {"pccr6" , GROUP7 + 6, "org.gnu.gdb.or1k.group7", "perf"},
213 {"pccr7" , GROUP7 + 7, "org.gnu.gdb.or1k.group7", "perf"},
214 {"pcmr0" , GROUP7 + 8, "org.gnu.gdb.or1k.group7", "perf"},
215 {"pcmr1" , GROUP7 + 9, "org.gnu.gdb.or1k.group7", "perf"},
216 {"pcmr2" , GROUP7 + 10, "org.gnu.gdb.or1k.group7", "perf"},
217 {"pcmr3" , GROUP7 + 11, "org.gnu.gdb.or1k.group7", "perf"},
218 {"pcmr4" , GROUP7 + 12, "org.gnu.gdb.or1k.group7", "perf"},
219 {"pcmr5" , GROUP7 + 13, "org.gnu.gdb.or1k.group7", "perf"},
220 {"pcmr6" , GROUP7 + 14, "org.gnu.gdb.or1k.group7", "perf"},
221 {"pcmr7" , GROUP7 + 15, "org.gnu.gdb.or1k.group7", "perf"},
222
223 {"pmr" , GROUP8 + 0, "org.gnu.gdb.or1k.group8", "power"},
224
225 {"picmr" , GROUP9 + 0, "org.gnu.gdb.or1k.group9", "pic"},
226 {"picsr" , GROUP9 + 2, "org.gnu.gdb.or1k.group9", "pic"},
227
228 {"ttmr" , GROUP10 + 0, "org.gnu.gdb.or1k.group10", "timer"},
229 {"ttcr" , GROUP10 + 1, "org.gnu.gdb.or1k.group10", "timer"},
230 };
231
232 static int or1k_add_reg(struct target *target, struct or1k_core_reg *new_reg)
233 {
234 struct or1k_common *or1k = target_to_or1k(target);
235 int reg_list_size = or1k->nb_regs * sizeof(struct or1k_core_reg);
236
237 or1k_core_reg_list_arch_info = realloc(or1k_core_reg_list_arch_info,
238 reg_list_size + sizeof(struct or1k_core_reg));
239
240 memcpy(&or1k_core_reg_list_arch_info[or1k->nb_regs], new_reg,
241 sizeof(struct or1k_core_reg));
242
243 or1k_core_reg_list_arch_info[or1k->nb_regs].list_num = or1k->nb_regs;
244
245 or1k->nb_regs++;
246
247 return ERROR_OK;
248 }
249
250 static int or1k_create_reg_list(struct target *target)
251 {
252 struct or1k_common *or1k = target_to_or1k(target);
253
254 LOG_DEBUG("-");
255
256 or1k_core_reg_list_arch_info = malloc(ARRAY_SIZE(or1k_init_reg_list) *
257 sizeof(struct or1k_core_reg));
258
259 for (int i = 0; i < (int)ARRAY_SIZE(or1k_init_reg_list); i++) {
260 or1k_core_reg_list_arch_info[i].name = or1k_init_reg_list[i].name;
261 or1k_core_reg_list_arch_info[i].spr_num = or1k_init_reg_list[i].spr_num;
262 or1k_core_reg_list_arch_info[i].group = or1k_init_reg_list[i].group;
263 or1k_core_reg_list_arch_info[i].feature = or1k_init_reg_list[i].feature;
264 or1k_core_reg_list_arch_info[i].list_num = i;
265 or1k_core_reg_list_arch_info[i].target = NULL;
266 or1k_core_reg_list_arch_info[i].or1k_common = NULL;
267 }
268
269 or1k->nb_regs = ARRAY_SIZE(or1k_init_reg_list);
270
271 struct or1k_core_reg new_reg;
272 new_reg.target = NULL;
273 new_reg.or1k_common = NULL;
274
275 char name[32];
276 for (int way = 0; way < 4; way++) {
277 for (int i = 0; i < 128; i++) {
278
279 sprintf(name, "dtlbw%dmr%d", way, i);
280 new_reg.name = strdup(name);
281 new_reg.spr_num = GROUP1 + 512 + i + (way * 256);
282 new_reg.feature = "org.gnu.gdb.or1k.group1";
283 new_reg.group = "dmmu";
284 or1k_add_reg(target, &new_reg);
285
286 sprintf(name, "dtlbw%dtr%d", way, i);
287 new_reg.name = strdup(name);
288 new_reg.spr_num = GROUP1 + 640 + i + (way * 256);
289 new_reg.feature = "org.gnu.gdb.or1k.group1";
290 new_reg.group = "dmmu";
291 or1k_add_reg(target, &new_reg);
292
293
294 sprintf(name, "itlbw%dmr%d", way, i);
295 new_reg.name = strdup(name);
296 new_reg.spr_num = GROUP2 + 512 + i + (way * 256);
297 new_reg.feature = "org.gnu.gdb.or1k.group2";
298 new_reg.group = "immu";
299 or1k_add_reg(target, &new_reg);
300
301
302 sprintf(name, "itlbw%dtr%d", way, i);
303 new_reg.name = strdup(name);
304 new_reg.spr_num = GROUP2 + 640 + i + (way * 256);
305 new_reg.feature = "org.gnu.gdb.or1k.group2";
306 new_reg.group = "immu";
307 or1k_add_reg(target, &new_reg);
308
309 }
310 }
311
312 return ERROR_OK;
313 }
314
315 static int or1k_jtag_read_regs(struct or1k_common *or1k, uint32_t *regs)
316 {
317 struct or1k_du *du_core = or1k_jtag_to_du(&or1k->jtag);
318
319 LOG_DEBUG("-");
320
321 return du_core->or1k_jtag_read_cpu(&or1k->jtag,
322 or1k->arch_info[OR1K_REG_R0].spr_num, OR1K_REG_R31 + 1,
323 regs + OR1K_REG_R0);
324 }
325
326 static int or1k_jtag_write_regs(struct or1k_common *or1k, uint32_t *regs)
327 {
328 struct or1k_du *du_core = or1k_jtag_to_du(&or1k->jtag);
329
330 LOG_DEBUG("-");
331
332 return du_core->or1k_jtag_write_cpu(&or1k->jtag,
333 or1k->arch_info[OR1K_REG_R0].spr_num, OR1K_REG_R31 + 1,
334 &regs[OR1K_REG_R0]);
335 }
336
337 static int or1k_save_context(struct target *target)
338 {
339 struct or1k_common *or1k = target_to_or1k(target);
340 struct or1k_du *du_core = or1k_to_du(or1k);
341 int regs_read = 0;
342 int retval;
343
344 LOG_DEBUG("-");
345
346 for (int i = 0; i < OR1KNUMCOREREGS; i++) {
347 if (!or1k->core_cache->reg_list[i].valid) {
348 if (i == OR1K_REG_PPC || i == OR1K_REG_NPC || i == OR1K_REG_SR) {
349 retval = du_core->or1k_jtag_read_cpu(&or1k->jtag,
350 or1k->arch_info[i].spr_num, 1,
351 &or1k->core_regs[i]);
352 if (retval != ERROR_OK)
353 return retval;
354 } else if (!regs_read) {
355 /* read gpr registers at once (but only one time in this loop) */
356 retval = or1k_jtag_read_regs(or1k, or1k->core_regs);
357 if (retval != ERROR_OK)
358 return retval;
359 /* prevent next reads in this loop */
360 regs_read = 1;
361 }
362 /* We've just updated the core_reg[i], now update
363 the core cache */
364 or1k_read_core_reg(target, i);
365 }
366 }
367
368 return ERROR_OK;
369 }
370
371 static int or1k_restore_context(struct target *target)
372 {
373 struct or1k_common *or1k = target_to_or1k(target);
374 struct or1k_du *du_core = or1k_to_du(or1k);
375 int reg_write = 0;
376 int retval;
377
378 LOG_DEBUG("-");
379
380 for (int i = 0; i < OR1KNUMCOREREGS; i++) {
381 if (or1k->core_cache->reg_list[i].dirty) {
382 or1k_write_core_reg(target, i);
383
384 if (i == OR1K_REG_PPC || i == OR1K_REG_NPC || i == OR1K_REG_SR) {
385 retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
386 or1k->arch_info[i].spr_num, 1,
387 &or1k->core_regs[i]);
388 if (retval != ERROR_OK) {
389 LOG_ERROR("Error while restoring context");
390 return retval;
391 }
392 } else
393 reg_write = 1;
394 }
395 }
396
397 if (reg_write) {
398 /* read gpr registers at once (but only one time in this loop) */
399 retval = or1k_jtag_write_regs(or1k, or1k->core_regs);
400 if (retval != ERROR_OK) {
401 LOG_ERROR("Error while restoring context");
402 return retval;
403 }
404 }
405
406 return ERROR_OK;
407 }
408
409 static int or1k_read_core_reg(struct target *target, int num)
410 {
411 struct or1k_common *or1k = target_to_or1k(target);
412 struct or1k_du *du_core = or1k_to_du(or1k);
413 uint32_t reg_value;
414
415 LOG_DEBUG("-");
416
417 if ((num < 0) || (num >= or1k->nb_regs))
418 return ERROR_COMMAND_SYNTAX_ERROR;
419
420 if ((num >= 0) && (num < OR1KNUMCOREREGS)) {
421 reg_value = or1k->core_regs[num];
422 buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
423 LOG_DEBUG("Read core reg %i value 0x%08" PRIx32, num , reg_value);
424 or1k->core_cache->reg_list[num].valid = 1;
425 or1k->core_cache->reg_list[num].dirty = 0;
426 } else {
427 /* This is an spr, always read value from HW */
428 int retval = du_core->or1k_jtag_read_cpu(&or1k->jtag,
429 or1k->arch_info[num].spr_num, 1, &reg_value);
430 if (retval != ERROR_OK) {
431 LOG_ERROR("Error while reading spr 0x%08" PRIx32, or1k->arch_info[num].spr_num);
432 return retval;
433 }
434 buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
435 LOG_DEBUG("Read spr reg %i value 0x%08" PRIx32, num , reg_value);
436 }
437
438 return ERROR_OK;
439 }
440
441 static int or1k_write_core_reg(struct target *target, int num)
442 {
443 struct or1k_common *or1k = target_to_or1k(target);
444
445 LOG_DEBUG("-");
446
447 if ((num < 0) || (num >= OR1KNUMCOREREGS))
448 return ERROR_COMMAND_SYNTAX_ERROR;
449
450 uint32_t reg_value = buf_get_u32(or1k->core_cache->reg_list[num].value, 0, 32);
451 or1k->core_regs[num] = reg_value;
452 LOG_DEBUG("Write core reg %i value 0x%08" PRIx32, num , reg_value);
453 or1k->core_cache->reg_list[num].valid = 1;
454 or1k->core_cache->reg_list[num].dirty = 0;
455
456 return ERROR_OK;
457 }
458
459 static int or1k_get_core_reg(struct reg *reg)
460 {
461 struct or1k_core_reg *or1k_reg = reg->arch_info;
462 struct target *target = or1k_reg->target;
463
464 LOG_DEBUG("-");
465
466 if (target->state != TARGET_HALTED)
467 return ERROR_TARGET_NOT_HALTED;
468
469 return or1k_read_core_reg(target, or1k_reg->list_num);
470 }
471
472 static int or1k_set_core_reg(struct reg *reg, uint8_t *buf)
473 {
474 struct or1k_core_reg *or1k_reg = reg->arch_info;
475 struct target *target = or1k_reg->target;
476 struct or1k_common *or1k = target_to_or1k(target);
477 struct or1k_du *du_core = or1k_to_du(or1k);
478 uint32_t value = buf_get_u32(buf, 0, 32);
479
480 LOG_DEBUG("-");
481
482 if (target->state != TARGET_HALTED)
483 return ERROR_TARGET_NOT_HALTED;
484
485 if (or1k_reg->list_num < OR1KNUMCOREREGS) {
486 buf_set_u32(reg->value, 0, 32, value);
487 reg->dirty = 1;
488 reg->valid = 1;
489 } else {
490 /* This is an spr, write it to the HW */
491 int retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
492 or1k_reg->spr_num, 1, &value);
493 if (retval != ERROR_OK) {
494 LOG_ERROR("Error while writing spr 0x%08" PRIx32, or1k_reg->spr_num);
495 return retval;
496 }
497 }
498
499 return ERROR_OK;
500 }
501
502 static const struct reg_arch_type or1k_reg_type = {
503 .get = or1k_get_core_reg,
504 .set = or1k_set_core_reg,
505 };
506
507 static struct reg_cache *or1k_build_reg_cache(struct target *target)
508 {
509 struct or1k_common *or1k = target_to_or1k(target);
510 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
511 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
512 struct reg *reg_list = calloc(or1k->nb_regs, sizeof(struct reg));
513 struct or1k_core_reg *arch_info =
514 malloc((or1k->nb_regs) * sizeof(struct or1k_core_reg));
515 struct reg_feature *feature;
516
517 LOG_DEBUG("-");
518
519 /* Build the process context cache */
520 cache->name = "OpenRISC 1000 registers";
521 cache->next = NULL;
522 cache->reg_list = reg_list;
523 cache->num_regs = or1k->nb_regs;
524 (*cache_p) = cache;
525 or1k->core_cache = cache;
526 or1k->arch_info = arch_info;
527
528 for (int i = 0; i < or1k->nb_regs; i++) {
529 arch_info[i] = or1k_core_reg_list_arch_info[i];
530 arch_info[i].target = target;
531 arch_info[i].or1k_common = or1k;
532 reg_list[i].name = or1k_core_reg_list_arch_info[i].name;
533
534 feature = malloc(sizeof(struct reg_feature));
535 feature->name = or1k_core_reg_list_arch_info[i].feature;
536 reg_list[i].feature = feature;
537
538 reg_list[i].group = or1k_core_reg_list_arch_info[i].group;
539 reg_list[i].size = 32;
540 reg_list[i].value = calloc(1, 4);
541 reg_list[i].dirty = 0;
542 reg_list[i].valid = 0;
543 reg_list[i].type = &or1k_reg_type;
544 reg_list[i].arch_info = &arch_info[i];
545 reg_list[i].number = i;
546 reg_list[i].exist = true;
547 }
548
549 return cache;
550 }
551
552 static int or1k_debug_entry(struct target *target)
553 {
554 LOG_DEBUG("-");
555
556 int retval = or1k_save_context(target);
557 if (retval != ERROR_OK) {
558 LOG_ERROR("Error while calling or1k_save_context");
559 return retval;
560 }
561
562 struct or1k_common *or1k = target_to_or1k(target);
563 uint32_t addr = or1k->core_regs[OR1K_REG_NPC];
564
565 if (breakpoint_find(target, addr))
566 /* Halted on a breakpoint, step back to permit executing the instruction there */
567 retval = or1k_set_core_reg(&or1k->core_cache->reg_list[OR1K_REG_NPC],
568 (uint8_t *)&addr);
569
570 return retval;
571 }
572
573 static int or1k_halt(struct target *target)
574 {
575 struct or1k_common *or1k = target_to_or1k(target);
576 struct or1k_du *du_core = or1k_to_du(or1k);
577
578 LOG_DEBUG("target->state: %s",
579 target_state_name(target));
580
581 if (target->state == TARGET_HALTED) {
582 LOG_DEBUG("Target was already halted");
583 return ERROR_OK;
584 }
585
586 if (target->state == TARGET_UNKNOWN)
587 LOG_WARNING("Target was in unknown state when halt was requested");
588
589 if (target->state == TARGET_RESET) {
590 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) &&
591 jtag_get_srst()) {
592 LOG_ERROR("Can't request a halt while in reset if nSRST pulls nTRST");
593 return ERROR_TARGET_FAILURE;
594 } else {
595 target->debug_reason = DBG_REASON_DBGRQ;
596 return ERROR_OK;
597 }
598 }
599
600 int retval = du_core->or1k_cpu_stall(&or1k->jtag, CPU_STALL);
601 if (retval != ERROR_OK) {
602 LOG_ERROR("Impossible to stall the CPU");
603 return retval;
604 }
605
606 target->debug_reason = DBG_REASON_DBGRQ;
607
608 return ERROR_OK;
609 }
610
611 static int or1k_is_cpu_running(struct target *target, int *running)
612 {
613 struct or1k_common *or1k = target_to_or1k(target);
614 struct or1k_du *du_core = or1k_to_du(or1k);
615 int retval;
616 int tries = 0;
617 const int RETRIES_MAX = 5;
618
619 /* Have a retry loop to determine of the CPU is running.
620 If target has been hard reset for any reason, it might take a couple
621 of goes before it's ready again.
622 */
623 while (tries < RETRIES_MAX) {
624
625 tries++;
626
627 retval = du_core->or1k_is_cpu_running(&or1k->jtag, running);
628 if (retval != ERROR_OK) {
629 LOG_WARNING("Debug IF CPU control reg read failure.");
630 /* Try once to restart the JTAG infrastructure -
631 quite possibly the board has just been reset. */
632 LOG_WARNING("Resetting JTAG TAP state and reconnectiong to debug IF.");
633 du_core->or1k_jtag_init(&or1k->jtag);
634
635 LOG_WARNING("...attempt %d of %d", tries, RETRIES_MAX);
636
637 alive_sleep(2);
638
639 continue;
640 } else
641 return ERROR_OK;
642 }
643
644 LOG_ERROR("Could not re-establish communication with target");
645 return retval;
646 }
647
648 static int or1k_poll(struct target *target)
649 {
650 int retval;
651 int running;
652
653 retval = or1k_is_cpu_running(target, &running);
654 if (retval != ERROR_OK) {
655 LOG_ERROR("Error while calling or1k_is_cpu_running");
656 return retval;
657 }
658
659 /* check for processor halted */
660 if (!running) {
661 /* It's actually stalled, so update our software's state */
662 if ((target->state == TARGET_RUNNING) ||
663 (target->state == TARGET_RESET)) {
664
665 target->state = TARGET_HALTED;
666
667 retval = or1k_debug_entry(target);
668 if (retval != ERROR_OK) {
669 LOG_ERROR("Error while calling or1k_debug_entry");
670 return retval;
671 }
672
673 target_call_event_callbacks(target,
674 TARGET_EVENT_HALTED);
675 } else if (target->state == TARGET_DEBUG_RUNNING) {
676 target->state = TARGET_HALTED;
677
678 retval = or1k_debug_entry(target);
679 if (retval != ERROR_OK) {
680 LOG_ERROR("Error while calling or1k_debug_entry");
681 return retval;
682 }
683
684 target_call_event_callbacks(target,
685 TARGET_EVENT_DEBUG_HALTED);
686 }
687 } else { /* ... target is running */
688
689 /* If target was supposed to be stalled, stall it again */
690 if (target->state == TARGET_HALTED) {
691
692 target->state = TARGET_RUNNING;
693
694 retval = or1k_halt(target);
695 if (retval != ERROR_OK) {
696 LOG_ERROR("Error while calling or1k_halt");
697 return retval;
698 }
699
700 retval = or1k_debug_entry(target);
701 if (retval != ERROR_OK) {
702 LOG_ERROR("Error while calling or1k_debug_entry");
703 return retval;
704 }
705
706 target_call_event_callbacks(target,
707 TARGET_EVENT_DEBUG_HALTED);
708 }
709
710 target->state = TARGET_RUNNING;
711
712 }
713
714 return ERROR_OK;
715 }
716
717 static int or1k_assert_reset(struct target *target)
718 {
719 struct or1k_common *or1k = target_to_or1k(target);
720 struct or1k_du *du_core = or1k_to_du(or1k);
721
722 LOG_DEBUG("-");
723
724 int retval = du_core->or1k_cpu_reset(&or1k->jtag, CPU_RESET);
725 if (retval != ERROR_OK) {
726 LOG_ERROR("Error while asserting RESET");
727 return retval;
728 }
729
730 return ERROR_OK;
731 }
732
733 static int or1k_deassert_reset(struct target *target)
734 {
735 struct or1k_common *or1k = target_to_or1k(target);
736 struct or1k_du *du_core = or1k_to_du(or1k);
737
738 LOG_DEBUG("-");
739
740 int retval = du_core->or1k_cpu_reset(&or1k->jtag, CPU_NOT_RESET);
741 if (retval != ERROR_OK) {
742 LOG_ERROR("Error while desasserting RESET");
743 return retval;
744 }
745
746 return ERROR_OK;
747 }
748
749 static int or1k_soft_reset_halt(struct target *target)
750 {
751 struct or1k_common *or1k = target_to_or1k(target);
752 struct or1k_du *du_core = or1k_to_du(or1k);
753
754 LOG_DEBUG("-");
755
756 int retval = du_core->or1k_cpu_stall(&or1k->jtag, CPU_STALL);
757 if (retval != ERROR_OK) {
758 LOG_ERROR("Error while stalling the CPU");
759 return retval;
760 }
761
762 retval = or1k_assert_reset(target);
763 if (retval != ERROR_OK)
764 return retval;
765
766 retval = or1k_deassert_reset(target);
767 if (retval != ERROR_OK)
768 return retval;
769
770 return ERROR_OK;
771 }
772
773 static bool is_any_soft_breakpoint(struct target *target)
774 {
775 struct breakpoint *breakpoint = target->breakpoints;
776
777 LOG_DEBUG("-");
778
779 while (breakpoint)
780 if (breakpoint->type == BKPT_SOFT)
781 return true;
782
783 return false;
784 }
785
786 static int or1k_resume_or_step(struct target *target, int current,
787 uint32_t address, int handle_breakpoints,
788 int debug_execution, int step)
789 {
790 struct or1k_common *or1k = target_to_or1k(target);
791 struct or1k_du *du_core = or1k_to_du(or1k);
792 struct breakpoint *breakpoint = NULL;
793 uint32_t resume_pc;
794 uint32_t debug_reg_list[OR1K_DEBUG_REG_NUM];
795
796 LOG_DEBUG("Addr: 0x%" PRIx32 ", stepping: %s, handle breakpoints %s\n",
797 address, step ? "yes" : "no", handle_breakpoints ? "yes" : "no");
798
799 if (target->state != TARGET_HALTED) {
800 LOG_ERROR("Target not halted");
801 return ERROR_TARGET_NOT_HALTED;
802 }
803
804 if (!debug_execution)
805 target_free_all_working_areas(target);
806
807 /* current ? continue on current pc : continue at <address> */
808 if (!current)
809 buf_set_u32(or1k->core_cache->reg_list[OR1K_REG_NPC].value, 0,
810 32, address);
811
812 int retval = or1k_restore_context(target);
813 if (retval != ERROR_OK) {
814 LOG_ERROR("Error while calling or1k_restore_context");
815 return retval;
816 }
817
818 /* read debug registers (starting from DMR1 register) */
819 retval = du_core->or1k_jtag_read_cpu(&or1k->jtag, OR1K_DMR1_CPU_REG_ADD,
820 OR1K_DEBUG_REG_NUM, debug_reg_list);
821 if (retval != ERROR_OK) {
822 LOG_ERROR("Error while reading debug registers");
823 return retval;
824 }
825
826 /* Clear Debug Reason Register (DRR) */
827 debug_reg_list[OR1K_DEBUG_REG_DRR] = 0;
828
829 /* Clear watchpoint break generation in Debug Mode Register 2 (DMR2) */
830 debug_reg_list[OR1K_DEBUG_REG_DMR2] &= ~OR1K_DMR2_WGB;
831 if (step)
832 /* Set the single step trigger in Debug Mode Register 1 (DMR1) */
833 debug_reg_list[OR1K_DEBUG_REG_DMR1] |= OR1K_DMR1_ST | OR1K_DMR1_BT;
834 else
835 /* Clear the single step trigger in Debug Mode Register 1 (DMR1) */
836 debug_reg_list[OR1K_DEBUG_REG_DMR1] &= ~(OR1K_DMR1_ST | OR1K_DMR1_BT);
837
838 /* Set traps to be handled by the debug unit in the Debug Stop
839 Register (DSR). Check if we have any software breakpoints in
840 place before setting this value - the kernel, for instance,
841 relies on l.trap instructions not stalling the processor ! */
842 if (is_any_soft_breakpoint(target) == true)
843 debug_reg_list[OR1K_DEBUG_REG_DSR] |= OR1K_DSR_TE;
844
845 /* Write debug registers (starting from DMR1 register) */
846 retval = du_core->or1k_jtag_write_cpu(&or1k->jtag, OR1K_DMR1_CPU_REG_ADD,
847 OR1K_DEBUG_REG_NUM, debug_reg_list);
848 if (retval != ERROR_OK) {
849 LOG_ERROR("Error while writing back debug registers");
850 return retval;
851 }
852
853 resume_pc = buf_get_u32(or1k->core_cache->reg_list[OR1K_REG_NPC].value,
854 0, 32);
855
856 /* The front-end may request us not to handle breakpoints */
857 if (handle_breakpoints) {
858 /* Single step past breakpoint at current address */
859 breakpoint = breakpoint_find(target, resume_pc);
860 if (breakpoint) {
861 LOG_DEBUG("Unset breakpoint at 0x%08" PRIx32, breakpoint->address);
862 retval = or1k_remove_breakpoint(target, breakpoint);
863 if (retval != ERROR_OK)
864 return retval;
865 }
866 }
867
868 /* Unstall time */
869 retval = du_core->or1k_cpu_stall(&or1k->jtag, CPU_UNSTALL);
870 if (retval != ERROR_OK) {
871 LOG_ERROR("Error while unstalling the CPU");
872 return retval;
873 }
874
875 if (step)
876 target->debug_reason = DBG_REASON_SINGLESTEP;
877 else
878 target->debug_reason = DBG_REASON_NOTHALTED;
879
880 /* Registers are now invalid */
881 register_cache_invalidate(or1k->core_cache);
882
883 if (!debug_execution) {
884 target->state = TARGET_RUNNING;
885 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
886 LOG_DEBUG("Target resumed at 0x%08" PRIx32, resume_pc);
887 } else {
888 target->state = TARGET_DEBUG_RUNNING;
889 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
890 LOG_DEBUG("Target debug resumed at 0x%08" PRIx32, resume_pc);
891 }
892
893 return ERROR_OK;
894 }
895
896 static int or1k_resume(struct target *target, int current,
897 uint32_t address, int handle_breakpoints, int debug_execution)
898 {
899 return or1k_resume_or_step(target, current, address,
900 handle_breakpoints,
901 debug_execution,
902 NO_SINGLE_STEP);
903 }
904
905 static int or1k_step(struct target *target, int current,
906 uint32_t address, int handle_breakpoints)
907 {
908 return or1k_resume_or_step(target, current, address,
909 handle_breakpoints,
910 0,
911 SINGLE_STEP);
912
913 }
914
915 static int or1k_add_breakpoint(struct target *target,
916 struct breakpoint *breakpoint)
917 {
918 struct or1k_common *or1k = target_to_or1k(target);
919 struct or1k_du *du_core = or1k_to_du(or1k);
920 uint8_t data;
921
922 LOG_DEBUG("Adding breakpoint: addr 0x%08" PRIx32 ", len %d, type %d, set: %d, id: %" PRId32,
923 breakpoint->address, breakpoint->length, breakpoint->type,
924 breakpoint->set, breakpoint->unique_id);
925
926 /* Only support SW breakpoints for now. */
927 if (breakpoint->type == BKPT_HARD)
928 LOG_ERROR("HW breakpoints not supported for now. Doing SW breakpoint.");
929
930 /* Read and save the instruction */
931 int retval = du_core->or1k_jtag_read_memory(&or1k->jtag,
932 breakpoint->address,
933 4,
934 1,
935 &data);
936 if (retval != ERROR_OK) {
937 LOG_ERROR("Error while reading the instruction at 0x%08" PRIx32,
938 breakpoint->address);
939 return retval;
940 }
941
942 if (breakpoint->orig_instr != NULL)
943 free(breakpoint->orig_instr);
944
945 breakpoint->orig_instr = malloc(breakpoint->length);
946 memcpy(breakpoint->orig_instr, &data, breakpoint->length);
947
948 /* Sub in the OR1K trap instruction */
949 uint8_t or1k_trap_insn[4];
950 target_buffer_set_u32(target, or1k_trap_insn, OR1K_TRAP_INSTR);
951 retval = du_core->or1k_jtag_write_memory(&or1k->jtag,
952 breakpoint->address,
953 4,
954 1,
955 or1k_trap_insn);
956
957 if (retval != ERROR_OK) {
958 LOG_ERROR("Error while writing OR1K_TRAP_INSTR at 0x%08" PRIx32,
959 breakpoint->address);
960 return retval;
961 }
962
963 /* invalidate instruction cache */
964 retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
965 OR1K_ICBIR_CPU_REG_ADD, 1, &breakpoint->address);
966 if (retval != ERROR_OK) {
967 LOG_ERROR("Error while invalidating the ICACHE");
968 return retval;
969 }
970
971 return ERROR_OK;
972 }
973
974 static int or1k_remove_breakpoint(struct target *target,
975 struct breakpoint *breakpoint)
976 {
977 struct or1k_common *or1k = target_to_or1k(target);
978 struct or1k_du *du_core = or1k_to_du(or1k);
979
980 LOG_DEBUG("Removing breakpoint: addr 0x%08" PRIx32 ", len %d, type %d, set: %d, id: %" PRId32,
981 breakpoint->address, breakpoint->length, breakpoint->type,
982 breakpoint->set, breakpoint->unique_id);
983
984 /* Only support SW breakpoints for now. */
985 if (breakpoint->type == BKPT_HARD)
986 LOG_ERROR("HW breakpoints not supported for now. Doing SW breakpoint.");
987
988 /* Replace the removed instruction */
989 int retval = du_core->or1k_jtag_write_memory(&or1k->jtag,
990 breakpoint->address,
991 4,
992 1,
993 breakpoint->orig_instr);
994
995 if (retval != ERROR_OK) {
996 LOG_ERROR("Error while writing back the instruction at 0x%08" PRIx32,
997 breakpoint->address);
998 return retval;
999 }
1000
1001 /* invalidate instruction cache */
1002 retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
1003 OR1K_ICBIR_CPU_REG_ADD, 1, &breakpoint->address);
1004 if (retval != ERROR_OK) {
1005 LOG_ERROR("Error while invalidating the ICACHE");
1006 return retval;
1007 }
1008
1009 return ERROR_OK;
1010 }
1011
1012 static int or1k_add_watchpoint(struct target *target,
1013 struct watchpoint *watchpoint)
1014 {
1015 LOG_ERROR("%s: implement me", __func__);
1016 return ERROR_OK;
1017 }
1018
1019 static int or1k_remove_watchpoint(struct target *target,
1020 struct watchpoint *watchpoint)
1021 {
1022 LOG_ERROR("%s: implement me", __func__);
1023 return ERROR_OK;
1024 }
1025
1026 static int or1k_read_memory(struct target *target, uint32_t address,
1027 uint32_t size, uint32_t count, uint8_t *buffer)
1028 {
1029 struct or1k_common *or1k = target_to_or1k(target);
1030 struct or1k_du *du_core = or1k_to_du(or1k);
1031
1032 LOG_DEBUG("Read memory at 0x%08" PRIx32 ", size: %" PRIu32 ", count: 0x%08" PRIx32, address, size, count);
1033
1034 if (target->state != TARGET_HALTED) {
1035 LOG_ERROR("Target not halted");
1036 return ERROR_TARGET_NOT_HALTED;
1037 }
1038
1039 /* Sanitize arguments */
1040 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !buffer) {
1041 LOG_ERROR("Bad arguments");
1042 return ERROR_COMMAND_SYNTAX_ERROR;
1043 }
1044
1045 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) {
1046 LOG_ERROR("Can't handle unaligned memory access");
1047 return ERROR_TARGET_UNALIGNED_ACCESS;
1048 }
1049
1050 return du_core->or1k_jtag_read_memory(&or1k->jtag, address, size, count, buffer);
1051 }
1052
1053 static int or1k_write_memory(struct target *target, uint32_t address,
1054 uint32_t size, uint32_t count, const uint8_t *buffer)
1055 {
1056 struct or1k_common *or1k = target_to_or1k(target);
1057 struct or1k_du *du_core = or1k_to_du(or1k);
1058
1059 LOG_DEBUG("Write memory at 0x%08" PRIx32 ", size: %" PRIu32 ", count: 0x%08" PRIx32, address, size, count);
1060
1061 if (target->state != TARGET_HALTED) {
1062 LOG_WARNING("Target not halted");
1063 return ERROR_TARGET_NOT_HALTED;
1064 }
1065
1066 /* Sanitize arguments */
1067 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !buffer) {
1068 LOG_ERROR("Bad arguments");
1069 return ERROR_COMMAND_SYNTAX_ERROR;
1070 }
1071
1072 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) {
1073 LOG_ERROR("Can't handle unaligned memory access");
1074 return ERROR_TARGET_UNALIGNED_ACCESS;
1075 }
1076
1077 return du_core->or1k_jtag_write_memory(&or1k->jtag, address, size, count, buffer);
1078 }
1079
1080 static int or1k_init_target(struct command_context *cmd_ctx,
1081 struct target *target)
1082 {
1083 struct or1k_common *or1k = target_to_or1k(target);
1084 struct or1k_du *du_core = or1k_to_du(or1k);
1085 struct or1k_jtag *jtag = &or1k->jtag;
1086
1087 if (du_core == NULL) {
1088 LOG_ERROR("No debug unit selected");
1089 return ERROR_FAIL;
1090 }
1091
1092 if (jtag->tap_ip == NULL) {
1093 LOG_ERROR("No tap selected");
1094 return ERROR_FAIL;
1095 }
1096
1097 or1k->jtag.tap = target->tap;
1098 or1k->jtag.or1k_jtag_inited = 0;
1099 or1k->jtag.or1k_jtag_module_selected = -1;
1100 or1k->jtag.target = target;
1101
1102 or1k_build_reg_cache(target);
1103
1104 return ERROR_OK;
1105 }
1106
1107 static int or1k_target_create(struct target *target, Jim_Interp *interp)
1108 {
1109 if (target->tap == NULL)
1110 return ERROR_FAIL;
1111
1112 struct or1k_common *or1k = calloc(1, sizeof(struct or1k_common));
1113
1114 target->arch_info = or1k;
1115
1116 or1k_create_reg_list(target);
1117
1118 or1k_tap_vjtag_register();
1119 or1k_tap_xilinx_bscan_register();
1120 or1k_tap_mohor_register();
1121
1122 or1k_du_adv_register();
1123
1124 return ERROR_OK;
1125 }
1126
1127 static int or1k_examine(struct target *target)
1128 {
1129 struct or1k_common *or1k = target_to_or1k(target);
1130 struct or1k_du *du_core = or1k_to_du(or1k);
1131
1132 if (!target_was_examined(target)) {
1133
1134 target_set_examined(target);
1135
1136 int running;
1137
1138 int retval = du_core->or1k_is_cpu_running(&or1k->jtag, &running);
1139 if (retval != ERROR_OK) {
1140 LOG_ERROR("Couldn't read the CPU state");
1141 return retval;
1142 } else {
1143 if (running)
1144 target->state = TARGET_RUNNING;
1145 else {
1146 LOG_DEBUG("Target is halted");
1147
1148 /* This is the first time we examine the target,
1149 * it is stalled and we don't know why. Let's
1150 * assume this is because of a debug reason.
1151 */
1152 if (target->state == TARGET_UNKNOWN)
1153 target->debug_reason = DBG_REASON_DBGRQ;
1154
1155 target->state = TARGET_HALTED;
1156 }
1157 }
1158 }
1159
1160 return ERROR_OK;
1161 }
1162
1163 static int or1k_arch_state(struct target *target)
1164 {
1165 return ERROR_OK;
1166 }
1167
1168 static int or1k_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
1169 int *reg_list_size, enum target_register_class reg_class)
1170 {
1171 struct or1k_common *or1k = target_to_or1k(target);
1172
1173 if (reg_class == REG_CLASS_GENERAL) {
1174 /* We will have this called whenever GDB connects. */
1175 int retval = or1k_save_context(target);
1176 if (retval != ERROR_OK) {
1177 LOG_ERROR("Error while calling or1k_save_context");
1178 return retval;
1179 }
1180 *reg_list_size = OR1KNUMCOREREGS;
1181 /* this is free()'d back in gdb_server.c's gdb_get_register_packet() */
1182 *reg_list = malloc((*reg_list_size) * sizeof(struct reg *));
1183
1184 for (int i = 0; i < OR1KNUMCOREREGS; i++)
1185 (*reg_list)[i] = &or1k->core_cache->reg_list[i];
1186 } else {
1187 *reg_list_size = or1k->nb_regs;
1188 *reg_list = malloc((*reg_list_size) * sizeof(struct reg *));
1189
1190 for (int i = 0; i < or1k->nb_regs; i++)
1191 (*reg_list)[i] = &or1k->core_cache->reg_list[i];
1192 }
1193
1194 return ERROR_OK;
1195
1196 }
1197
1198 int or1k_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fileio_info)
1199 {
1200 return ERROR_FAIL;
1201 }
1202
1203 static int or1k_checksum_memory(struct target *target, uint32_t address,
1204 uint32_t count, uint32_t *checksum) {
1205
1206 return ERROR_FAIL;
1207 }
1208
1209 static int or1k_profiling(struct target *target, uint32_t *samples,
1210 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1211 {
1212 struct timeval timeout, now;
1213 struct or1k_common *or1k = target_to_or1k(target);
1214 struct or1k_du *du_core = or1k_to_du(or1k);
1215 int retval = ERROR_OK;
1216
1217 gettimeofday(&timeout, NULL);
1218 timeval_add_time(&timeout, seconds, 0);
1219
1220 LOG_INFO("Starting or1k profiling. Sampling npc as fast as we can...");
1221
1222 /* Make sure the target is running */
1223 target_poll(target);
1224 if (target->state == TARGET_HALTED)
1225 retval = target_resume(target, 1, 0, 0, 0);
1226
1227 if (retval != ERROR_OK) {
1228 LOG_ERROR("Error while resuming target");
1229 return retval;
1230 }
1231
1232 uint32_t sample_count = 0;
1233
1234 for (;;) {
1235 uint32_t reg_value;
1236 retval = du_core->or1k_jtag_read_cpu(&or1k->jtag, GROUP0 + 16 /* NPC */, 1, &reg_value);
1237 if (retval != ERROR_OK) {
1238 LOG_ERROR("Error while reading NPC");
1239 return retval;
1240 }
1241
1242 samples[sample_count++] = reg_value;
1243
1244 gettimeofday(&now, NULL);
1245 if ((sample_count >= max_num_samples) ||
1246 ((now.tv_sec >= timeout.tv_sec) && (now.tv_usec >= timeout.tv_usec))) {
1247 LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1248 break;
1249 }
1250 }
1251
1252 *num_samples = sample_count;
1253 return retval;
1254 }
1255
1256 COMMAND_HANDLER(or1k_tap_select_command_handler)
1257 {
1258 struct target *target = get_current_target(CMD_CTX);
1259 struct or1k_common *or1k = target_to_or1k(target);
1260 struct or1k_jtag *jtag = &or1k->jtag;
1261 struct or1k_tap_ip *or1k_tap;
1262
1263 if (CMD_ARGC != 1)
1264 return ERROR_COMMAND_SYNTAX_ERROR;
1265
1266 list_for_each_entry(or1k_tap, &tap_list, list) {
1267 if (or1k_tap->name) {
1268 if (!strcmp(CMD_ARGV[0], or1k_tap->name)) {
1269 jtag->tap_ip = or1k_tap;
1270 LOG_INFO("%s tap selected", or1k_tap->name);
1271 return ERROR_OK;
1272 }
1273 }
1274 }
1275
1276 LOG_ERROR("%s unknown, no tap selected", CMD_ARGV[0]);
1277 return ERROR_COMMAND_SYNTAX_ERROR;
1278 }
1279
1280 COMMAND_HANDLER(or1k_tap_list_command_handler)
1281 {
1282 struct or1k_tap_ip *or1k_tap;
1283
1284 if (CMD_ARGC != 0)
1285 return ERROR_COMMAND_SYNTAX_ERROR;
1286
1287 list_for_each_entry(or1k_tap, &tap_list, list) {
1288 if (or1k_tap->name)
1289 command_print(CMD_CTX, "%s", or1k_tap->name);
1290 }
1291
1292 return ERROR_OK;
1293 }
1294
1295 COMMAND_HANDLER(or1k_du_select_command_handler)
1296 {
1297 struct target *target = get_current_target(CMD_CTX);
1298 struct or1k_common *or1k = target_to_or1k(target);
1299 struct or1k_jtag *jtag = &or1k->jtag;
1300 struct or1k_du *or1k_du;
1301
1302 if (CMD_ARGC > 2)
1303 return ERROR_COMMAND_SYNTAX_ERROR;
1304
1305 list_for_each_entry(or1k_du, &du_list, list) {
1306 if (or1k_du->name) {
1307 if (!strcmp(CMD_ARGV[0], or1k_du->name)) {
1308 jtag->du_core = or1k_du;
1309 LOG_INFO("%s debug unit selected", or1k_du->name);
1310
1311 if (CMD_ARGC == 2) {
1312 int options;
1313 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], options);
1314 or1k_du->options = options;
1315 LOG_INFO("Option %x is passed to %s debug unit"
1316 , options, or1k_du->name);
1317 }
1318
1319 return ERROR_OK;
1320 }
1321 }
1322 }
1323
1324 LOG_ERROR("%s unknown, no debug unit selected", CMD_ARGV[0]);
1325 return ERROR_COMMAND_SYNTAX_ERROR;
1326 }
1327
1328 COMMAND_HANDLER(or1k_du_list_command_handler)
1329 {
1330 struct or1k_du *or1k_du;
1331
1332 if (CMD_ARGC != 0)
1333 return ERROR_COMMAND_SYNTAX_ERROR;
1334
1335 list_for_each_entry(or1k_du, &du_list, list) {
1336 if (or1k_du->name)
1337 command_print(CMD_CTX, "%s", or1k_du->name);
1338 }
1339
1340 return ERROR_OK;
1341 }
1342
1343 COMMAND_HANDLER(or1k_addreg_command_handler)
1344 {
1345 struct target *target = get_current_target(CMD_CTX);
1346 struct or1k_core_reg new_reg;
1347
1348 if (CMD_ARGC != 4)
1349 return ERROR_COMMAND_SYNTAX_ERROR;
1350
1351 new_reg.target = NULL;
1352 new_reg.or1k_common = NULL;
1353
1354 uint32_t addr;
1355 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], addr);
1356
1357 new_reg.name = strdup(CMD_ARGV[0]);
1358 new_reg.spr_num = addr;
1359 new_reg.feature = strdup(CMD_ARGV[2]);
1360 new_reg.group = strdup(CMD_ARGV[3]);
1361
1362 or1k_add_reg(target, &new_reg);
1363
1364 LOG_DEBUG("Add reg \"%s\" @ 0x%08" PRIx32 ", group \"%s\", feature \"%s\"",
1365 new_reg.name, addr, new_reg.group, new_reg.feature);
1366
1367 return ERROR_OK;
1368 }
1369
1370 static const struct command_registration or1k_hw_ip_command_handlers[] = {
1371 {
1372 "tap_select",
1373 .handler = or1k_tap_select_command_handler,
1374 .mode = COMMAND_ANY,
1375 .usage = "tap_select name",
1376 .help = "Select the TAP core to use",
1377 },
1378 {
1379 "tap_list",
1380 .handler = or1k_tap_list_command_handler,
1381 .mode = COMMAND_ANY,
1382 .usage = "tap_list",
1383 .help = "Display available TAP core",
1384 },
1385 {
1386 "du_select",
1387 .handler = or1k_du_select_command_handler,
1388 .mode = COMMAND_ANY,
1389 .usage = "du_select name",
1390 .help = "Select the Debug Unit core to use",
1391 },
1392 {
1393 "du_list",
1394 .handler = or1k_du_list_command_handler,
1395 .mode = COMMAND_ANY,
1396 .usage = "select_tap name",
1397 .help = "Display available Debug Unit core",
1398 },
1399 COMMAND_REGISTRATION_DONE
1400 };
1401
1402 static const struct command_registration or1k_reg_command_handlers[] = {
1403 {
1404 "addreg",
1405 .handler = or1k_addreg_command_handler,
1406 .mode = COMMAND_ANY,
1407 .usage = "addreg name addr feature group",
1408 .help = "Add a register to the register list",
1409 },
1410 COMMAND_REGISTRATION_DONE
1411 };
1412
1413 static const struct command_registration or1k_command_handlers[] = {
1414 {
1415 .chain = or1k_reg_command_handlers,
1416 },
1417 {
1418 .chain = or1k_hw_ip_command_handlers,
1419 },
1420 COMMAND_REGISTRATION_DONE
1421 };
1422
1423
1424 struct target_type or1k_target = {
1425 .name = "or1k",
1426
1427 .poll = or1k_poll,
1428 .arch_state = or1k_arch_state,
1429
1430 .target_request_data = NULL,
1431
1432 .halt = or1k_halt,
1433 .resume = or1k_resume,
1434 .step = or1k_step,
1435
1436 .assert_reset = or1k_assert_reset,
1437 .deassert_reset = or1k_deassert_reset,
1438 .soft_reset_halt = or1k_soft_reset_halt,
1439
1440 .get_gdb_reg_list = or1k_get_gdb_reg_list,
1441
1442 .read_memory = or1k_read_memory,
1443 .write_memory = or1k_write_memory,
1444 .checksum_memory = or1k_checksum_memory,
1445
1446 .commands = or1k_command_handlers,
1447 .add_breakpoint = or1k_add_breakpoint,
1448 .remove_breakpoint = or1k_remove_breakpoint,
1449 .add_watchpoint = or1k_add_watchpoint,
1450 .remove_watchpoint = or1k_remove_watchpoint,
1451
1452 .target_create = or1k_target_create,
1453 .init_target = or1k_init_target,
1454 .examine = or1k_examine,
1455
1456 .get_gdb_fileio_info = or1k_get_gdb_fileio_info,
1457
1458 .profiling = or1k_profiling,
1459 };
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