aice: add Andes AICE support
[openocd.git] / src / target / nds32_reg.h
1 /***************************************************************************
2 * Copyright (C) 2013 by Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
20 #ifndef __NDS32_REG_H__
21 #define __NDS32_REG_H__
22
23 #define SRIDX(a, b, c) ((a << 7) | (b << 3) | c)
24 #define NDS32_REGISTER_DISABLE (0x0)
25
26 enum nds32_reg_number_s {
27 /* general registers */
28 R0 = 0,
29 R1,
30 R2,
31 R3,
32 R4,
33 R5,
34 R6,
35 R7,
36 R8,
37 R9,
38 R10,
39 R11,
40 R12,
41 R13,
42 R14,
43 R15,
44 R16,
45 R17,
46 R18,
47 R19,
48 R20,
49 R21,
50 R22,
51 R23,
52 R24,
53 R25,
54 R26,
55 R27,
56 R28,
57 R29,
58 R30,
59 R31,
60 PC,
61 D0LO,
62 D0HI,
63 D1LO,
64 D1HI,
65 ITB,
66 IFC_LP,
67
68 /* system registers */
69 CR0,
70 CR1,
71 CR2,
72 CR3,
73 CR4,
74 CR5,
75 CR6,
76 IR0,
77 IR1,
78 IR2,
79 IR3,
80 IR4,
81 IR5,
82 IR6,
83 IR7,
84 IR8,
85 IR9,
86 IR10,
87 IR11,
88 IR12,
89 IR13,
90 IR14,
91 IR15,
92 IR16,
93 IR17,
94 IR18,
95 IR19,
96 IR20,
97 IR21,
98 IR22,
99 IR23,
100 IR24,
101 IR25,
102 MR0,
103 MR1,
104 MR2,
105 MR3,
106 MR4,
107 MR5,
108 MR6,
109 MR7,
110 MR8,
111 MR9,
112 MR10,
113 MR11,
114 DR0,
115 DR1,
116 DR2,
117 DR3,
118 DR4,
119 DR5,
120 DR6,
121 DR7,
122 DR8,
123 DR9,
124 DR10,
125 DR11,
126 DR12,
127 DR13,
128 DR14,
129 DR15,
130 DR16,
131 DR17,
132 DR18,
133 DR19,
134 DR20,
135 DR21,
136 DR22,
137 DR23,
138 DR24,
139 DR25,
140 DR26,
141 DR27,
142 DR28,
143 DR29,
144 DR30,
145 DR31,
146 DR32,
147 DR33,
148 DR34,
149 DR35,
150 DR36,
151 DR37,
152 DR38,
153 DR39,
154 DR40,
155 DR41,
156 DR42,
157 DR43,
158 DR44,
159 DR45,
160 DR46,
161 DR47,
162 DR48,
163 PFR0,
164 PFR1,
165 PFR2,
166 PFR3,
167 DMAR0,
168 DMAR1,
169 DMAR2,
170 DMAR3,
171 DMAR4,
172 DMAR5,
173 DMAR6,
174 DMAR7,
175 DMAR8,
176 DMAR9,
177 DMAR10,
178 RACR,
179 FUCPR,
180 IDR0,
181 IDR1,
182 SECUR0,
183
184 /* audio registers */
185 D0L24,
186 D1L24,
187 I0,
188 I1,
189 I2,
190 I3,
191 I4,
192 I5,
193 I6,
194 I7,
195 M1,
196 M2,
197 M3,
198 M5,
199 M6,
200 M7,
201 MOD,
202 LBE,
203 LE,
204 LC,
205 ADM_VBASE,
206 SHFT_CTL0,
207 SHFT_CTL1,
208 CB_CTL,
209 CBB0,
210 CBB1,
211 CBB2,
212 CBB3,
213 CBE0,
214 CBE1,
215 CBE2,
216 CBE3,
217
218 /* fpu */
219 FPCSR,
220 FPCFG,
221 FS0,
222 FS1,
223 FS2,
224 FS3,
225 FS4,
226 FS5,
227 FS6,
228 FS7,
229 FS8,
230 FS9,
231 FS10,
232 FS11,
233 FS12,
234 FS13,
235 FS14,
236 FS15,
237 FS16,
238 FS17,
239 FS18,
240 FS19,
241 FS20,
242 FS21,
243 FS22,
244 FS23,
245 FS24,
246 FS25,
247 FS26,
248 FS27,
249 FS28,
250 FS29,
251 FS30,
252 FS31,
253 FD0,
254 FD1,
255 FD2,
256 FD3,
257 FD4,
258 FD5,
259 FD6,
260 FD7,
261 FD8,
262 FD9,
263 FD10,
264 FD11,
265 FD12,
266 FD13,
267 FD14,
268 FD15,
269 FD16,
270 FD17,
271 FD18,
272 FD19,
273 FD20,
274 FD21,
275 FD22,
276 FD23,
277 FD24,
278 FD25,
279 FD26,
280 FD27,
281 FD28,
282 FD29,
283 FD30,
284 FD31,
285
286 TOTAL_REG_NUM,
287 };
288
289 enum nds32_reg_type_s {
290 NDS32_REG_TYPE_GPR = 0,
291 NDS32_REG_TYPE_SPR,
292 NDS32_REG_TYPE_CR,
293 NDS32_REG_TYPE_IR,
294 NDS32_REG_TYPE_MR,
295 NDS32_REG_TYPE_DR,
296 NDS32_REG_TYPE_PFR,
297 NDS32_REG_TYPE_DMAR,
298 NDS32_REG_TYPE_RACR,
299 NDS32_REG_TYPE_IDR,
300 NDS32_REG_TYPE_AUMR,
301 NDS32_REG_TYPE_SECURE,
302 NDS32_REG_TYPE_FPU,
303 };
304
305 struct nds32_reg_s {
306 const char *simple_mnemonic;
307 const char *symbolic_mnemonic;
308 uint32_t sr_index;
309 enum nds32_reg_type_s type;
310 uint8_t size;
311 };
312
313 void nds32_reg_init(void);
314 uint32_t nds32_reg_sr_index(uint32_t number);
315 enum nds32_reg_type_s nds32_reg_type(uint32_t number);
316 uint8_t nds32_reg_size(uint32_t number);
317 const char *nds32_reg_simple_name(uint32_t number);
318 const char *nds32_reg_symbolic_name(uint32_t number);
319
320 #endif