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target: don't implicitly include "breakpoint.h"
[openocd.git] / src / target / mips_m4k.c
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "breakpoints.h"
27 #include "mips32.h"
28 #include "mips_m4k.h"
29 #include "mips32_dmaacc.h"
30 #include "target_type.h"
31
32
33 /* cli handling */
34
35 /* forward declarations */
36 int mips_m4k_poll(struct target *target);
37 int mips_m4k_halt(struct target *target);
38 int mips_m4k_soft_reset_halt(struct target *target);
39 int mips_m4k_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
40 int mips_m4k_step(struct target *target, int current, uint32_t address, int handle_breakpoints);
41 int mips_m4k_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
42 int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
43 int mips_m4k_register_commands(struct command_context *cmd_ctx);
44 int mips_m4k_init_target(struct command_context *cmd_ctx, struct target *target);
45 int mips_m4k_target_create(struct target *target, Jim_Interp *interp);
46
47 int mips_m4k_examine(struct target *target);
48 int mips_m4k_assert_reset(struct target *target);
49 int mips_m4k_deassert_reset(struct target *target);
50 int mips_m4k_checksum_memory(struct target *target, uint32_t address, uint32_t size, uint32_t *checksum);
51
52 struct target_type mips_m4k_target =
53 {
54 .name = "mips_m4k",
55
56 .poll = mips_m4k_poll,
57 .arch_state = mips32_arch_state,
58
59 .target_request_data = NULL,
60
61 .halt = mips_m4k_halt,
62 .resume = mips_m4k_resume,
63 .step = mips_m4k_step,
64
65 .assert_reset = mips_m4k_assert_reset,
66 .deassert_reset = mips_m4k_deassert_reset,
67 .soft_reset_halt = mips_m4k_soft_reset_halt,
68
69 .get_gdb_reg_list = mips32_get_gdb_reg_list,
70
71 .read_memory = mips_m4k_read_memory,
72 .write_memory = mips_m4k_write_memory,
73 .bulk_write_memory = mips_m4k_bulk_write_memory,
74 .checksum_memory = mips_m4k_checksum_memory,
75 .blank_check_memory = NULL,
76
77 .run_algorithm = mips32_run_algorithm,
78
79 .add_breakpoint = mips_m4k_add_breakpoint,
80 .remove_breakpoint = mips_m4k_remove_breakpoint,
81 .add_watchpoint = mips_m4k_add_watchpoint,
82 .remove_watchpoint = mips_m4k_remove_watchpoint,
83
84 .register_commands = mips_m4k_register_commands,
85 .target_create = mips_m4k_target_create,
86 .init_target = mips_m4k_init_target,
87 .examine = mips_m4k_examine,
88 };
89
90 int mips_m4k_examine_debug_reason(struct target *target)
91 {
92 uint32_t break_status;
93 int retval;
94
95 if ((target->debug_reason != DBG_REASON_DBGRQ)
96 && (target->debug_reason != DBG_REASON_SINGLESTEP))
97 {
98 /* get info about inst breakpoint support */
99 if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK)
100 return retval;
101 if (break_status & 0x1f)
102 {
103 /* we have halted on a breakpoint */
104 if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
105 return retval;
106 target->debug_reason = DBG_REASON_BREAKPOINT;
107 }
108
109 /* get info about data breakpoint support */
110 if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK)
111 return retval;
112 if (break_status & 0x1f)
113 {
114 /* we have halted on a breakpoint */
115 if ((retval = target_write_u32(target, 0xFF302000, 0)) != ERROR_OK)
116 return retval;
117 target->debug_reason = DBG_REASON_WATCHPOINT;
118 }
119 }
120
121 return ERROR_OK;
122 }
123
124 int mips_m4k_debug_entry(struct target *target)
125 {
126 struct mips32_common *mips32 = target->arch_info;
127 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
128 uint32_t debug_reg;
129
130 /* read debug register */
131 mips_ejtag_read_debug(ejtag_info, &debug_reg);
132
133 /* make sure break uit configured */
134 mips32_configure_break_unit(target);
135
136 /* attempt to find halt reason */
137 mips_m4k_examine_debug_reason(target);
138
139 /* clear single step if active */
140 if (debug_reg & EJTAG_DEBUG_DSS)
141 {
142 /* stopped due to single step - clear step bit */
143 mips_ejtag_config_step(ejtag_info, 0);
144 }
145
146 mips32_save_context(target);
147
148 LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
149 *(uint32_t*)(mips32->core_cache->reg_list[MIPS32_PC].value),
150 target_state_name(target));
151
152 return ERROR_OK;
153 }
154
155 int mips_m4k_poll(struct target *target)
156 {
157 int retval;
158 struct mips32_common *mips32 = target->arch_info;
159 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
160 uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
161
162 /* read ejtag control reg */
163 jtag_set_end_state(TAP_IDLE);
164 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
165 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
166
167 /* clear this bit before handling polling
168 * as after reset registers will read zero */
169 if (ejtag_ctrl & EJTAG_CTRL_ROCC)
170 {
171 /* we have detected a reset, clear flag
172 * otherwise ejtag will not work */
173 jtag_set_end_state(TAP_IDLE);
174 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
175
176 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
177 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
178 LOG_DEBUG("Reset Detected");
179 }
180
181 /* check for processor halted */
182 if (ejtag_ctrl & EJTAG_CTRL_BRKST)
183 {
184 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
185 {
186 jtag_set_end_state(TAP_IDLE);
187 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
188
189 target->state = TARGET_HALTED;
190
191 if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
192 return retval;
193
194 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
195 }
196 else if (target->state == TARGET_DEBUG_RUNNING)
197 {
198 target->state = TARGET_HALTED;
199
200 if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
201 return retval;
202
203 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
204 }
205 }
206 else
207 {
208 target->state = TARGET_RUNNING;
209 }
210
211 // LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl);
212
213 return ERROR_OK;
214 }
215
216 int mips_m4k_halt(struct target *target)
217 {
218 struct mips32_common *mips32 = target->arch_info;
219 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
220
221 LOG_DEBUG("target->state: %s",
222 target_state_name(target));
223
224 if (target->state == TARGET_HALTED)
225 {
226 LOG_DEBUG("target was already halted");
227 return ERROR_OK;
228 }
229
230 if (target->state == TARGET_UNKNOWN)
231 {
232 LOG_WARNING("target was in unknown state when halt was requested");
233 }
234
235 if (target->state == TARGET_RESET)
236 {
237 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
238 {
239 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
240 return ERROR_TARGET_FAILURE;
241 }
242 else
243 {
244 /* we came here in a reset_halt or reset_init sequence
245 * debug entry was already prepared in mips32_prepare_reset_halt()
246 */
247 target->debug_reason = DBG_REASON_DBGRQ;
248
249 return ERROR_OK;
250 }
251 }
252
253 /* break processor */
254 mips_ejtag_enter_debug(ejtag_info);
255
256 target->debug_reason = DBG_REASON_DBGRQ;
257
258 return ERROR_OK;
259 }
260
261 int mips_m4k_assert_reset(struct target *target)
262 {
263 struct mips32_common *mips32 = target->arch_info;
264 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
265
266 LOG_DEBUG("target->state: %s",
267 target_state_name(target));
268
269 enum reset_types jtag_reset_config = jtag_get_reset_config();
270 if (!(jtag_reset_config & RESET_HAS_SRST))
271 {
272 LOG_ERROR("Can't assert SRST");
273 return ERROR_FAIL;
274 }
275
276 if (target->reset_halt)
277 {
278 /* use hardware to catch reset */
279 jtag_set_end_state(TAP_IDLE);
280 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
281 }
282 else
283 {
284 jtag_set_end_state(TAP_IDLE);
285 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
286 }
287
288 if (strcmp(target->variant, "ejtag_srst") == 0)
289 {
290 uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
291 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
292 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
293 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
294 }
295 else
296 {
297 /* here we should issue a srst only, but we may have to assert trst as well */
298 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
299 {
300 jtag_add_reset(1, 1);
301 }
302 else
303 {
304 jtag_add_reset(0, 1);
305 }
306 }
307
308 target->state = TARGET_RESET;
309 jtag_add_sleep(50000);
310
311 mips32_invalidate_core_regs(target);
312
313 if (target->reset_halt)
314 {
315 int retval;
316 if ((retval = target_halt(target)) != ERROR_OK)
317 return retval;
318 }
319
320 return ERROR_OK;
321 }
322
323 int mips_m4k_deassert_reset(struct target *target)
324 {
325 LOG_DEBUG("target->state: %s",
326 target_state_name(target));
327
328 /* deassert reset lines */
329 jtag_add_reset(0, 0);
330
331 return ERROR_OK;
332 }
333
334 int mips_m4k_soft_reset_halt(struct target *target)
335 {
336 /* TODO */
337 return ERROR_OK;
338 }
339
340 int mips_m4k_single_step_core(struct target *target)
341 {
342 struct mips32_common *mips32 = target->arch_info;
343 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
344
345 /* configure single step mode */
346 mips_ejtag_config_step(ejtag_info, 1);
347
348 /* disable interrupts while stepping */
349 mips32_enable_interrupts(target, 0);
350
351 /* exit debug mode */
352 mips_ejtag_exit_debug(ejtag_info);
353
354 mips_m4k_debug_entry(target);
355
356 return ERROR_OK;
357 }
358
359 int mips_m4k_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
360 {
361 struct mips32_common *mips32 = target->arch_info;
362 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
363 struct breakpoint *breakpoint = NULL;
364 uint32_t resume_pc;
365
366 if (target->state != TARGET_HALTED)
367 {
368 LOG_WARNING("target not halted");
369 return ERROR_TARGET_NOT_HALTED;
370 }
371
372 if (!debug_execution)
373 {
374 target_free_all_working_areas(target);
375 mips_m4k_enable_breakpoints(target);
376 mips_m4k_enable_watchpoints(target);
377 }
378
379 /* current = 1: continue on current pc, otherwise continue at <address> */
380 if (!current)
381 {
382 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
383 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
384 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
385 }
386
387 resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
388
389 mips32_restore_context(target);
390
391 /* the front-end may request us not to handle breakpoints */
392 if (handle_breakpoints)
393 {
394 /* Single step past breakpoint at current address */
395 if ((breakpoint = breakpoint_find(target, resume_pc)))
396 {
397 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
398 mips_m4k_unset_breakpoint(target, breakpoint);
399 mips_m4k_single_step_core(target);
400 mips_m4k_set_breakpoint(target, breakpoint);
401 }
402 }
403
404 /* enable interrupts if we are running */
405 mips32_enable_interrupts(target, !debug_execution);
406
407 /* exit debug mode */
408 mips_ejtag_exit_debug(ejtag_info);
409 target->debug_reason = DBG_REASON_NOTHALTED;
410
411 /* registers are now invalid */
412 mips32_invalidate_core_regs(target);
413
414 if (!debug_execution)
415 {
416 target->state = TARGET_RUNNING;
417 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
418 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
419 }
420 else
421 {
422 target->state = TARGET_DEBUG_RUNNING;
423 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
424 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
425 }
426
427 return ERROR_OK;
428 }
429
430 int mips_m4k_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
431 {
432 /* get pointers to arch-specific information */
433 struct mips32_common *mips32 = target->arch_info;
434 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
435 struct breakpoint *breakpoint = NULL;
436
437 if (target->state != TARGET_HALTED)
438 {
439 LOG_WARNING("target not halted");
440 return ERROR_TARGET_NOT_HALTED;
441 }
442
443 /* current = 1: continue on current pc, otherwise continue at <address> */
444 if (!current)
445 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
446
447 /* the front-end may request us not to handle breakpoints */
448 if (handle_breakpoints)
449 if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32))))
450 mips_m4k_unset_breakpoint(target, breakpoint);
451
452 /* restore context */
453 mips32_restore_context(target);
454
455 /* configure single step mode */
456 mips_ejtag_config_step(ejtag_info, 1);
457
458 target->debug_reason = DBG_REASON_SINGLESTEP;
459
460 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
461
462 /* disable interrupts while stepping */
463 mips32_enable_interrupts(target, 0);
464
465 /* exit debug mode */
466 mips_ejtag_exit_debug(ejtag_info);
467
468 /* registers are now invalid */
469 mips32_invalidate_core_regs(target);
470
471 if (breakpoint)
472 mips_m4k_set_breakpoint(target, breakpoint);
473
474 LOG_DEBUG("target stepped ");
475
476 mips_m4k_debug_entry(target);
477 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
478
479 return ERROR_OK;
480 }
481
482 void mips_m4k_enable_breakpoints(struct target *target)
483 {
484 struct breakpoint *breakpoint = target->breakpoints;
485
486 /* set any pending breakpoints */
487 while (breakpoint)
488 {
489 if (breakpoint->set == 0)
490 mips_m4k_set_breakpoint(target, breakpoint);
491 breakpoint = breakpoint->next;
492 }
493 }
494
495 int mips_m4k_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
496 {
497 struct mips32_common *mips32 = target->arch_info;
498 struct mips32_comparator * comparator_list = mips32->inst_break_list;
499 int retval;
500
501 if (breakpoint->set)
502 {
503 LOG_WARNING("breakpoint already set");
504 return ERROR_OK;
505 }
506
507 if (breakpoint->type == BKPT_HARD)
508 {
509 int bp_num = 0;
510
511 while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
512 bp_num++;
513 if (bp_num >= mips32->num_inst_bpoints)
514 {
515 LOG_DEBUG("ERROR Can not find free FP Comparator(bpid: %d)",
516 breakpoint->unique_id );
517 LOG_WARNING("ERROR Can not find free FP Comparator");
518 exit(-1);
519 }
520 breakpoint->set = bp_num + 1;
521 comparator_list[bp_num].used = 1;
522 comparator_list[bp_num].bp_value = breakpoint->address;
523 target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
524 target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
525 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
526 LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "",
527 breakpoint->unique_id,
528 bp_num, comparator_list[bp_num].bp_value);
529 }
530 else if (breakpoint->type == BKPT_SOFT)
531 {
532 LOG_DEBUG("bpid: %d", breakpoint->unique_id );
533 if (breakpoint->length == 4)
534 {
535 uint32_t verify = 0xffffffff;
536
537 if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
538 {
539 return retval;
540 }
541 if ((retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP)) != ERROR_OK)
542 {
543 return retval;
544 }
545
546 if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
547 {
548 return retval;
549 }
550 if (verify != MIPS32_SDBBP)
551 {
552 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
553 return ERROR_OK;
554 }
555 }
556 else
557 {
558 uint16_t verify = 0xffff;
559
560 if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
561 {
562 return retval;
563 }
564 if ((retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP)) != ERROR_OK)
565 {
566 return retval;
567 }
568
569 if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
570 {
571 return retval;
572 }
573 if (verify != MIPS16_SDBBP)
574 {
575 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
576 return ERROR_OK;
577 }
578 }
579
580 breakpoint->set = 20; /* Any nice value but 0 */
581 }
582
583 return ERROR_OK;
584 }
585
586 int mips_m4k_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
587 {
588 /* get pointers to arch-specific information */
589 struct mips32_common *mips32 = target->arch_info;
590 struct mips32_comparator * comparator_list = mips32->inst_break_list;
591 int retval;
592
593 if (!breakpoint->set)
594 {
595 LOG_WARNING("breakpoint not set");
596 return ERROR_OK;
597 }
598
599 if (breakpoint->type == BKPT_HARD)
600 {
601 int bp_num = breakpoint->set - 1;
602 if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints))
603 {
604 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
605 breakpoint->unique_id);
606 return ERROR_OK;
607 }
608 LOG_DEBUG("bpid: %d - releasing hw: %d",
609 breakpoint->unique_id,
610 bp_num );
611 comparator_list[bp_num].used = 0;
612 comparator_list[bp_num].bp_value = 0;
613 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
614
615 }
616 else
617 {
618 /* restore original instruction (kept in target endianness) */
619 LOG_DEBUG("bpid: %d", breakpoint->unique_id);
620 if (breakpoint->length == 4)
621 {
622 uint32_t current_instr;
623
624 /* check that user program has not modified breakpoint instruction */
625 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
626 {
627 return retval;
628 }
629 if (current_instr == MIPS32_SDBBP)
630 {
631 if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
632 {
633 return retval;
634 }
635 }
636 }
637 else
638 {
639 uint16_t current_instr;
640
641 /* check that user program has not modified breakpoint instruction */
642 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
643 {
644 return retval;
645 }
646
647 if (current_instr == MIPS16_SDBBP)
648 {
649 if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
650 {
651 return retval;
652 }
653 }
654 }
655 }
656 breakpoint->set = 0;
657
658 return ERROR_OK;
659 }
660
661 int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
662 {
663 struct mips32_common *mips32 = target->arch_info;
664
665 if (breakpoint->type == BKPT_HARD)
666 {
667 if (mips32->num_inst_bpoints_avail < 1)
668 {
669 LOG_INFO("no hardware breakpoint available");
670 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
671 }
672
673 mips32->num_inst_bpoints_avail--;
674 }
675
676 mips_m4k_set_breakpoint(target, breakpoint);
677
678 return ERROR_OK;
679 }
680
681 int mips_m4k_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
682 {
683 /* get pointers to arch-specific information */
684 struct mips32_common *mips32 = target->arch_info;
685
686 if (target->state != TARGET_HALTED)
687 {
688 LOG_WARNING("target not halted");
689 return ERROR_TARGET_NOT_HALTED;
690 }
691
692 if (breakpoint->set)
693 {
694 mips_m4k_unset_breakpoint(target, breakpoint);
695 }
696
697 if (breakpoint->type == BKPT_HARD)
698 mips32->num_inst_bpoints_avail++;
699
700 return ERROR_OK;
701 }
702
703 int mips_m4k_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
704 {
705 struct mips32_common *mips32 = target->arch_info;
706 struct mips32_comparator * comparator_list = mips32->data_break_list;
707 int wp_num = 0;
708 /*
709 * watchpoint enabled, ignore all byte lanes in value register
710 * and exclude both load and store accesses from watchpoint
711 * condition evaluation
712 */
713 int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
714 (0xff << EJTAG_DBCn_BLM_SHIFT);
715
716 if (watchpoint->set)
717 {
718 LOG_WARNING("watchpoint already set");
719 return ERROR_OK;
720 }
721
722 while(comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
723 wp_num++;
724 if (wp_num >= mips32->num_data_bpoints)
725 {
726 LOG_DEBUG("ERROR Can not find free FP Comparator");
727 LOG_WARNING("ERROR Can not find free FP Comparator");
728 exit(-1);
729 }
730
731 if (watchpoint->length != 4)
732 {
733 LOG_ERROR("Only watchpoints of length 4 are supported");
734 return ERROR_TARGET_UNALIGNED_ACCESS;
735 }
736
737 if (watchpoint->address % 4)
738 {
739 LOG_ERROR("Watchpoints address should be word aligned");
740 return ERROR_TARGET_UNALIGNED_ACCESS;
741 }
742
743 switch (watchpoint->rw)
744 {
745 case WPT_READ:
746 enable &= ~EJTAG_DBCn_NOLB;
747 break;
748 case WPT_WRITE:
749 enable &= ~EJTAG_DBCn_NOSB;
750 break;
751 case WPT_ACCESS:
752 enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
753 break;
754 default:
755 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
756 }
757
758 watchpoint->set = wp_num + 1;
759 comparator_list[wp_num].used = 1;
760 comparator_list[wp_num].bp_value = watchpoint->address;
761 target_write_u32(target, comparator_list[wp_num].reg_address, comparator_list[wp_num].bp_value);
762 target_write_u32(target, comparator_list[wp_num].reg_address + 0x08, 0x00000000);
763 target_write_u32(target, comparator_list[wp_num].reg_address + 0x10, 0x00000000);
764 target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, enable);
765 target_write_u32(target, comparator_list[wp_num].reg_address + 0x20, 0);
766 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
767
768 return ERROR_OK;
769 }
770
771 int mips_m4k_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
772 {
773 /* get pointers to arch-specific information */
774 struct mips32_common *mips32 = target->arch_info;
775 struct mips32_comparator * comparator_list = mips32->data_break_list;
776
777 if (!watchpoint->set)
778 {
779 LOG_WARNING("watchpoint not set");
780 return ERROR_OK;
781 }
782
783 int wp_num = watchpoint->set - 1;
784 if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints))
785 {
786 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
787 return ERROR_OK;
788 }
789 comparator_list[wp_num].used = 0;
790 comparator_list[wp_num].bp_value = 0;
791 target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, 0);
792 watchpoint->set = 0;
793
794 return ERROR_OK;
795 }
796
797 int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
798 {
799 struct mips32_common *mips32 = target->arch_info;
800
801 if (mips32->num_data_bpoints_avail < 1)
802 {
803 LOG_INFO("no hardware watchpoints available");
804 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
805 }
806
807 mips32->num_data_bpoints_avail--;
808
809 mips_m4k_set_watchpoint(target, watchpoint);
810 return ERROR_OK;
811 }
812
813 int mips_m4k_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
814 {
815 /* get pointers to arch-specific information */
816 struct mips32_common *mips32 = target->arch_info;
817
818 if (target->state != TARGET_HALTED)
819 {
820 LOG_WARNING("target not halted");
821 return ERROR_TARGET_NOT_HALTED;
822 }
823
824 if (watchpoint->set)
825 {
826 mips_m4k_unset_watchpoint(target, watchpoint);
827 }
828
829 mips32->num_data_bpoints_avail++;
830
831 return ERROR_OK;
832 }
833
834 void mips_m4k_enable_watchpoints(struct target *target)
835 {
836 struct watchpoint *watchpoint = target->watchpoints;
837
838 /* set any pending watchpoints */
839 while (watchpoint)
840 {
841 if (watchpoint->set == 0)
842 mips_m4k_set_watchpoint(target, watchpoint);
843 watchpoint = watchpoint->next;
844 }
845 }
846
847 int mips_m4k_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
848 {
849 struct mips32_common *mips32 = target->arch_info;
850 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
851
852 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
853
854 if (target->state != TARGET_HALTED)
855 {
856 LOG_WARNING("target not halted");
857 return ERROR_TARGET_NOT_HALTED;
858 }
859
860 /* sanitize arguments */
861 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
862 return ERROR_INVALID_ARGUMENTS;
863
864 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
865 return ERROR_TARGET_UNALIGNED_ACCESS;
866
867 /* if noDMA off, use DMAACC mode for memory read */
868 int retval;
869 if (ejtag_info->impcode & EJTAG_IMP_NODMA)
870 retval = mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
871 else
872 retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
873 if (ERROR_OK != retval)
874 return retval;
875
876 return ERROR_OK;
877 }
878
879 int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
880 {
881 struct mips32_common *mips32 = target->arch_info;
882 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
883
884 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
885
886 if (target->state != TARGET_HALTED)
887 {
888 LOG_WARNING("target not halted");
889 return ERROR_TARGET_NOT_HALTED;
890 }
891
892 /* sanitize arguments */
893 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
894 return ERROR_INVALID_ARGUMENTS;
895
896 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
897 return ERROR_TARGET_UNALIGNED_ACCESS;
898
899 /* if noDMA off, use DMAACC mode for memory write */
900 if (ejtag_info->impcode & EJTAG_IMP_NODMA)
901 return mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
902 else
903 return mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
904 }
905
906 int mips_m4k_register_commands(struct command_context *cmd_ctx)
907 {
908 int retval;
909
910 retval = mips32_register_commands(cmd_ctx);
911 return retval;
912 }
913
914 int mips_m4k_init_target(struct command_context *cmd_ctx, struct target *target)
915 {
916 mips32_build_reg_cache(target);
917
918 return ERROR_OK;
919 }
920
921 int mips_m4k_init_arch_info(struct target *target, struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)
922 {
923 struct mips32_common *mips32 = &mips_m4k->mips32_common;
924
925 mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
926
927 /* initialize mips4k specific info */
928 mips32_init_arch_info(target, mips32, tap);
929 mips32->arch_info = mips_m4k;
930
931 return ERROR_OK;
932 }
933
934 int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
935 {
936 struct mips_m4k_common *mips_m4k = calloc(1,sizeof(struct mips_m4k_common));
937
938 mips_m4k_init_arch_info(target, mips_m4k, target->tap);
939
940 return ERROR_OK;
941 }
942
943 int mips_m4k_examine(struct target *target)
944 {
945 int retval;
946 struct mips32_common *mips32 = target->arch_info;
947 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
948 uint32_t idcode = 0;
949
950 if (!target_was_examined(target))
951 {
952 mips_ejtag_get_idcode(ejtag_info, &idcode);
953 ejtag_info->idcode = idcode;
954
955 if (((idcode >> 1) & 0x7FF) == 0x29)
956 {
957 /* we are using a pic32mx so select ejtag port
958 * as it is not selected by default */
959 mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
960 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
961 }
962 }
963
964 /* init rest of ejtag interface */
965 if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
966 return retval;
967
968 if ((retval = mips32_examine(target)) != ERROR_OK)
969 return retval;
970
971 return ERROR_OK;
972 }
973
974 int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
975 {
976 return mips_m4k_write_memory(target, address, 4, count, buffer);
977 }
978
979 int mips_m4k_checksum_memory(struct target *target, uint32_t address, uint32_t size, uint32_t *checksum)
980 {
981 return ERROR_FAIL; /* use bulk read method */
982 }
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