1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
28 #include "mips32_dmaacc.h"
33 /* forward declarations */
34 int mips_m4k_poll(target_t
*target
);
35 int mips_m4k_halt(struct target_s
*target
);
36 int mips_m4k_soft_reset_halt(struct target_s
*target
);
37 int mips_m4k_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
);
38 int mips_m4k_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
);
39 int mips_m4k_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
40 int mips_m4k_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
41 int mips_m4k_register_commands(struct command_context_s
*cmd_ctx
);
42 int mips_m4k_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
43 int mips_m4k_quit(void);
44 int mips_m4k_target_create(struct target_s
*target
, Jim_Interp
*interp
);
46 int mips_m4k_examine(struct target_s
*target
);
47 int mips_m4k_assert_reset(target_t
*target
);
48 int mips_m4k_deassert_reset(target_t
*target
);
49 int mips_m4k_checksum_memory(target_t
*target
, u32 address
, u32 size
, u32
*checksum
);
51 target_type_t mips_m4k_target
=
55 .poll
= mips_m4k_poll
,
56 .arch_state
= mips32_arch_state
,
58 .target_request_data
= NULL
,
60 .halt
= mips_m4k_halt
,
61 .resume
= mips_m4k_resume
,
62 .step
= mips_m4k_step
,
64 .assert_reset
= mips_m4k_assert_reset
,
65 .deassert_reset
= mips_m4k_deassert_reset
,
66 .soft_reset_halt
= mips_m4k_soft_reset_halt
,
68 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
70 .read_memory
= mips_m4k_read_memory
,
71 .write_memory
= mips_m4k_write_memory
,
72 .bulk_write_memory
= mips_m4k_bulk_write_memory
,
73 .checksum_memory
= mips_m4k_checksum_memory
,
74 .blank_check_memory
= NULL
,
76 .run_algorithm
= mips32_run_algorithm
,
78 .add_breakpoint
= mips_m4k_add_breakpoint
,
79 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
80 .add_watchpoint
= mips_m4k_add_watchpoint
,
81 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
83 .register_commands
= mips_m4k_register_commands
,
84 .target_create
= mips_m4k_target_create
,
85 .init_target
= mips_m4k_init_target
,
86 .examine
= mips_m4k_examine
,
90 int mips_m4k_examine_debug_reason(target_t
*target
)
95 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
96 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
98 /* get info about inst breakpoint support */
99 if ((retval
= target_read_u32(target
, EJTAG_IBS
, &break_status
)) != ERROR_OK
)
101 if (break_status
& 0x1f)
103 /* we have halted on a breakpoint */
104 if ((retval
= target_write_u32(target
, EJTAG_IBS
, 0)) != ERROR_OK
)
106 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
109 /* get info about data breakpoint support */
110 if ((retval
= target_read_u32(target
, 0xFF302000, &break_status
)) != ERROR_OK
)
112 if (break_status
& 0x1f)
114 /* we have halted on a breakpoint */
115 if ((retval
= target_write_u32(target
, 0xFF302000, 0)) != ERROR_OK
)
117 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
124 int mips_m4k_debug_entry(target_t
*target
)
126 mips32_common_t
*mips32
= target
->arch_info
;
127 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
130 /* read debug register */
131 mips_ejtag_read_debug(ejtag_info
, &debug_reg
);
133 /* make sure break uit configured */
134 mips32_configure_break_unit(target
);
136 /* attempt to find halt reason */
137 mips_m4k_examine_debug_reason(target
);
139 /* clear single step if active */
140 if (debug_reg
& EJTAG_DEBUG_DSS
)
142 /* stopped due to single step - clear step bit */
143 mips_ejtag_config_step(ejtag_info
, 0);
146 mips32_save_context(target
);
148 LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s",
149 *(u32
*)(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
),
150 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
155 int mips_m4k_poll(target_t
*target
)
158 mips32_common_t
*mips32
= target
->arch_info
;
159 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
160 u32 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
162 /* read ejtag control reg */
163 jtag_add_end_state(TAP_IDLE
);
164 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
165 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
167 /* clear this bit before handling polling
168 * as after reset registers will read zero */
169 if (ejtag_ctrl
& EJTAG_CTRL_ROCC
)
171 /* we have detected a reset, clear flag
172 * otherwise ejtag will not work */
173 jtag_add_end_state(TAP_IDLE
);
174 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_ROCC
;
176 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
177 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
178 LOG_DEBUG("Reset Detected");
181 /* check for processor halted */
182 if (ejtag_ctrl
& EJTAG_CTRL_BRKST
)
184 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
186 jtag_add_end_state(TAP_IDLE
);
187 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
189 target
->state
= TARGET_HALTED
;
191 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
194 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
196 else if (target
->state
== TARGET_DEBUG_RUNNING
)
198 target
->state
= TARGET_HALTED
;
200 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
203 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
208 target
->state
= TARGET_RUNNING
;
211 // LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
216 int mips_m4k_halt(struct target_s
*target
)
218 mips32_common_t
*mips32
= target
->arch_info
;
219 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
221 LOG_DEBUG("target->state: %s",
222 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
224 if (target
->state
== TARGET_HALTED
)
226 LOG_DEBUG("target was already halted");
230 if (target
->state
== TARGET_UNKNOWN
)
232 LOG_WARNING("target was in unknown state when halt was requested");
235 if (target
->state
== TARGET_RESET
)
237 if ((jtag_reset_config
& RESET_SRST_PULLS_TRST
) && jtag_srst
)
239 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
240 return ERROR_TARGET_FAILURE
;
244 /* we came here in a reset_halt or reset_init sequence
245 * debug entry was already prepared in mips32_prepare_reset_halt()
247 target
->debug_reason
= DBG_REASON_DBGRQ
;
253 /* break processor */
254 mips_ejtag_enter_debug(ejtag_info
);
256 target
->debug_reason
= DBG_REASON_DBGRQ
;
261 int mips_m4k_assert_reset(target_t
*target
)
263 mips32_common_t
*mips32
= target
->arch_info
;
264 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
266 LOG_DEBUG("target->state: %s",
267 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
269 if (!(jtag_reset_config
& RESET_HAS_SRST
))
271 LOG_ERROR("Can't assert SRST");
275 if (target
->reset_halt
)
277 /* use hardware to catch reset */
278 jtag_add_end_state(TAP_IDLE
);
279 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
, NULL
);
283 jtag_add_end_state(TAP_IDLE
);
284 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
287 if (strcmp(target
->variant
, "ejtag_srst") == 0)
289 u32 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_PRRST
| EJTAG_CTRL_PERRST
;
290 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
291 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
292 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
296 /* here we should issue a srst only, but we may have to assert trst as well */
297 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
299 jtag_add_reset(1, 1);
303 jtag_add_reset(0, 1);
307 target
->state
= TARGET_RESET
;
308 jtag_add_sleep(50000);
310 mips32_invalidate_core_regs(target
);
312 if (target
->reset_halt
)
315 if ((retval
= target_halt(target
))!=ERROR_OK
)
322 int mips_m4k_deassert_reset(target_t
*target
)
324 LOG_DEBUG("target->state: %s",
325 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
327 /* deassert reset lines */
328 jtag_add_reset(0, 0);
333 int mips_m4k_soft_reset_halt(struct target_s
*target
)
339 int mips_m4k_single_step_core(target_t
*target
)
341 mips32_common_t
*mips32
= target
->arch_info
;
342 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
344 /* configure single step mode */
345 mips_ejtag_config_step(ejtag_info
, 1);
347 /* exit debug mode */
348 mips_ejtag_exit_debug(ejtag_info
, 1);
350 mips_m4k_debug_entry(target
);
355 int mips_m4k_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
357 mips32_common_t
*mips32
= target
->arch_info
;
358 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
359 breakpoint_t
*breakpoint
= NULL
;
362 if (target
->state
!= TARGET_HALTED
)
364 LOG_WARNING("target not halted");
365 return ERROR_TARGET_NOT_HALTED
;
368 if (!debug_execution
)
370 target_free_all_working_areas(target
);
371 mips_m4k_enable_breakpoints(target
);
372 mips_m4k_enable_watchpoints(target
);
375 /* current = 1: continue on current pc, otherwise continue at <address> */
378 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
379 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
380 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
383 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
385 mips32_restore_context(target
);
387 /* the front-end may request us not to handle breakpoints */
388 if (handle_breakpoints
)
390 /* Single step past breakpoint at current address */
391 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
393 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
394 mips_m4k_unset_breakpoint(target
, breakpoint
);
395 mips_m4k_single_step_core(target
);
396 mips_m4k_set_breakpoint(target
, breakpoint
);
400 /* exit debug mode - enable interrupts if required */
401 mips_ejtag_exit_debug(ejtag_info
, !debug_execution
);
402 target
->debug_reason
= DBG_REASON_NOTHALTED
;
404 /* registers are now invalid */
405 mips32_invalidate_core_regs(target
);
407 if (!debug_execution
)
409 target
->state
= TARGET_RUNNING
;
410 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
411 LOG_DEBUG("target resumed at 0x%x", resume_pc
);
415 target
->state
= TARGET_DEBUG_RUNNING
;
416 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
417 LOG_DEBUG("target debug resumed at 0x%x", resume_pc
);
423 int mips_m4k_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
425 /* get pointers to arch-specific information */
426 mips32_common_t
*mips32
= target
->arch_info
;
427 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
428 breakpoint_t
*breakpoint
= NULL
;
430 if (target
->state
!= TARGET_HALTED
)
432 LOG_WARNING("target not halted");
433 return ERROR_TARGET_NOT_HALTED
;
436 /* current = 1: continue on current pc, otherwise continue at <address> */
438 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
440 /* the front-end may request us not to handle breakpoints */
441 if (handle_breakpoints
)
442 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32))))
443 mips_m4k_unset_breakpoint(target
, breakpoint
);
445 /* restore context */
446 mips32_restore_context(target
);
448 /* configure single step mode */
449 mips_ejtag_config_step(ejtag_info
, 1);
451 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
453 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
455 /* exit debug mode */
456 mips_ejtag_exit_debug(ejtag_info
, 1);
458 /* registers are now invalid */
459 mips32_invalidate_core_regs(target
);
462 mips_m4k_set_breakpoint(target
, breakpoint
);
464 LOG_DEBUG("target stepped ");
466 mips_m4k_debug_entry(target
);
467 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
472 void mips_m4k_enable_breakpoints(struct target_s
*target
)
474 breakpoint_t
*breakpoint
= target
->breakpoints
;
476 /* set any pending breakpoints */
479 if (breakpoint
->set
== 0)
480 mips_m4k_set_breakpoint(target
, breakpoint
);
481 breakpoint
= breakpoint
->next
;
485 int mips_m4k_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
487 mips32_common_t
*mips32
= target
->arch_info
;
488 mips32_comparator_t
* comparator_list
= mips32
->inst_break_list
;
493 LOG_WARNING("breakpoint already set");
497 if (breakpoint
->type
== BKPT_HARD
)
501 while(comparator_list
[bp_num
].used
&& (bp_num
< mips32
->num_inst_bpoints
))
503 if (bp_num
>= mips32
->num_inst_bpoints
)
505 LOG_DEBUG("ERROR Can not find free FP Comparator");
506 LOG_WARNING("ERROR Can not find free FP Comparator");
509 breakpoint
->set
= bp_num
+ 1;
510 comparator_list
[bp_num
].used
= 1;
511 comparator_list
[bp_num
].bp_value
= breakpoint
->address
;
512 target_write_u32(target
, comparator_list
[bp_num
].reg_address
, comparator_list
[bp_num
].bp_value
);
513 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x08, 0x00000000);
514 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 1);
515 LOG_DEBUG("bp_num %i bp_value 0x%x", bp_num
, comparator_list
[bp_num
].bp_value
);
517 else if (breakpoint
->type
== BKPT_SOFT
)
519 if (breakpoint
->length
== 4)
521 u32 verify
= 0xffffffff;
523 if((retval
= target
->type
->read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
527 if ((retval
= target_write_u32(target
, breakpoint
->address
, MIPS32_SDBBP
)) != ERROR_OK
)
532 if ((retval
= target_read_u32(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
536 if (verify
!= MIPS32_SDBBP
)
538 LOG_ERROR("Unable to set 32bit breakpoint at address %08x - check that memory is read/writable", breakpoint
->address
);
546 if((retval
= target
->type
->read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
550 if ((retval
= target_write_u16(target
, breakpoint
->address
, MIPS16_SDBBP
)) != ERROR_OK
)
555 if ((retval
= target_read_u16(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
559 if (verify
!= MIPS16_SDBBP
)
561 LOG_ERROR("Unable to set 16bit breakpoint at address %08x - check that memory is read/writable", breakpoint
->address
);
566 breakpoint
->set
= 20; /* Any nice value but 0 */
572 int mips_m4k_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
574 /* get pointers to arch-specific information */
575 mips32_common_t
*mips32
= target
->arch_info
;
576 mips32_comparator_t
* comparator_list
= mips32
->inst_break_list
;
579 if (!breakpoint
->set
)
581 LOG_WARNING("breakpoint not set");
585 if (breakpoint
->type
== BKPT_HARD
)
587 int bp_num
= breakpoint
->set
- 1;
588 if ((bp_num
< 0) || (bp_num
>= mips32
->num_inst_bpoints
))
590 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
593 comparator_list
[bp_num
].used
= 0;
594 comparator_list
[bp_num
].bp_value
= 0;
595 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 0);
599 /* restore original instruction (kept in target endianness) */
600 if (breakpoint
->length
== 4)
604 /* check that user program has not modified breakpoint instruction */
605 if ((retval
= target
->type
->read_memory(target
, breakpoint
->address
, 4, 1, (u8
*)¤t_instr
)) != ERROR_OK
)
609 if (current_instr
== MIPS32_SDBBP
)
611 if((retval
= target
->type
->write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
621 /* check that user program has not modified breakpoint instruction */
622 if ((retval
= target
->type
->read_memory(target
, breakpoint
->address
, 2, 1, (u8
*)¤t_instr
)) != ERROR_OK
)
627 if (current_instr
== MIPS16_SDBBP
)
629 if((retval
= target
->type
->write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
641 int mips_m4k_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
643 mips32_common_t
*mips32
= target
->arch_info
;
645 if (breakpoint
->type
== BKPT_HARD
)
647 if (mips32
->num_inst_bpoints_avail
< 1)
649 LOG_INFO("no hardware breakpoint available");
650 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
653 mips32
->num_inst_bpoints_avail
--;
656 mips_m4k_set_breakpoint(target
, breakpoint
);
661 int mips_m4k_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
663 /* get pointers to arch-specific information */
664 mips32_common_t
*mips32
= target
->arch_info
;
666 if (target
->state
!= TARGET_HALTED
)
668 LOG_WARNING("target not halted");
669 return ERROR_TARGET_NOT_HALTED
;
674 mips_m4k_unset_breakpoint(target
, breakpoint
);
677 if (breakpoint
->type
== BKPT_HARD
)
678 mips32
->num_inst_bpoints_avail
++;
683 int mips_m4k_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
689 int mips_m4k_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
695 int mips_m4k_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
701 int mips_m4k_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
707 void mips_m4k_enable_watchpoints(struct target_s
*target
)
709 watchpoint_t
*watchpoint
= target
->watchpoints
;
711 /* set any pending watchpoints */
714 if (watchpoint
->set
== 0)
715 mips_m4k_set_watchpoint(target
, watchpoint
);
716 watchpoint
= watchpoint
->next
;
720 int mips_m4k_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
722 mips32_common_t
*mips32
= target
->arch_info
;
723 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
725 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
727 if (target
->state
!= TARGET_HALTED
)
729 LOG_WARNING("target not halted");
730 return ERROR_TARGET_NOT_HALTED
;
733 /* sanitize arguments */
734 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
735 return ERROR_INVALID_ARGUMENTS
;
737 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
738 return ERROR_TARGET_UNALIGNED_ACCESS
;
745 /* if noDMA off, use DMAACC mode for memory read */
746 if(ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
747 return mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
749 return mips32_dmaacc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
751 LOG_ERROR("BUG: we shouldn't get here");
759 int mips_m4k_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
761 mips32_common_t
*mips32
= target
->arch_info
;
762 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
764 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
766 if (target
->state
!= TARGET_HALTED
)
768 LOG_WARNING("target not halted");
769 return ERROR_TARGET_NOT_HALTED
;
772 /* sanitize arguments */
773 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
774 return ERROR_INVALID_ARGUMENTS
;
776 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
777 return ERROR_TARGET_UNALIGNED_ACCESS
;
784 /* if noDMA off, use DMAACC mode for memory write */
785 if(ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
786 mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
788 mips32_dmaacc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
791 LOG_ERROR("BUG: we shouldn't get here");
799 int mips_m4k_register_commands(struct command_context_s
*cmd_ctx
)
803 retval
= mips32_register_commands(cmd_ctx
);
807 int mips_m4k_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
809 mips32_build_reg_cache(target
);
814 int mips_m4k_quit(void)
819 int mips_m4k_init_arch_info(target_t
*target
, mips_m4k_common_t
*mips_m4k
, jtag_tap_t
*tap
)
821 mips32_common_t
*mips32
= &mips_m4k
->mips32_common
;
823 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
825 /* initialize mips4k specific info */
826 mips32_init_arch_info(target
, mips32
, tap
);
827 mips32
->arch_info
= mips_m4k
;
832 int mips_m4k_target_create(struct target_s
*target
, Jim_Interp
*interp
)
834 mips_m4k_common_t
*mips_m4k
= calloc(1,sizeof(mips_m4k_common_t
));
836 mips_m4k_init_arch_info(target
, mips_m4k
, target
->tap
);
841 int mips_m4k_examine(struct target_s
*target
)
844 mips32_common_t
*mips32
= target
->arch_info
;
845 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
848 if (!target
->type
->examined
)
850 mips_ejtag_get_idcode(ejtag_info
, &idcode
, NULL
);
851 ejtag_info
->idcode
= idcode
;
853 if (((idcode
>> 1) & 0x7FF) == 0x29)
855 /* we are using a pic32mx so select ejtag port
856 * as it is not selected by default */
857 mips_ejtag_set_instr(ejtag_info
, 0x05, NULL
);
858 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
862 /* init rest of ejtag interface */
863 if ((retval
= mips_ejtag_init(ejtag_info
)) != ERROR_OK
)
866 if ((retval
= mips32_examine(target
)) != ERROR_OK
)
872 int mips_m4k_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
)
874 return mips_m4k_write_memory(target
, address
, 4, count
, buffer
);
877 int mips_m4k_checksum_memory(target_t
*target
, u32 address
, u32 size
, u32
*checksum
)
879 return ERROR_FAIL
; /* use bulk read method */
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