1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
28 #include "mips32_dmaacc.h"
29 #include "target_type.h"
34 /* forward declarations */
35 int mips_m4k_poll(target_t
*target
);
36 int mips_m4k_halt(struct target_s
*target
);
37 int mips_m4k_soft_reset_halt(struct target_s
*target
);
38 int mips_m4k_resume(struct target_s
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
);
39 int mips_m4k_step(struct target_s
*target
, int current
, uint32_t address
, int handle_breakpoints
);
40 int mips_m4k_read_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
41 int mips_m4k_write_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
42 int mips_m4k_register_commands(struct command_context_s
*cmd_ctx
);
43 int mips_m4k_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
44 int mips_m4k_quit(void);
45 int mips_m4k_target_create(struct target_s
*target
, Jim_Interp
*interp
);
47 int mips_m4k_examine(struct target_s
*target
);
48 int mips_m4k_assert_reset(target_t
*target
);
49 int mips_m4k_deassert_reset(target_t
*target
);
50 int mips_m4k_checksum_memory(target_t
*target
, uint32_t address
, uint32_t size
, uint32_t *checksum
);
52 target_type_t mips_m4k_target
=
56 .poll
= mips_m4k_poll
,
57 .arch_state
= mips32_arch_state
,
59 .target_request_data
= NULL
,
61 .halt
= mips_m4k_halt
,
62 .resume
= mips_m4k_resume
,
63 .step
= mips_m4k_step
,
65 .assert_reset
= mips_m4k_assert_reset
,
66 .deassert_reset
= mips_m4k_deassert_reset
,
67 .soft_reset_halt
= mips_m4k_soft_reset_halt
,
69 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
71 .read_memory
= mips_m4k_read_memory
,
72 .write_memory
= mips_m4k_write_memory
,
73 .bulk_write_memory
= mips_m4k_bulk_write_memory
,
74 .checksum_memory
= mips_m4k_checksum_memory
,
75 .blank_check_memory
= NULL
,
77 .run_algorithm
= mips32_run_algorithm
,
79 .add_breakpoint
= mips_m4k_add_breakpoint
,
80 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
81 .add_watchpoint
= mips_m4k_add_watchpoint
,
82 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
84 .register_commands
= mips_m4k_register_commands
,
85 .target_create
= mips_m4k_target_create
,
86 .init_target
= mips_m4k_init_target
,
87 .examine
= mips_m4k_examine
,
91 int mips_m4k_examine_debug_reason(target_t
*target
)
93 uint32_t break_status
;
96 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
97 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
99 /* get info about inst breakpoint support */
100 if ((retval
= target_read_u32(target
, EJTAG_IBS
, &break_status
)) != ERROR_OK
)
102 if (break_status
& 0x1f)
104 /* we have halted on a breakpoint */
105 if ((retval
= target_write_u32(target
, EJTAG_IBS
, 0)) != ERROR_OK
)
107 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
110 /* get info about data breakpoint support */
111 if ((retval
= target_read_u32(target
, 0xFF302000, &break_status
)) != ERROR_OK
)
113 if (break_status
& 0x1f)
115 /* we have halted on a breakpoint */
116 if ((retval
= target_write_u32(target
, 0xFF302000, 0)) != ERROR_OK
)
118 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
125 int mips_m4k_debug_entry(target_t
*target
)
127 mips32_common_t
*mips32
= target
->arch_info
;
128 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
131 /* read debug register */
132 mips_ejtag_read_debug(ejtag_info
, &debug_reg
);
134 /* make sure break uit configured */
135 mips32_configure_break_unit(target
);
137 /* attempt to find halt reason */
138 mips_m4k_examine_debug_reason(target
);
140 /* clear single step if active */
141 if (debug_reg
& EJTAG_DEBUG_DSS
)
143 /* stopped due to single step - clear step bit */
144 mips_ejtag_config_step(ejtag_info
, 0);
147 mips32_save_context(target
);
149 LOG_DEBUG("entered debug state at PC 0x%" PRIx32
", target->state: %s",
150 *(uint32_t*)(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
),
151 target_state_name(target
));
156 int mips_m4k_poll(target_t
*target
)
159 mips32_common_t
*mips32
= target
->arch_info
;
160 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
161 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
163 /* read ejtag control reg */
164 jtag_set_end_state(TAP_IDLE
);
165 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
166 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
168 /* clear this bit before handling polling
169 * as after reset registers will read zero */
170 if (ejtag_ctrl
& EJTAG_CTRL_ROCC
)
172 /* we have detected a reset, clear flag
173 * otherwise ejtag will not work */
174 jtag_set_end_state(TAP_IDLE
);
175 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_ROCC
;
177 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
178 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
179 LOG_DEBUG("Reset Detected");
182 /* check for processor halted */
183 if (ejtag_ctrl
& EJTAG_CTRL_BRKST
)
185 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
187 jtag_set_end_state(TAP_IDLE
);
188 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
190 target
->state
= TARGET_HALTED
;
192 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
195 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
197 else if (target
->state
== TARGET_DEBUG_RUNNING
)
199 target
->state
= TARGET_HALTED
;
201 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
204 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
209 target
->state
= TARGET_RUNNING
;
212 // LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl);
217 int mips_m4k_halt(struct target_s
*target
)
219 mips32_common_t
*mips32
= target
->arch_info
;
220 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
222 LOG_DEBUG("target->state: %s",
223 target_state_name(target
));
225 if (target
->state
== TARGET_HALTED
)
227 LOG_DEBUG("target was already halted");
231 if (target
->state
== TARGET_UNKNOWN
)
233 LOG_WARNING("target was in unknown state when halt was requested");
236 if (target
->state
== TARGET_RESET
)
238 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst())
240 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
241 return ERROR_TARGET_FAILURE
;
245 /* we came here in a reset_halt or reset_init sequence
246 * debug entry was already prepared in mips32_prepare_reset_halt()
248 target
->debug_reason
= DBG_REASON_DBGRQ
;
254 /* break processor */
255 mips_ejtag_enter_debug(ejtag_info
);
257 target
->debug_reason
= DBG_REASON_DBGRQ
;
262 int mips_m4k_assert_reset(target_t
*target
)
264 mips32_common_t
*mips32
= target
->arch_info
;
265 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
267 LOG_DEBUG("target->state: %s",
268 target_state_name(target
));
270 enum reset_types jtag_reset_config
= jtag_get_reset_config();
271 if (!(jtag_reset_config
& RESET_HAS_SRST
))
273 LOG_ERROR("Can't assert SRST");
277 if (target
->reset_halt
)
279 /* use hardware to catch reset */
280 jtag_set_end_state(TAP_IDLE
);
281 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
, NULL
);
285 jtag_set_end_state(TAP_IDLE
);
286 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
289 if (strcmp(target
->variant
, "ejtag_srst") == 0)
291 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_PRRST
| EJTAG_CTRL_PERRST
;
292 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
293 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
294 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
298 /* here we should issue a srst only, but we may have to assert trst as well */
299 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
301 jtag_add_reset(1, 1);
305 jtag_add_reset(0, 1);
309 target
->state
= TARGET_RESET
;
310 jtag_add_sleep(50000);
312 mips32_invalidate_core_regs(target
);
314 if (target
->reset_halt
)
317 if ((retval
= target_halt(target
)) != ERROR_OK
)
324 int mips_m4k_deassert_reset(target_t
*target
)
326 LOG_DEBUG("target->state: %s",
327 target_state_name(target
));
329 /* deassert reset lines */
330 jtag_add_reset(0, 0);
335 int mips_m4k_soft_reset_halt(struct target_s
*target
)
341 int mips_m4k_single_step_core(target_t
*target
)
343 mips32_common_t
*mips32
= target
->arch_info
;
344 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
346 /* configure single step mode */
347 mips_ejtag_config_step(ejtag_info
, 1);
349 /* disable interrupts while stepping */
350 mips32_enable_interrupts(target
, 0);
352 /* exit debug mode */
353 mips_ejtag_exit_debug(ejtag_info
);
355 mips_m4k_debug_entry(target
);
360 int mips_m4k_resume(struct target_s
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
)
362 mips32_common_t
*mips32
= target
->arch_info
;
363 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
364 breakpoint_t
*breakpoint
= NULL
;
367 if (target
->state
!= TARGET_HALTED
)
369 LOG_WARNING("target not halted");
370 return ERROR_TARGET_NOT_HALTED
;
373 if (!debug_execution
)
375 target_free_all_working_areas(target
);
376 mips_m4k_enable_breakpoints(target
);
377 mips_m4k_enable_watchpoints(target
);
380 /* current = 1: continue on current pc, otherwise continue at <address> */
383 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
384 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
385 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
388 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
390 mips32_restore_context(target
);
392 /* the front-end may request us not to handle breakpoints */
393 if (handle_breakpoints
)
395 /* Single step past breakpoint at current address */
396 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
398 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
399 mips_m4k_unset_breakpoint(target
, breakpoint
);
400 mips_m4k_single_step_core(target
);
401 mips_m4k_set_breakpoint(target
, breakpoint
);
405 /* enable interrupts if we are running */
406 mips32_enable_interrupts(target
, !debug_execution
);
408 /* exit debug mode */
409 mips_ejtag_exit_debug(ejtag_info
);
410 target
->debug_reason
= DBG_REASON_NOTHALTED
;
412 /* registers are now invalid */
413 mips32_invalidate_core_regs(target
);
415 if (!debug_execution
)
417 target
->state
= TARGET_RUNNING
;
418 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
419 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
423 target
->state
= TARGET_DEBUG_RUNNING
;
424 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
425 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
431 int mips_m4k_step(struct target_s
*target
, int current
, uint32_t address
, int handle_breakpoints
)
433 /* get pointers to arch-specific information */
434 mips32_common_t
*mips32
= target
->arch_info
;
435 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
436 breakpoint_t
*breakpoint
= NULL
;
438 if (target
->state
!= TARGET_HALTED
)
440 LOG_WARNING("target not halted");
441 return ERROR_TARGET_NOT_HALTED
;
444 /* current = 1: continue on current pc, otherwise continue at <address> */
446 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
448 /* the front-end may request us not to handle breakpoints */
449 if (handle_breakpoints
)
450 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32))))
451 mips_m4k_unset_breakpoint(target
, breakpoint
);
453 /* restore context */
454 mips32_restore_context(target
);
456 /* configure single step mode */
457 mips_ejtag_config_step(ejtag_info
, 1);
459 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
461 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
463 /* disable interrupts while stepping */
464 mips32_enable_interrupts(target
, 0);
466 /* exit debug mode */
467 mips_ejtag_exit_debug(ejtag_info
);
469 /* registers are now invalid */
470 mips32_invalidate_core_regs(target
);
473 mips_m4k_set_breakpoint(target
, breakpoint
);
475 LOG_DEBUG("target stepped ");
477 mips_m4k_debug_entry(target
);
478 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
483 void mips_m4k_enable_breakpoints(struct target_s
*target
)
485 breakpoint_t
*breakpoint
= target
->breakpoints
;
487 /* set any pending breakpoints */
490 if (breakpoint
->set
== 0)
491 mips_m4k_set_breakpoint(target
, breakpoint
);
492 breakpoint
= breakpoint
->next
;
496 int mips_m4k_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
498 mips32_common_t
*mips32
= target
->arch_info
;
499 mips32_comparator_t
* comparator_list
= mips32
->inst_break_list
;
504 LOG_WARNING("breakpoint already set");
508 if (breakpoint
->type
== BKPT_HARD
)
512 while (comparator_list
[bp_num
].used
&& (bp_num
< mips32
->num_inst_bpoints
))
514 if (bp_num
>= mips32
->num_inst_bpoints
)
516 LOG_DEBUG("ERROR Can not find free FP Comparator(bpid: %d)",
517 breakpoint
->unique_id
);
518 LOG_WARNING("ERROR Can not find free FP Comparator");
521 breakpoint
->set
= bp_num
+ 1;
522 comparator_list
[bp_num
].used
= 1;
523 comparator_list
[bp_num
].bp_value
= breakpoint
->address
;
524 target_write_u32(target
, comparator_list
[bp_num
].reg_address
, comparator_list
[bp_num
].bp_value
);
525 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x08, 0x00000000);
526 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 1);
527 LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32
"",
528 breakpoint
->unique_id
,
529 bp_num
, comparator_list
[bp_num
].bp_value
);
531 else if (breakpoint
->type
== BKPT_SOFT
)
533 LOG_DEBUG("bpid: %d", breakpoint
->unique_id
);
534 if (breakpoint
->length
== 4)
536 uint32_t verify
= 0xffffffff;
538 if ((retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
542 if ((retval
= target_write_u32(target
, breakpoint
->address
, MIPS32_SDBBP
)) != ERROR_OK
)
547 if ((retval
= target_read_u32(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
551 if (verify
!= MIPS32_SDBBP
)
553 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
559 uint16_t verify
= 0xffff;
561 if ((retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
565 if ((retval
= target_write_u16(target
, breakpoint
->address
, MIPS16_SDBBP
)) != ERROR_OK
)
570 if ((retval
= target_read_u16(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
574 if (verify
!= MIPS16_SDBBP
)
576 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
581 breakpoint
->set
= 20; /* Any nice value but 0 */
587 int mips_m4k_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
589 /* get pointers to arch-specific information */
590 mips32_common_t
*mips32
= target
->arch_info
;
591 mips32_comparator_t
* comparator_list
= mips32
->inst_break_list
;
594 if (!breakpoint
->set
)
596 LOG_WARNING("breakpoint not set");
600 if (breakpoint
->type
== BKPT_HARD
)
602 int bp_num
= breakpoint
->set
- 1;
603 if ((bp_num
< 0) || (bp_num
>= mips32
->num_inst_bpoints
))
605 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
606 breakpoint
->unique_id
);
609 LOG_DEBUG("bpid: %d - releasing hw: %d",
610 breakpoint
->unique_id
,
612 comparator_list
[bp_num
].used
= 0;
613 comparator_list
[bp_num
].bp_value
= 0;
614 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 0);
619 /* restore original instruction (kept in target endianness) */
620 LOG_DEBUG("bpid: %d", breakpoint
->unique_id
);
621 if (breakpoint
->length
== 4)
623 uint32_t current_instr
;
625 /* check that user program has not modified breakpoint instruction */
626 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, (uint8_t*)¤t_instr
)) != ERROR_OK
)
630 if (current_instr
== MIPS32_SDBBP
)
632 if ((retval
= target_write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
640 uint16_t current_instr
;
642 /* check that user program has not modified breakpoint instruction */
643 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, (uint8_t*)¤t_instr
)) != ERROR_OK
)
648 if (current_instr
== MIPS16_SDBBP
)
650 if ((retval
= target_write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
662 int mips_m4k_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
664 mips32_common_t
*mips32
= target
->arch_info
;
666 if (breakpoint
->type
== BKPT_HARD
)
668 if (mips32
->num_inst_bpoints_avail
< 1)
670 LOG_INFO("no hardware breakpoint available");
671 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
674 mips32
->num_inst_bpoints_avail
--;
677 mips_m4k_set_breakpoint(target
, breakpoint
);
682 int mips_m4k_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
684 /* get pointers to arch-specific information */
685 mips32_common_t
*mips32
= target
->arch_info
;
687 if (target
->state
!= TARGET_HALTED
)
689 LOG_WARNING("target not halted");
690 return ERROR_TARGET_NOT_HALTED
;
695 mips_m4k_unset_breakpoint(target
, breakpoint
);
698 if (breakpoint
->type
== BKPT_HARD
)
699 mips32
->num_inst_bpoints_avail
++;
704 int mips_m4k_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
706 mips32_common_t
*mips32
= target
->arch_info
;
707 mips32_comparator_t
* comparator_list
= mips32
->data_break_list
;
710 * watchpoint enabled, ignore all byte lanes in value register
711 * and exclude both load and store accesses from watchpoint
712 * condition evaluation
714 int enable
= EJTAG_DBCn_NOSB
| EJTAG_DBCn_NOLB
| EJTAG_DBCn_BE
|
715 (0xff << EJTAG_DBCn_BLM_SHIFT
);
719 LOG_WARNING("watchpoint already set");
723 while(comparator_list
[wp_num
].used
&& (wp_num
< mips32
->num_data_bpoints
))
725 if (wp_num
>= mips32
->num_data_bpoints
)
727 LOG_DEBUG("ERROR Can not find free FP Comparator");
728 LOG_WARNING("ERROR Can not find free FP Comparator");
732 if (watchpoint
->length
!= 4)
734 LOG_ERROR("Only watchpoints of length 4 are supported");
735 return ERROR_TARGET_UNALIGNED_ACCESS
;
738 if (watchpoint
->address
% 4)
740 LOG_ERROR("Watchpoints address should be word aligned");
741 return ERROR_TARGET_UNALIGNED_ACCESS
;
744 switch (watchpoint
->rw
)
747 enable
&= ~EJTAG_DBCn_NOLB
;
750 enable
&= ~EJTAG_DBCn_NOSB
;
753 enable
&= ~(EJTAG_DBCn_NOLB
| EJTAG_DBCn_NOSB
);
756 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
759 watchpoint
->set
= wp_num
+ 1;
760 comparator_list
[wp_num
].used
= 1;
761 comparator_list
[wp_num
].bp_value
= watchpoint
->address
;
762 target_write_u32(target
, comparator_list
[wp_num
].reg_address
, comparator_list
[wp_num
].bp_value
);
763 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x08, 0x00000000);
764 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x10, 0x00000000);
765 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x18, enable
);
766 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x20, 0);
767 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32
"", wp_num
, comparator_list
[wp_num
].bp_value
);
772 int mips_m4k_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
774 /* get pointers to arch-specific information */
775 mips32_common_t
*mips32
= target
->arch_info
;
776 mips32_comparator_t
* comparator_list
= mips32
->data_break_list
;
778 if (!watchpoint
->set
)
780 LOG_WARNING("watchpoint not set");
784 int wp_num
= watchpoint
->set
- 1;
785 if ((wp_num
< 0) || (wp_num
>= mips32
->num_data_bpoints
))
787 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
790 comparator_list
[wp_num
].used
= 0;
791 comparator_list
[wp_num
].bp_value
= 0;
792 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x18, 0);
798 int mips_m4k_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
800 mips32_common_t
*mips32
= target
->arch_info
;
802 if (mips32
->num_data_bpoints_avail
< 1)
804 LOG_INFO("no hardware watchpoints available");
805 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
808 mips32
->num_data_bpoints_avail
--;
810 mips_m4k_set_watchpoint(target
, watchpoint
);
814 int mips_m4k_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
816 /* get pointers to arch-specific information */
817 mips32_common_t
*mips32
= target
->arch_info
;
819 if (target
->state
!= TARGET_HALTED
)
821 LOG_WARNING("target not halted");
822 return ERROR_TARGET_NOT_HALTED
;
827 mips_m4k_unset_watchpoint(target
, watchpoint
);
830 mips32
->num_data_bpoints_avail
++;
835 void mips_m4k_enable_watchpoints(struct target_s
*target
)
837 watchpoint_t
*watchpoint
= target
->watchpoints
;
839 /* set any pending watchpoints */
842 if (watchpoint
->set
== 0)
843 mips_m4k_set_watchpoint(target
, watchpoint
);
844 watchpoint
= watchpoint
->next
;
848 int mips_m4k_read_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
850 mips32_common_t
*mips32
= target
->arch_info
;
851 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
853 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
855 if (target
->state
!= TARGET_HALTED
)
857 LOG_WARNING("target not halted");
858 return ERROR_TARGET_NOT_HALTED
;
861 /* sanitize arguments */
862 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
863 return ERROR_INVALID_ARGUMENTS
;
865 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
866 return ERROR_TARGET_UNALIGNED_ACCESS
;
868 /* if noDMA off, use DMAACC mode for memory read */
870 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
871 retval
= mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
873 retval
= mips32_dmaacc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
874 if (ERROR_OK
!= retval
)
880 int mips_m4k_write_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
882 mips32_common_t
*mips32
= target
->arch_info
;
883 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
885 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
887 if (target
->state
!= TARGET_HALTED
)
889 LOG_WARNING("target not halted");
890 return ERROR_TARGET_NOT_HALTED
;
893 /* sanitize arguments */
894 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
895 return ERROR_INVALID_ARGUMENTS
;
897 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
898 return ERROR_TARGET_UNALIGNED_ACCESS
;
900 /* if noDMA off, use DMAACC mode for memory write */
901 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
902 return mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
904 return mips32_dmaacc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
907 int mips_m4k_register_commands(struct command_context_s
*cmd_ctx
)
911 retval
= mips32_register_commands(cmd_ctx
);
915 int mips_m4k_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
917 mips32_build_reg_cache(target
);
922 int mips_m4k_quit(void)
927 int mips_m4k_init_arch_info(target_t
*target
, mips_m4k_common_t
*mips_m4k
, jtag_tap_t
*tap
)
929 mips32_common_t
*mips32
= &mips_m4k
->mips32_common
;
931 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
933 /* initialize mips4k specific info */
934 mips32_init_arch_info(target
, mips32
, tap
);
935 mips32
->arch_info
= mips_m4k
;
940 int mips_m4k_target_create(struct target_s
*target
, Jim_Interp
*interp
)
942 mips_m4k_common_t
*mips_m4k
= calloc(1,sizeof(mips_m4k_common_t
));
944 mips_m4k_init_arch_info(target
, mips_m4k
, target
->tap
);
949 int mips_m4k_examine(struct target_s
*target
)
952 mips32_common_t
*mips32
= target
->arch_info
;
953 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
956 if (!target_was_examined(target
))
958 mips_ejtag_get_idcode(ejtag_info
, &idcode
);
959 ejtag_info
->idcode
= idcode
;
961 if (((idcode
>> 1) & 0x7FF) == 0x29)
963 /* we are using a pic32mx so select ejtag port
964 * as it is not selected by default */
965 mips_ejtag_set_instr(ejtag_info
, 0x05, NULL
);
966 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
970 /* init rest of ejtag interface */
971 if ((retval
= mips_ejtag_init(ejtag_info
)) != ERROR_OK
)
974 if ((retval
= mips32_examine(target
)) != ERROR_OK
)
980 int mips_m4k_bulk_write_memory(target_t
*target
, uint32_t address
, uint32_t count
, uint8_t *buffer
)
982 return mips_m4k_write_memory(target
, address
, 4, count
, buffer
);
985 int mips_m4k_checksum_memory(target_t
*target
, uint32_t address
, uint32_t size
, uint32_t *checksum
)
987 return ERROR_FAIL
; /* use bulk read method */
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)