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target/arc: fix off-by-one error in arc_save_context()
[openocd.git] / src / target / mips_m4k.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2008 by Spencer Oliver *
5 * spen@spen-soft.co.uk *
6 * *
7 * Copyright (C) 2008 by David T.L. Wong *
8 * *
9 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
10 * *
11 * Copyright (C) 2011 by Drasko DRASKOVIC *
12 * drasko.draskovic@gmail.com *
13 ***************************************************************************/
14
15 #ifdef HAVE_CONFIG_H
16 #include "config.h"
17 #endif
18
19 #include "breakpoints.h"
20 #include "mips32.h"
21 #include "mips_m4k.h"
22 #include "mips32_dmaacc.h"
23 #include "target_type.h"
24 #include "register.h"
25 #include "smp.h"
26
27 static void mips_m4k_enable_breakpoints(struct target *target);
28 static void mips_m4k_enable_watchpoints(struct target *target);
29 static int mips_m4k_set_breakpoint(struct target *target,
30 struct breakpoint *breakpoint);
31 static int mips_m4k_unset_breakpoint(struct target *target,
32 struct breakpoint *breakpoint);
33 static int mips_m4k_internal_restore(struct target *target, int current,
34 target_addr_t address, int handle_breakpoints,
35 int debug_execution);
36 static int mips_m4k_halt(struct target *target);
37 static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t address,
38 uint32_t count, const uint8_t *buffer);
39 static int mips_m4k_bulk_read_memory(struct target *target, target_addr_t address,
40 uint32_t count, uint8_t *buffer);
41
42 static int mips_m4k_examine_debug_reason(struct target *target)
43 {
44 struct mips32_common *mips32 = target_to_mips32(target);
45 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
46 uint32_t break_status;
47 int retval;
48
49 if ((target->debug_reason != DBG_REASON_DBGRQ)
50 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
51 if (ejtag_info->debug_caps & EJTAG_DCR_IB) {
52 /* get info about inst breakpoint support */
53 retval = target_read_u32(target,
54 ejtag_info->ejtag_ibs_addr, &break_status);
55 if (retval != ERROR_OK)
56 return retval;
57 if (break_status & 0x1f) {
58 /* we have halted on a breakpoint */
59 retval = target_write_u32(target,
60 ejtag_info->ejtag_ibs_addr, 0);
61 if (retval != ERROR_OK)
62 return retval;
63 target->debug_reason = DBG_REASON_BREAKPOINT;
64 }
65 }
66
67 if (ejtag_info->debug_caps & EJTAG_DCR_DB) {
68 /* get info about data breakpoint support */
69 retval = target_read_u32(target,
70 ejtag_info->ejtag_dbs_addr, &break_status);
71 if (retval != ERROR_OK)
72 return retval;
73 if (break_status & 0x1f) {
74 /* we have halted on a breakpoint */
75 retval = target_write_u32(target,
76 ejtag_info->ejtag_dbs_addr, 0);
77 if (retval != ERROR_OK)
78 return retval;
79 target->debug_reason = DBG_REASON_WATCHPOINT;
80 }
81 }
82 }
83
84 return ERROR_OK;
85 }
86
87 static int mips_m4k_debug_entry(struct target *target)
88 {
89 struct mips32_common *mips32 = target_to_mips32(target);
90 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
91
92 mips32_save_context(target);
93
94 /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
95 mips_ejtag_config_step(ejtag_info, 0);
96
97 /* make sure break unit configured */
98 mips32_configure_break_unit(target);
99
100 /* attempt to find halt reason */
101 mips_m4k_examine_debug_reason(target);
102
103 mips32_read_config_regs(target);
104
105 /* default to mips32 isa, it will be changed below if required */
106 mips32->isa_mode = MIPS32_ISA_MIPS32;
107
108 /* other than mips32 only and isa bit set ? */
109 if (mips32->isa_imp && buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1))
110 mips32->isa_mode = mips32->isa_imp == 2 ? MIPS32_ISA_MIPS16E : MIPS32_ISA_MMIPS32;
111
112 LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
113 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
114 target_state_name(target));
115
116 return ERROR_OK;
117 }
118
119 static struct target *get_mips_m4k(struct target *target, int32_t coreid)
120 {
121 struct target_list *head;
122
123 foreach_smp_target(head, target->smp_targets) {
124 struct target *curr = head->target;
125 if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
126 return curr;
127 }
128 return target;
129 }
130
131 static int mips_m4k_halt_smp(struct target *target)
132 {
133 int retval = ERROR_OK;
134 struct target_list *head;
135
136 foreach_smp_target(head, target->smp_targets) {
137 int ret = ERROR_OK;
138 struct target *curr = head->target;
139 if ((curr != target) && (curr->state != TARGET_HALTED))
140 ret = mips_m4k_halt(curr);
141
142 if (ret != ERROR_OK) {
143 LOG_ERROR("halt failed target->coreid: %" PRId32, curr->coreid);
144 retval = ret;
145 }
146 }
147 return retval;
148 }
149
150 static int update_halt_gdb(struct target *target)
151 {
152 int retval = ERROR_OK;
153 if (target->gdb_service->core[0] == -1) {
154 target->gdb_service->target = target;
155 target->gdb_service->core[0] = target->coreid;
156 retval = mips_m4k_halt_smp(target);
157 }
158 return retval;
159 }
160
161 static int mips_m4k_poll(struct target *target)
162 {
163 int retval = ERROR_OK;
164 struct mips32_common *mips32 = target_to_mips32(target);
165 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
166 uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
167 enum target_state prev_target_state = target->state;
168
169 /* toggle to another core is done by gdb as follow */
170 /* maint packet J core_id */
171 /* continue */
172 /* the next polling trigger an halt event sent to gdb */
173 if ((target->state == TARGET_HALTED) && (target->smp) &&
174 (target->gdb_service) &&
175 (!target->gdb_service->target)) {
176 target->gdb_service->target =
177 get_mips_m4k(target, target->gdb_service->core[1]);
178 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
179 return retval;
180 }
181
182 /* read ejtag control reg */
183 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
184 retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
185 if (retval != ERROR_OK)
186 return retval;
187
188 ejtag_info->isa = (ejtag_ctrl & EJTAG_CTRL_DBGISA) ? 1 : 0;
189
190 /* clear this bit before handling polling
191 * as after reset registers will read zero */
192 if (ejtag_ctrl & EJTAG_CTRL_ROCC) {
193 /* we have detected a reset, clear flag
194 * otherwise ejtag will not work */
195 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
196
197 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
198 retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
199 if (retval != ERROR_OK)
200 return retval;
201 LOG_DEBUG("Reset Detected");
202 }
203
204 /* check for processor halted */
205 if (ejtag_ctrl & EJTAG_CTRL_BRKST) {
206 if ((target->state != TARGET_HALTED)
207 && (target->state != TARGET_DEBUG_RUNNING)) {
208 if (target->state == TARGET_UNKNOWN)
209 LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
210
211 /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
212 * (maybe put on by HALT-ing the board in the previous session).
213 *
214 * Force enable debug entry for this session.
215 */
216 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
217 target->state = TARGET_HALTED;
218 retval = mips_m4k_debug_entry(target);
219 if (retval != ERROR_OK)
220 return retval;
221
222 if (target->smp &&
223 ((prev_target_state == TARGET_RUNNING)
224 || (prev_target_state == TARGET_RESET))) {
225 retval = update_halt_gdb(target);
226 if (retval != ERROR_OK)
227 return retval;
228 }
229 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
230 } else if (target->state == TARGET_DEBUG_RUNNING) {
231 target->state = TARGET_HALTED;
232
233 retval = mips_m4k_debug_entry(target);
234 if (retval != ERROR_OK)
235 return retval;
236
237 if (target->smp) {
238 retval = update_halt_gdb(target);
239 if (retval != ERROR_OK)
240 return retval;
241 }
242
243 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
244 }
245 } else
246 target->state = TARGET_RUNNING;
247
248 /* LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */
249
250 return ERROR_OK;
251 }
252
253 static int mips_m4k_halt(struct target *target)
254 {
255 struct mips32_common *mips32 = target_to_mips32(target);
256 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
257
258 LOG_DEBUG("target->state: %s", target_state_name(target));
259
260 if (target->state == TARGET_HALTED) {
261 LOG_DEBUG("target was already halted");
262 return ERROR_OK;
263 }
264
265 if (target->state == TARGET_UNKNOWN)
266 LOG_WARNING("target was in unknown state when halt was requested");
267
268 if (target->state == TARGET_RESET) {
269 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
270 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
271 return ERROR_TARGET_FAILURE;
272 } else {
273 /* we came here in a reset_halt or reset_init sequence
274 * debug entry was already prepared in mips_m4k_assert_reset()
275 */
276 target->debug_reason = DBG_REASON_DBGRQ;
277
278 return ERROR_OK;
279 }
280 }
281
282 /* break processor */
283 mips_ejtag_enter_debug(ejtag_info);
284
285 target->debug_reason = DBG_REASON_DBGRQ;
286
287 return ERROR_OK;
288 }
289
290 static int mips_m4k_assert_reset(struct target *target)
291 {
292 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
293 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
294
295 /* TODO: apply hw reset signal in not examined state */
296 if (!(target_was_examined(target))) {
297 LOG_WARNING("Reset is not asserted because the target is not examined.");
298 LOG_WARNING("Use a reset button or power cycle the target.");
299 return ERROR_TARGET_NOT_EXAMINED;
300 }
301
302 LOG_DEBUG("target->state: %s",
303 target_state_name(target));
304
305 enum reset_types jtag_reset_config = jtag_get_reset_config();
306
307 /* some cores support connecting while srst is asserted
308 * use that mode is it has been configured */
309
310 bool srst_asserted = false;
311
312 if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
313 (jtag_reset_config & RESET_SRST_NO_GATING)) {
314 jtag_add_reset(0, 1);
315 srst_asserted = true;
316 }
317
318
319 /* EJTAG before v2.5/2.6 does not support EJTAGBOOT or NORMALBOOT */
320 if (ejtag_info->ejtag_version != EJTAG_VERSION_20) {
321 if (target->reset_halt) {
322 /* use hardware to catch reset */
323 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
324 } else
325 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
326 }
327
328 if (jtag_reset_config & RESET_HAS_SRST) {
329 /* here we should issue a srst only, but we may have to assert trst as well */
330 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
331 jtag_add_reset(1, 1);
332 else if (!srst_asserted)
333 jtag_add_reset(0, 1);
334 } else if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
335 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
336 } else {
337 if (mips_m4k->is_pic32mx) {
338 LOG_DEBUG("Using MTAP reset to reset processor...");
339
340 /* use microchip specific MTAP reset */
341 mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
342 mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
343
344 mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
345 mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
346 mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
347 } else {
348 /* use ejtag reset - not supported by all cores */
349 uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
350 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
351 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
352 mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
353 }
354 }
355
356 target->state = TARGET_RESET;
357 jtag_add_sleep(50000);
358
359 register_cache_invalidate(mips_m4k->mips32.core_cache);
360
361 if (target->reset_halt) {
362 int retval = target_halt(target);
363 if (retval != ERROR_OK)
364 return retval;
365 }
366
367 return ERROR_OK;
368 }
369
370 static int mips_m4k_deassert_reset(struct target *target)
371 {
372 LOG_DEBUG("target->state: %s", target_state_name(target));
373
374 /* deassert reset lines */
375 jtag_add_reset(0, 0);
376
377 return ERROR_OK;
378 }
379
380 static int mips_m4k_single_step_core(struct target *target)
381 {
382 struct mips32_common *mips32 = target_to_mips32(target);
383 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
384
385 /* configure single step mode */
386 mips_ejtag_config_step(ejtag_info, 1);
387
388 /* disable interrupts while stepping */
389 mips32_enable_interrupts(target, 0);
390
391 /* exit debug mode */
392 mips_ejtag_exit_debug(ejtag_info);
393
394 mips_m4k_debug_entry(target);
395
396 return ERROR_OK;
397 }
398
399 static int mips_m4k_restore_smp(struct target *target, uint32_t address, int handle_breakpoints)
400 {
401 int retval = ERROR_OK;
402 struct target_list *head;
403
404 foreach_smp_target(head, target->smp_targets) {
405 int ret = ERROR_OK;
406 struct target *curr = head->target;
407 if ((curr != target) && (curr->state != TARGET_RUNNING)) {
408 /* resume current address , not in step mode */
409 ret = mips_m4k_internal_restore(curr, 1, address,
410 handle_breakpoints, 0);
411
412 if (ret != ERROR_OK) {
413 LOG_ERROR("target->coreid :%" PRId32 " failed to resume at address :0x%" PRIx32,
414 curr->coreid, address);
415 retval = ret;
416 }
417 }
418 }
419 return retval;
420 }
421
422 static int mips_m4k_internal_restore(struct target *target, int current,
423 target_addr_t address, int handle_breakpoints, int debug_execution)
424 {
425 struct mips32_common *mips32 = target_to_mips32(target);
426 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
427 struct breakpoint *breakpoint = NULL;
428 uint32_t resume_pc;
429
430 if (target->state != TARGET_HALTED) {
431 LOG_WARNING("target not halted");
432 return ERROR_TARGET_NOT_HALTED;
433 }
434
435 if (!debug_execution) {
436 target_free_all_working_areas(target);
437 mips_m4k_enable_breakpoints(target);
438 mips_m4k_enable_watchpoints(target);
439 }
440
441 /* current = 1: continue on current pc, otherwise continue at <address> */
442 if (!current) {
443 mips_m4k_isa_filter(mips32->isa_imp, &address);
444 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
445 mips32->core_cache->reg_list[MIPS32_PC].dirty = true;
446 mips32->core_cache->reg_list[MIPS32_PC].valid = true;
447 }
448
449 if ((mips32->isa_imp > 1) && debug_execution) /* if more than one isa supported */
450 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode);
451
452 if (!current)
453 resume_pc = address;
454 else
455 resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
456
457 mips32_restore_context(target);
458
459 /* the front-end may request us not to handle breakpoints */
460 if (handle_breakpoints) {
461 /* Single step past breakpoint at current address */
462 breakpoint = breakpoint_find(target, resume_pc);
463 if (breakpoint) {
464 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT "",
465 breakpoint->address);
466 mips_m4k_unset_breakpoint(target, breakpoint);
467 mips_m4k_single_step_core(target);
468 mips_m4k_set_breakpoint(target, breakpoint);
469 }
470 }
471
472 /* enable interrupts if we are running */
473 mips32_enable_interrupts(target, !debug_execution);
474
475 /* exit debug mode */
476 mips_ejtag_exit_debug(ejtag_info);
477 target->debug_reason = DBG_REASON_NOTHALTED;
478
479 /* registers are now invalid */
480 register_cache_invalidate(mips32->core_cache);
481
482 if (!debug_execution) {
483 target->state = TARGET_RUNNING;
484 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
485 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
486 } else {
487 target->state = TARGET_DEBUG_RUNNING;
488 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
489 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
490 }
491
492 return ERROR_OK;
493 }
494
495 static int mips_m4k_resume(struct target *target, int current,
496 target_addr_t address, int handle_breakpoints, int debug_execution)
497 {
498 int retval = ERROR_OK;
499
500 /* dummy resume for smp toggle in order to reduce gdb impact */
501 if ((target->smp) && (target->gdb_service->core[1] != -1)) {
502 /* simulate a start and halt of target */
503 target->gdb_service->target = NULL;
504 target->gdb_service->core[0] = target->gdb_service->core[1];
505 /* fake resume at next poll we play the target core[1], see poll*/
506 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
507 return retval;
508 }
509
510 retval = mips_m4k_internal_restore(target, current, address,
511 handle_breakpoints,
512 debug_execution);
513
514 if (retval == ERROR_OK && target->smp) {
515 target->gdb_service->core[0] = -1;
516 retval = mips_m4k_restore_smp(target, address, handle_breakpoints);
517 }
518
519 return retval;
520 }
521
522 static int mips_m4k_step(struct target *target, int current,
523 target_addr_t address, int handle_breakpoints)
524 {
525 /* get pointers to arch-specific information */
526 struct mips32_common *mips32 = target_to_mips32(target);
527 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
528 struct breakpoint *breakpoint = NULL;
529
530 if (target->state != TARGET_HALTED) {
531 LOG_WARNING("target not halted");
532 return ERROR_TARGET_NOT_HALTED;
533 }
534
535 /* current = 1: continue on current pc, otherwise continue at <address> */
536 if (!current) {
537 mips_m4k_isa_filter(mips32->isa_imp, &address);
538 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
539 mips32->core_cache->reg_list[MIPS32_PC].dirty = true;
540 mips32->core_cache->reg_list[MIPS32_PC].valid = true;
541 }
542
543 /* the front-end may request us not to handle breakpoints */
544 if (handle_breakpoints) {
545 breakpoint = breakpoint_find(target,
546 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
547 if (breakpoint)
548 mips_m4k_unset_breakpoint(target, breakpoint);
549 }
550
551 /* restore context */
552 mips32_restore_context(target);
553
554 /* configure single step mode */
555 mips_ejtag_config_step(ejtag_info, 1);
556
557 target->debug_reason = DBG_REASON_SINGLESTEP;
558
559 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
560
561 /* disable interrupts while stepping */
562 mips32_enable_interrupts(target, 0);
563
564 /* exit debug mode */
565 mips_ejtag_exit_debug(ejtag_info);
566
567 /* registers are now invalid */
568 register_cache_invalidate(mips32->core_cache);
569
570 LOG_DEBUG("target stepped ");
571 mips_m4k_debug_entry(target);
572
573 if (breakpoint)
574 mips_m4k_set_breakpoint(target, breakpoint);
575
576 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
577
578 return ERROR_OK;
579 }
580
581 static void mips_m4k_enable_breakpoints(struct target *target)
582 {
583 struct breakpoint *breakpoint = target->breakpoints;
584
585 /* set any pending breakpoints */
586 while (breakpoint) {
587 if (!breakpoint->is_set)
588 mips_m4k_set_breakpoint(target, breakpoint);
589 breakpoint = breakpoint->next;
590 }
591 }
592
593 static int mips_m4k_set_breakpoint(struct target *target,
594 struct breakpoint *breakpoint)
595 {
596 struct mips32_common *mips32 = target_to_mips32(target);
597 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
598 struct mips32_comparator *comparator_list = mips32->inst_break_list;
599 int retval;
600
601 if (breakpoint->is_set) {
602 LOG_WARNING("breakpoint already set");
603 return ERROR_OK;
604 }
605
606 if (breakpoint->type == BKPT_HARD) {
607 int bp_num = 0;
608
609 while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
610 bp_num++;
611 if (bp_num >= mips32->num_inst_bpoints) {
612 LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32 ")",
613 breakpoint->unique_id);
614 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
615 }
616 breakpoint_hw_set(breakpoint, bp_num);
617 comparator_list[bp_num].used = 1;
618 comparator_list[bp_num].bp_value = breakpoint->address;
619
620 if (breakpoint->length != 4) /* make sure isa bit set */
621 comparator_list[bp_num].bp_value |= 1;
622 else /* make sure isa bit cleared */
623 comparator_list[bp_num].bp_value &= ~1;
624
625 /* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved.
626 * Warning: there is no IB ASID registers in 2.0.
627 * Do not set it! :) */
628 if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
629 comparator_list[bp_num].bp_value &= 0xFFFFFFFC;
630
631 target_write_u32(target, comparator_list[bp_num].reg_address,
632 comparator_list[bp_num].bp_value);
633 target_write_u32(target, comparator_list[bp_num].reg_address +
634 ejtag_info->ejtag_ibm_offs, 0x00000000);
635 target_write_u32(target, comparator_list[bp_num].reg_address +
636 ejtag_info->ejtag_ibc_offs, 1);
637 LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
638 breakpoint->unique_id,
639 bp_num, comparator_list[bp_num].bp_value);
640 } else if (breakpoint->type == BKPT_SOFT) {
641 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
642
643 uint32_t isa_req = breakpoint->length & 1; /* micro mips request bit */
644 uint32_t bplength = breakpoint->length & ~1; /* drop micro mips request bit for length */
645 uint32_t bpaddr = breakpoint->address & ~1; /* drop isa bit from address, if set */
646
647 if (bplength == 4) {
648 uint32_t verify = 0xffffffff;
649 uint32_t sdbbp32_instr = MIPS32_SDBBP(isa_req);
650 if (ejtag_info->endianness && isa_req)
651 sdbbp32_instr = SWAP16(sdbbp32_instr);
652
653 if ((breakpoint->address & 3) == 0) { /* word aligned */
654
655 retval = target_read_memory(target, bpaddr, bplength, 1, breakpoint->orig_instr);
656 if (retval != ERROR_OK)
657 return retval;
658
659 retval = target_write_u32(target, bpaddr, sdbbp32_instr);
660 if (retval != ERROR_OK)
661 return retval;
662
663 retval = target_read_u32(target, bpaddr, &verify);
664 if (retval != ERROR_OK)
665 return retval;
666
667 if (verify != sdbbp32_instr)
668 verify = 0;
669
670 } else { /* 16 bit aligned */
671 retval = target_read_memory(target, bpaddr, 2, 2, breakpoint->orig_instr);
672 if (retval != ERROR_OK)
673 return retval;
674
675 uint8_t sdbbp_buf[4];
676 target_buffer_set_u32(target, sdbbp_buf, sdbbp32_instr);
677
678 retval = target_write_memory(target, bpaddr, 2, 2, sdbbp_buf);
679 if (retval != ERROR_OK)
680 return retval;
681
682 retval = target_read_memory(target, bpaddr, 2, 2, sdbbp_buf);
683 if (retval != ERROR_OK)
684 return retval;
685
686 if (target_buffer_get_u32(target, sdbbp_buf) != sdbbp32_instr)
687 verify = 0;
688 }
689
690 if (verify == 0) {
691 LOG_ERROR("Unable to set 32bit breakpoint at address %08" TARGET_PRIxADDR
692 " - check that memory is read/writable", breakpoint->address);
693 return ERROR_OK;
694 }
695
696 } else {
697 uint16_t verify = 0xffff;
698
699 retval = target_read_memory(target, bpaddr, bplength, 1, breakpoint->orig_instr);
700 if (retval != ERROR_OK)
701 return retval;
702
703 retval = target_write_u16(target, bpaddr, MIPS16_SDBBP(isa_req));
704 if (retval != ERROR_OK)
705 return retval;
706
707 retval = target_read_u16(target, bpaddr, &verify);
708 if (retval != ERROR_OK)
709 return retval;
710
711 if (verify != MIPS16_SDBBP(isa_req)) {
712 LOG_ERROR("Unable to set 16bit breakpoint at address %08" TARGET_PRIxADDR
713 " - check that memory is read/writable", breakpoint->address);
714 return ERROR_OK;
715 }
716 }
717
718 breakpoint->is_set = true;
719 }
720
721 return ERROR_OK;
722 }
723
724 static int mips_m4k_unset_breakpoint(struct target *target,
725 struct breakpoint *breakpoint)
726 {
727 /* get pointers to arch-specific information */
728 struct mips32_common *mips32 = target_to_mips32(target);
729 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
730 struct mips32_comparator *comparator_list = mips32->inst_break_list;
731 int retval;
732
733 if (!breakpoint->is_set) {
734 LOG_WARNING("breakpoint not set");
735 return ERROR_OK;
736 }
737
738 if (breakpoint->type == BKPT_HARD) {
739 int bp_num = breakpoint->number;
740 if (bp_num >= mips32->num_inst_bpoints) {
741 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")",
742 breakpoint->unique_id);
743 return ERROR_OK;
744 }
745 LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d",
746 breakpoint->unique_id,
747 bp_num);
748 comparator_list[bp_num].used = 0;
749 comparator_list[bp_num].bp_value = 0;
750 target_write_u32(target, comparator_list[bp_num].reg_address +
751 ejtag_info->ejtag_ibc_offs, 0);
752
753 } else {
754 /* restore original instruction (kept in target endianness) */
755 uint32_t isa_req = breakpoint->length & 1;
756 uint32_t bplength = breakpoint->length & ~1;
757 uint8_t current_instr[4];
758 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
759 if (bplength == 4) {
760 uint32_t sdbbp32_instr = MIPS32_SDBBP(isa_req);
761 if (ejtag_info->endianness && isa_req)
762 sdbbp32_instr = SWAP16(sdbbp32_instr);
763
764 if ((breakpoint->address & 3) == 0) { /* 32bit aligned */
765 /* check that user program has not modified breakpoint instruction */
766 retval = target_read_memory(target, breakpoint->address, 4, 1, current_instr);
767 if (retval != ERROR_OK)
768 return retval;
769 /**
770 * target_read_memory() gets us data in _target_ endianness.
771 * If we want to use this data on the host for comparisons with some macros
772 * we must first transform it to _host_ endianness using target_buffer_get_u16().
773 */
774 if (sdbbp32_instr == target_buffer_get_u32(target, current_instr)) {
775 retval = target_write_memory(target, breakpoint->address, 4, 1,
776 breakpoint->orig_instr);
777 if (retval != ERROR_OK)
778 return retval;
779 }
780 } else { /* 16bit aligned */
781 retval = target_read_memory(target, breakpoint->address, 2, 2, current_instr);
782 if (retval != ERROR_OK)
783 return retval;
784
785 if (sdbbp32_instr == target_buffer_get_u32(target, current_instr)) {
786 retval = target_write_memory(target, breakpoint->address, 2, 2,
787 breakpoint->orig_instr);
788 if (retval != ERROR_OK)
789 return retval;
790 }
791 }
792 } else {
793 /* check that user program has not modified breakpoint instruction */
794 retval = target_read_memory(target, breakpoint->address, 2, 1, current_instr);
795 if (retval != ERROR_OK)
796 return retval;
797
798 if (target_buffer_get_u16(target, current_instr) == MIPS16_SDBBP(isa_req)) {
799 retval = target_write_memory(target, breakpoint->address, 2, 1,
800 breakpoint->orig_instr);
801 if (retval != ERROR_OK)
802 return retval;
803 }
804 }
805 }
806
807 breakpoint->is_set = false;
808
809 return ERROR_OK;
810 }
811
812 static int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
813 {
814 struct mips32_common *mips32 = target_to_mips32(target);
815
816 if ((breakpoint->length > 5 || breakpoint->length < 2) || /* out of range */
817 (breakpoint->length == 4 && (breakpoint->address & 2)) || /* mips32 unaligned */
818 (mips32->isa_imp == MIPS32_ONLY && breakpoint->length != 4) || /* misp32 specific */
819 ((mips32->isa_imp & 1) != (breakpoint->length & 1))) /* isa not implemented */
820 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
821
822 if (breakpoint->type == BKPT_HARD) {
823 if (mips32->num_inst_bpoints_avail < 1) {
824 LOG_INFO("no hardware breakpoint available");
825 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
826 }
827
828 mips32->num_inst_bpoints_avail--;
829 }
830
831 return mips_m4k_set_breakpoint(target, breakpoint);
832 }
833
834 static int mips_m4k_remove_breakpoint(struct target *target,
835 struct breakpoint *breakpoint)
836 {
837 /* get pointers to arch-specific information */
838 struct mips32_common *mips32 = target_to_mips32(target);
839
840 if (target->state != TARGET_HALTED) {
841 LOG_WARNING("target not halted");
842 return ERROR_TARGET_NOT_HALTED;
843 }
844
845 if (breakpoint->is_set)
846 mips_m4k_unset_breakpoint(target, breakpoint);
847
848 if (breakpoint->type == BKPT_HARD)
849 mips32->num_inst_bpoints_avail++;
850
851 return ERROR_OK;
852 }
853
854 static int mips_m4k_set_watchpoint(struct target *target,
855 struct watchpoint *watchpoint)
856 {
857 struct mips32_common *mips32 = target_to_mips32(target);
858 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
859 struct mips32_comparator *comparator_list = mips32->data_break_list;
860 int wp_num = 0;
861 /*
862 * watchpoint enabled, ignore all byte lanes in value register
863 * and exclude both load and store accesses from watchpoint
864 * condition evaluation
865 */
866 int enable = EJTAG_DBCN_NOSB | EJTAG_DBCN_NOLB | EJTAG_DBCN_BE |
867 (0xff << EJTAG_DBCN_BLM_SHIFT);
868
869 if (watchpoint->is_set) {
870 LOG_WARNING("watchpoint already set");
871 return ERROR_OK;
872 }
873
874 while (comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
875 wp_num++;
876 if (wp_num >= mips32->num_data_bpoints) {
877 LOG_ERROR("Can not find free FP Comparator");
878 return ERROR_FAIL;
879 }
880
881 if (watchpoint->length != 4) {
882 LOG_ERROR("Only watchpoints of length 4 are supported");
883 return ERROR_TARGET_UNALIGNED_ACCESS;
884 }
885
886 if (watchpoint->address % 4) {
887 LOG_ERROR("Watchpoints address should be word aligned");
888 return ERROR_TARGET_UNALIGNED_ACCESS;
889 }
890
891 switch (watchpoint->rw) {
892 case WPT_READ:
893 enable &= ~EJTAG_DBCN_NOLB;
894 break;
895 case WPT_WRITE:
896 enable &= ~EJTAG_DBCN_NOSB;
897 break;
898 case WPT_ACCESS:
899 enable &= ~(EJTAG_DBCN_NOLB | EJTAG_DBCN_NOSB);
900 break;
901 default:
902 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
903 }
904
905 watchpoint_set(watchpoint, wp_num);
906 comparator_list[wp_num].used = 1;
907 comparator_list[wp_num].bp_value = watchpoint->address;
908
909 /* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved.
910 * There is as well no ASID register support. */
911 if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
912 comparator_list[wp_num].bp_value &= 0xFFFFFFF8;
913 else
914 target_write_u32(target, comparator_list[wp_num].reg_address +
915 ejtag_info->ejtag_dbasid_offs, 0x00000000);
916
917 target_write_u32(target, comparator_list[wp_num].reg_address,
918 comparator_list[wp_num].bp_value);
919 target_write_u32(target, comparator_list[wp_num].reg_address +
920 ejtag_info->ejtag_dbm_offs, 0x00000000);
921
922 target_write_u32(target, comparator_list[wp_num].reg_address +
923 ejtag_info->ejtag_dbc_offs, enable);
924 /* TODO: probably this value is ignored on 2.0 */
925 target_write_u32(target, comparator_list[wp_num].reg_address +
926 ejtag_info->ejtag_dbv_offs, 0);
927 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
928
929 return ERROR_OK;
930 }
931
932 static int mips_m4k_unset_watchpoint(struct target *target,
933 struct watchpoint *watchpoint)
934 {
935 /* get pointers to arch-specific information */
936 struct mips32_common *mips32 = target_to_mips32(target);
937 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
938 struct mips32_comparator *comparator_list = mips32->data_break_list;
939
940 if (!watchpoint->is_set) {
941 LOG_WARNING("watchpoint not set");
942 return ERROR_OK;
943 }
944
945 int wp_num = watchpoint->number;
946 if (wp_num >= mips32->num_data_bpoints) {
947 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
948 return ERROR_OK;
949 }
950 comparator_list[wp_num].used = 0;
951 comparator_list[wp_num].bp_value = 0;
952 target_write_u32(target, comparator_list[wp_num].reg_address +
953 ejtag_info->ejtag_dbc_offs, 0);
954 watchpoint->is_set = false;
955
956 return ERROR_OK;
957 }
958
959 static int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
960 {
961 struct mips32_common *mips32 = target_to_mips32(target);
962
963 if (mips32->num_data_bpoints_avail < 1) {
964 LOG_INFO("no hardware watchpoints available");
965 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
966 }
967
968 mips32->num_data_bpoints_avail--;
969
970 mips_m4k_set_watchpoint(target, watchpoint);
971 return ERROR_OK;
972 }
973
974 static int mips_m4k_remove_watchpoint(struct target *target,
975 struct watchpoint *watchpoint)
976 {
977 /* get pointers to arch-specific information */
978 struct mips32_common *mips32 = target_to_mips32(target);
979
980 if (target->state != TARGET_HALTED) {
981 LOG_WARNING("target not halted");
982 return ERROR_TARGET_NOT_HALTED;
983 }
984
985 if (watchpoint->is_set)
986 mips_m4k_unset_watchpoint(target, watchpoint);
987
988 mips32->num_data_bpoints_avail++;
989
990 return ERROR_OK;
991 }
992
993 static void mips_m4k_enable_watchpoints(struct target *target)
994 {
995 struct watchpoint *watchpoint = target->watchpoints;
996
997 /* set any pending watchpoints */
998 while (watchpoint) {
999 if (!watchpoint->is_set)
1000 mips_m4k_set_watchpoint(target, watchpoint);
1001 watchpoint = watchpoint->next;
1002 }
1003 }
1004
1005 static int mips_m4k_read_memory(struct target *target, target_addr_t address,
1006 uint32_t size, uint32_t count, uint8_t *buffer)
1007 {
1008 struct mips32_common *mips32 = target_to_mips32(target);
1009 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1010
1011 LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
1012 address, size, count);
1013
1014 if (target->state != TARGET_HALTED) {
1015 LOG_WARNING("target not halted");
1016 return ERROR_TARGET_NOT_HALTED;
1017 }
1018
1019 /* sanitize arguments */
1020 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1021 return ERROR_COMMAND_SYNTAX_ERROR;
1022
1023 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1024 return ERROR_TARGET_UNALIGNED_ACCESS;
1025
1026 if (size == 4 && count > 32) {
1027 int retval = mips_m4k_bulk_read_memory(target, address, count, buffer);
1028 if (retval == ERROR_OK)
1029 return ERROR_OK;
1030 LOG_WARNING("Falling back to non-bulk read");
1031 }
1032 /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */
1033 void *t = NULL;
1034
1035 if (size > 1) {
1036 t = malloc(count * size * sizeof(uint8_t));
1037 if (!t) {
1038 LOG_ERROR("Out of memory");
1039 return ERROR_FAIL;
1040 }
1041 } else
1042 t = buffer;
1043
1044 /* if noDMA off, use DMAACC mode for memory read */
1045 int retval;
1046 if (ejtag_info->impcode & EJTAG_IMP_NODMA)
1047 retval = mips32_pracc_read_mem(ejtag_info, address, size, count, t);
1048 else
1049 retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, t);
1050
1051 /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
1052 /* endianness, but byte array should represent target endianness */
1053 if (retval == ERROR_OK) {
1054 switch (size) {
1055 case 4:
1056 target_buffer_set_u32_array(target, buffer, count, t);
1057 break;
1058 case 2:
1059 target_buffer_set_u16_array(target, buffer, count, t);
1060 break;
1061 }
1062 }
1063
1064 if (size > 1)
1065 free(t);
1066
1067 return retval;
1068 }
1069
1070 static int mips_m4k_write_memory(struct target *target, target_addr_t address,
1071 uint32_t size, uint32_t count, const uint8_t *buffer)
1072 {
1073 struct mips32_common *mips32 = target_to_mips32(target);
1074 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1075
1076 LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
1077 address, size, count);
1078
1079 if (target->state != TARGET_HALTED) {
1080 LOG_WARNING("target not halted");
1081 return ERROR_TARGET_NOT_HALTED;
1082 }
1083
1084 if (size == 4 && count > 32) {
1085 int retval = mips_m4k_bulk_write_memory(target, address, count, buffer);
1086 if (retval == ERROR_OK)
1087 return ERROR_OK;
1088 LOG_WARNING("Falling back to non-bulk write");
1089 }
1090
1091 /* sanitize arguments */
1092 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1093 return ERROR_COMMAND_SYNTAX_ERROR;
1094
1095 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1096 return ERROR_TARGET_UNALIGNED_ACCESS;
1097
1098 /** correct endianness if we have word or hword access */
1099 void *t = NULL;
1100 if (size > 1) {
1101 /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
1102 /* endianness, but byte array represents target endianness */
1103 t = malloc(count * size * sizeof(uint8_t));
1104 if (!t) {
1105 LOG_ERROR("Out of memory");
1106 return ERROR_FAIL;
1107 }
1108
1109 switch (size) {
1110 case 4:
1111 target_buffer_get_u32_array(target, buffer, count, (uint32_t *)t);
1112 break;
1113 case 2:
1114 target_buffer_get_u16_array(target, buffer, count, (uint16_t *)t);
1115 break;
1116 }
1117 buffer = t;
1118 }
1119
1120 /* if noDMA off, use DMAACC mode for memory write */
1121 int retval;
1122 if (ejtag_info->impcode & EJTAG_IMP_NODMA)
1123 retval = mips32_pracc_write_mem(ejtag_info, address, size, count, buffer);
1124 else
1125 retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, buffer);
1126
1127 free(t);
1128
1129 if (retval != ERROR_OK)
1130 return retval;
1131
1132 return ERROR_OK;
1133 }
1134
1135 static int mips_m4k_init_target(struct command_context *cmd_ctx,
1136 struct target *target)
1137 {
1138 mips32_build_reg_cache(target);
1139
1140 return ERROR_OK;
1141 }
1142
1143 static int mips_m4k_init_arch_info(struct target *target,
1144 struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)
1145 {
1146 struct mips32_common *mips32 = &mips_m4k->mips32;
1147
1148 mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
1149
1150 /* initialize mips4k specific info */
1151 mips32_init_arch_info(target, mips32, tap);
1152 mips32->arch_info = mips_m4k;
1153
1154 return ERROR_OK;
1155 }
1156
1157 static int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
1158 {
1159 struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
1160
1161 mips_m4k_init_arch_info(target, mips_m4k, target->tap);
1162
1163 return ERROR_OK;
1164 }
1165
1166 static int mips_m4k_examine(struct target *target)
1167 {
1168 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1169 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1170
1171 if (!target_was_examined(target)) {
1172 int retval = mips_ejtag_get_idcode(ejtag_info);
1173 if (retval != ERROR_OK) {
1174 LOG_ERROR("idcode read failed");
1175 return retval;
1176 }
1177 if (((ejtag_info->idcode >> 1) & 0x7FF) == 0x29) {
1178 /* we are using a pic32mx so select ejtag port
1179 * as it is not selected by default */
1180 mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
1181 LOG_DEBUG("PIC32 Detected - using EJTAG Interface");
1182 mips_m4k->is_pic32mx = true;
1183 }
1184 }
1185
1186 /* init rest of ejtag interface */
1187 int retval = mips_ejtag_init(ejtag_info);
1188 if (retval != ERROR_OK)
1189 return retval;
1190
1191 return mips32_examine(target);
1192 }
1193
1194 static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t address,
1195 uint32_t count, const uint8_t *buffer)
1196 {
1197 struct mips32_common *mips32 = target_to_mips32(target);
1198 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1199 struct working_area *fast_data_area;
1200 int retval;
1201 int write_t = 1;
1202
1203 LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
1204 address, count);
1205
1206 /* check alignment */
1207 if (address & 0x3u)
1208 return ERROR_TARGET_UNALIGNED_ACCESS;
1209
1210 if (!mips32->fast_data_area) {
1211 /* Get memory for block write handler
1212 * we preserve this area between calls and gain a speed increase
1213 * of about 3kb/sec when writing flash
1214 * this will be released/nulled by the system when the target is resumed or reset */
1215 retval = target_alloc_working_area(target,
1216 MIPS32_FASTDATA_HANDLER_SIZE,
1217 &mips32->fast_data_area);
1218 if (retval != ERROR_OK) {
1219 LOG_ERROR("No working area available");
1220 return retval;
1221 }
1222
1223 /* reset fastadata state so the algo get reloaded */
1224 ejtag_info->fast_access_save = -1;
1225 }
1226
1227 fast_data_area = mips32->fast_data_area;
1228
1229 if (address < (fast_data_area->address + fast_data_area->size) &&
1230 fast_data_area->address < (address + count)) {
1231 LOG_ERROR("fast_data (" TARGET_ADDR_FMT ") is within write area "
1232 "(" TARGET_ADDR_FMT "-" TARGET_ADDR_FMT ").",
1233 fast_data_area->address, address, address + count);
1234 LOG_ERROR("Change work-area-phys or load_image address!");
1235 return ERROR_FAIL;
1236 }
1237
1238 /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1239 /* but byte array represents target endianness */
1240 uint32_t *t = NULL;
1241 t = malloc(count * sizeof(uint32_t));
1242 if (!t) {
1243 LOG_ERROR("Out of memory");
1244 return ERROR_FAIL;
1245 }
1246
1247 target_buffer_get_u32_array(target, buffer, count, t);
1248
1249 retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
1250 count, t);
1251
1252 free(t);
1253
1254 if (retval != ERROR_OK)
1255 LOG_ERROR("Fastdata access Failed");
1256
1257 return retval;
1258 }
1259
1260 static int mips_m4k_bulk_read_memory(struct target *target, target_addr_t address,
1261 uint32_t count, uint8_t *buffer)
1262 {
1263 struct mips32_common *mips32 = target_to_mips32(target);
1264 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1265 struct working_area *fast_data_area;
1266 int retval;
1267 int write_t = 0;
1268
1269 LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
1270 address, count);
1271
1272 /* check alignment */
1273 if (address & 0x3u)
1274 return ERROR_TARGET_UNALIGNED_ACCESS;
1275
1276 if (!mips32->fast_data_area) {
1277 /* Get memory for block read handler
1278 * we preserve this area between calls and gain a speed increase
1279 * of about 3kb/sec when reading flash
1280 * this will be released/nulled by the system when the target is resumed or reset */
1281 retval = target_alloc_working_area(target,
1282 MIPS32_FASTDATA_HANDLER_SIZE,
1283 &mips32->fast_data_area);
1284 if (retval != ERROR_OK) {
1285 LOG_ERROR("No working area available");
1286 return retval;
1287 }
1288
1289 /* reset fastadata state so the algo get reloaded */
1290 ejtag_info->fast_access_save = -1;
1291 }
1292
1293 fast_data_area = mips32->fast_data_area;
1294
1295 if (address < (fast_data_area->address + fast_data_area->size) &&
1296 fast_data_area->address < (address + count)) {
1297 LOG_ERROR("fast_data (" TARGET_ADDR_FMT ") is within read area "
1298 "(" TARGET_ADDR_FMT "-" TARGET_ADDR_FMT ").",
1299 fast_data_area->address, address, address + count);
1300 LOG_ERROR("Change work-area-phys or load_image address!");
1301 return ERROR_FAIL;
1302 }
1303
1304 /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1305 /* but byte array represents target endianness */
1306 uint32_t *t = malloc(count * sizeof(uint32_t));
1307 if (!t) {
1308 LOG_ERROR("Out of memory");
1309 return ERROR_FAIL;
1310 }
1311
1312 retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
1313 count, t);
1314
1315 target_buffer_set_u32_array(target, buffer, count, t);
1316
1317 free(t);
1318
1319 if (retval != ERROR_OK)
1320 LOG_ERROR("Fastdata access Failed");
1321
1322 return retval;
1323 }
1324
1325 static int mips_m4k_verify_pointer(struct command_invocation *cmd,
1326 struct mips_m4k_common *mips_m4k)
1327 {
1328 if (mips_m4k->common_magic != MIPSM4K_COMMON_MAGIC) {
1329 command_print(cmd, "target is not an MIPS_M4K");
1330 return ERROR_TARGET_INVALID;
1331 }
1332 return ERROR_OK;
1333 }
1334
1335 COMMAND_HANDLER(mips_m4k_handle_cp0_command)
1336 {
1337 int retval;
1338 struct target *target = get_current_target(CMD_CTX);
1339 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1340 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1341
1342 retval = mips_m4k_verify_pointer(CMD, mips_m4k);
1343 if (retval != ERROR_OK)
1344 return retval;
1345
1346 if (target->state != TARGET_HALTED) {
1347 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
1348 return ERROR_OK;
1349 }
1350
1351 /* two or more argument, access a single register/select (write if third argument is given) */
1352 if (CMD_ARGC < 2)
1353 return ERROR_COMMAND_SYNTAX_ERROR;
1354 else {
1355 uint32_t cp0_reg, cp0_sel;
1356 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
1357 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
1358
1359 if (CMD_ARGC == 2) {
1360 uint32_t value;
1361 retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
1362 if (retval != ERROR_OK) {
1363 command_print(CMD,
1364 "couldn't access reg %" PRIu32,
1365 cp0_reg);
1366 return ERROR_OK;
1367 }
1368 command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
1369 cp0_reg, cp0_sel, value);
1370
1371 } else if (CMD_ARGC == 3) {
1372 uint32_t value;
1373 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1374 retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
1375 if (retval != ERROR_OK) {
1376 command_print(CMD,
1377 "couldn't access cp0 reg %" PRIu32 ", select %" PRIu32,
1378 cp0_reg, cp0_sel);
1379 return ERROR_OK;
1380 }
1381 command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
1382 cp0_reg, cp0_sel, value);
1383 }
1384 }
1385
1386 return ERROR_OK;
1387 }
1388
1389 COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
1390 {
1391 struct target *target = get_current_target(CMD_CTX);
1392 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1393 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1394
1395 if (CMD_ARGC == 1)
1396 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
1397 else if (CMD_ARGC > 1)
1398 return ERROR_COMMAND_SYNTAX_ERROR;
1399
1400 command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay);
1401 if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {
1402 ejtag_info->mode = 0;
1403 command_print(CMD, "running in legacy mode");
1404 } else {
1405 ejtag_info->mode = 1;
1406 command_print(CMD, "running in fast queued mode");
1407 }
1408
1409 return ERROR_OK;
1410 }
1411
1412 static const struct command_registration mips_m4k_exec_command_handlers[] = {
1413 {
1414 .name = "cp0",
1415 .handler = mips_m4k_handle_cp0_command,
1416 .mode = COMMAND_EXEC,
1417 .usage = "regnum [value]",
1418 .help = "display/modify cp0 register",
1419 },
1420 {
1421 .name = "scan_delay",
1422 .handler = mips_m4k_handle_scan_delay_command,
1423 .mode = COMMAND_ANY,
1424 .help = "display/set scan delay in nano seconds",
1425 .usage = "[value]",
1426 },
1427 {
1428 .chain = smp_command_handlers,
1429 },
1430 COMMAND_REGISTRATION_DONE
1431 };
1432
1433 static const struct command_registration mips_m4k_command_handlers[] = {
1434 {
1435 .chain = mips32_command_handlers,
1436 },
1437 {
1438 .name = "mips_m4k",
1439 .mode = COMMAND_ANY,
1440 .help = "mips_m4k command group",
1441 .usage = "",
1442 .chain = mips_m4k_exec_command_handlers,
1443 },
1444 COMMAND_REGISTRATION_DONE
1445 };
1446
1447 struct target_type mips_m4k_target = {
1448 .name = "mips_m4k",
1449
1450 .poll = mips_m4k_poll,
1451 .arch_state = mips32_arch_state,
1452
1453 .halt = mips_m4k_halt,
1454 .resume = mips_m4k_resume,
1455 .step = mips_m4k_step,
1456
1457 .assert_reset = mips_m4k_assert_reset,
1458 .deassert_reset = mips_m4k_deassert_reset,
1459
1460 .get_gdb_reg_list = mips32_get_gdb_reg_list,
1461
1462 .read_memory = mips_m4k_read_memory,
1463 .write_memory = mips_m4k_write_memory,
1464 .checksum_memory = mips32_checksum_memory,
1465 .blank_check_memory = mips32_blank_check_memory,
1466
1467 .run_algorithm = mips32_run_algorithm,
1468
1469 .add_breakpoint = mips_m4k_add_breakpoint,
1470 .remove_breakpoint = mips_m4k_remove_breakpoint,
1471 .add_watchpoint = mips_m4k_add_watchpoint,
1472 .remove_watchpoint = mips_m4k_remove_watchpoint,
1473
1474 .commands = mips_m4k_command_handlers,
1475 .target_create = mips_m4k_target_create,
1476 .init_target = mips_m4k_init_target,
1477 .examine = mips_m4k_examine,
1478 };
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