src/target/mips_cpu.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 #ifndef OPENOCD_TARGET_MIPS_CPU_H
   3 #define OPENOCD_TARGET_MIPS_CPU_H
   4
   5 /*
   6  * NOTE: The proper detection of certain CPUs can become quite complicated.
   7  * Please consult the following Linux kernel code when adding new CPUs:
   8  *  arch/mips/include/asm/cpu.h
   9  *  arch/mips/kernel/cpu-probe.c
  10  */
  11
  12 /* Assigned Company values for bits 23:16 of the PRId register. */
  13 #define PRID_COMP_MASK          0xff0000
  14
  15 #define PRID_COMP_LEGACY    0x000000
  16 #define PRID_COMP_MTI       0x010000
  17 #define PRID_COMP_BROADCOM  0x020000
  18 #define PRID_COMP_ALCHEMY   0x030000
  19 #define PRID_COMP_LEXRA     0x0b0000
  20 #define PRID_COMP_ALTERA    0x100000
  21 #define PRID_COMP_INGENIC_E1    0xe10000
  22
  23 /*
  24  * Assigned Processor ID (implementation) values for bits 15:8 of the PRId
  25  * register. In order to detect a certain CPU type exactly eventually additional
  26  * registers may need to be examined.
  27  */
  28 #define PRID_IMP_MASK           0xff00
  29
  30 #define PRID_IMP_MAPTIV_UC      0x9D00
  31 #define PRID_IMP_MAPTIV_UP      0x9E00
  32 #define PRID_IMP_IAPTIV_CM      0xA000
  33 #define PRID_IMP_IAPTIV         0xA100
  34 #define PRID_IMP_M5150          0xA700
  35
  36 #define PRID_IMP_XBURST_REV1    0x0200 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
  37
  38 #endif /* OPENOCD_TARGET_MIPS_CPU_H */