Zach Welch <zw@superlucidity.net> fix -Werror warnings
[openocd.git] / src / target / mips32.h
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22
23 #ifndef MIPS32_H
24 #define MIPS32_H
25
26 #include "target.h"
27 #include "register.h"
28 #include "mips_ejtag.h"
29 #include "mips32_pracc.h"
30
31 #define MIPS32_COMMON_MAGIC 0xB320B320
32
33 /* offsets into mips32 core register cache */
34 enum
35 {
36 MIPS32_PC = 37,
37 MIPS32NUMCOREREGS
38 };
39
40 typedef struct mips32_comparator_s
41 {
42 int used;
43 //int type;
44 u32 bp_value;
45 u32 reg_address;
46 } mips32_comparator_t;
47
48 typedef struct mips32_common_s
49 {
50 u32 common_magic;
51 void *arch_info;
52 reg_cache_t *core_cache;
53 mips_ejtag_t ejtag_info;
54 u32 core_regs[MIPS32NUMCOREREGS];
55
56 int bp_scanned;
57 int num_inst_bpoints;
58 int num_data_bpoints;
59 int num_inst_bpoints_avail;
60 int num_data_bpoints_avail;
61 mips32_comparator_t *inst_break_list;
62 mips32_comparator_t *data_break_list;
63
64 /* register cache to processor synchronization */
65 int (*read_core_reg)(struct target_s *target, int num);
66 int (*write_core_reg)(struct target_s *target, int num);
67 } mips32_common_t;
68
69 typedef struct mips32_core_reg_s
70 {
71 u32 num;
72 target_t *target;
73 mips32_common_t *mips32_common;
74 } mips32_core_reg_t;
75
76 #define MIPS32_OP_BEQ 0x04
77 #define MIPS32_OP_ADDI 0x08
78 #define MIPS32_OP_AND 0x24
79 #define MIPS32_OP_COP0 0x10
80 #define MIPS32_OP_LUI 0x0F
81 #define MIPS32_OP_LW 0x23
82 #define MIPS32_OP_LBU 0x24
83 #define MIPS32_OP_LHU 0x25
84 #define MIPS32_OP_MFHI 0x10
85 #define MIPS32_OP_MTHI 0x11
86 #define MIPS32_OP_MFLO 0x12
87 #define MIPS32_OP_MTLO 0x13
88 #define MIPS32_OP_SB 0x28
89 #define MIPS32_OP_SH 0x29
90 #define MIPS32_OP_SW 0x2B
91 #define MIPS32_OP_ORI 0x0D
92
93 #define MIPS32_COP0_MF 0x00
94 #define MIPS32_COP0_MT 0x04
95
96 #define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) (((opcode)<<26) |((rs)<<21)|((rt)<<16)|((rd)<<11)| ((shamt)<<5) | (funct))
97 #define MIPS32_I_INST(opcode, rs, rt, immd) (((opcode)<<26) |((rs)<<21)|((rt)<<16)|(immd))
98 #define MIPS32_J_INST(opcode, addr) (((opcode)<<26) |(addr))
99
100 #define MIPS32_NOP 0
101 #define MIPS32_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
102 #define MIPS32_AND(reg, off, val) MIPS32_R_INST(0, off, val, reg, 0, MIPS32_OP_AND)
103 #define MIPS32_B(off) MIPS32_BEQ(0, 0, off)
104 #define MIPS32_BEQ(src,tar,off) MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
105 #define MIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
106 #define MIPS32_MTC0(gpr,cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
107 #define MIPS32_LBU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
108 #define MIPS32_LHU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off)
109 #define MIPS32_LUI(reg, val) MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)
110 #define MIPS32_LW(reg, off, base) MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
111 #define MIPS32_MFLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
112 #define MIPS32_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
113 #define MIPS32_MTLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MTLO)
114 #define MIPS32_MTHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MTHI)
115 #define MIPS32_ORI(src, tar, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
116 #define MIPS32_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
117 #define MIPS32_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
118 #define MIPS32_SW(reg, off, base) MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)
119
120 /* ejtag specific instructions */
121 #define MIPS32_DRET 0x4200001F
122 #define MIPS32_SDBBP 0x7000003F
123 #define MIPS16_SDBBP 0xE801
124
125 extern int mips32_arch_state(struct target_s *target);
126 extern int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap);
127 extern int mips32_restore_context(target_t *target);
128 extern int mips32_save_context(target_t *target);
129 extern reg_cache_t *mips32_build_reg_cache(target_t *target);
130 extern int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
131 extern int mips32_configure_break_unit(struct target_s *target);
132 extern int mips32_examine(struct target_s *target);
133
134 extern int mips32_register_commands(struct command_context_s *cmd_ctx);
135 extern int mips32_invalidate_core_regs(target_t *target);
136 extern int mips32_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
137
138 #endif /*MIPS32_H*/