1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2007,2008 Øyvind Harboe *
8 * oyvind.harboe@zylin.com *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ***************************************************************************/
33 char* mips32_core_reg_list
[] =
35 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
36 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
37 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
38 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
39 "status", "lo", "hi", "badvaddr", "cause", "pc"
42 struct mips32_core_reg mips32_core_reg_list_arch_info
[MIPS32NUMCOREREGS
] =
85 /* number of mips dummy fp regs fp0 - fp31 + fsr and fir
86 * we also add 18 unknown registers to handle gdb requests */
88 #define MIPS32NUMFPREGS 34 + 18
90 uint8_t mips32_gdb_dummy_fp_value
[] = {0, 0, 0, 0};
92 struct reg mips32_gdb_dummy_fp_reg
=
94 .name
= "GDB dummy floating-point register",
95 .value
= mips32_gdb_dummy_fp_value
,
102 int mips32_get_core_reg(struct reg
*reg
)
105 struct mips32_core_reg
*mips32_reg
= reg
->arch_info
;
106 struct target
*target
= mips32_reg
->target
;
107 struct mips32_common
*mips32_target
= target
->arch_info
;
109 if (target
->state
!= TARGET_HALTED
)
111 return ERROR_TARGET_NOT_HALTED
;
114 retval
= mips32_target
->read_core_reg(target
, mips32_reg
->num
);
119 int mips32_set_core_reg(struct reg
*reg
, uint8_t *buf
)
121 struct mips32_core_reg
*mips32_reg
= reg
->arch_info
;
122 struct target
*target
= mips32_reg
->target
;
123 uint32_t value
= buf_get_u32(buf
, 0, 32);
125 if (target
->state
!= TARGET_HALTED
)
127 return ERROR_TARGET_NOT_HALTED
;
130 buf_set_u32(reg
->value
, 0, 32, value
);
137 int mips32_read_core_reg(struct target
*target
, int num
)
140 struct mips32_core_reg
*mips_core_reg
;
142 /* get pointers to arch-specific information */
143 struct mips32_common
*mips32
= target
->arch_info
;
145 if ((num
< 0) || (num
>= MIPS32NUMCOREREGS
))
146 return ERROR_INVALID_ARGUMENTS
;
148 mips_core_reg
= mips32
->core_cache
->reg_list
[num
].arch_info
;
149 reg_value
= mips32
->core_regs
[num
];
150 buf_set_u32(mips32
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
151 mips32
->core_cache
->reg_list
[num
].valid
= 1;
152 mips32
->core_cache
->reg_list
[num
].dirty
= 0;
157 int mips32_write_core_reg(struct target
*target
, int num
)
160 struct mips32_core_reg
*mips_core_reg
;
162 /* get pointers to arch-specific information */
163 struct mips32_common
*mips32
= target
->arch_info
;
165 if ((num
< 0) || (num
>= MIPS32NUMCOREREGS
))
166 return ERROR_INVALID_ARGUMENTS
;
168 reg_value
= buf_get_u32(mips32
->core_cache
->reg_list
[num
].value
, 0, 32);
169 mips_core_reg
= mips32
->core_cache
->reg_list
[num
].arch_info
;
170 mips32
->core_regs
[num
] = reg_value
;
171 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", num
, reg_value
);
172 mips32
->core_cache
->reg_list
[num
].valid
= 1;
173 mips32
->core_cache
->reg_list
[num
].dirty
= 0;
178 int mips32_invalidate_core_regs(struct target
*target
)
180 /* get pointers to arch-specific information */
181 struct mips32_common
*mips32
= target
->arch_info
;
184 for (i
= 0; i
< mips32
->core_cache
->num_regs
; i
++)
186 mips32
->core_cache
->reg_list
[i
].valid
= 0;
187 mips32
->core_cache
->reg_list
[i
].dirty
= 0;
193 int mips32_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[], int *reg_list_size
)
195 /* get pointers to arch-specific information */
196 struct mips32_common
*mips32
= target
->arch_info
;
199 /* include floating point registers */
200 *reg_list_size
= MIPS32NUMCOREREGS
+ MIPS32NUMFPREGS
;
201 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
203 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
205 (*reg_list
)[i
] = &mips32
->core_cache
->reg_list
[i
];
208 /* add dummy floating points regs */
209 for (i
= MIPS32NUMCOREREGS
; i
< (MIPS32NUMCOREREGS
+ MIPS32NUMFPREGS
); i
++)
211 (*reg_list
)[i
] = &mips32_gdb_dummy_fp_reg
;
217 int mips32_save_context(struct target
*target
)
221 /* get pointers to arch-specific information */
222 struct mips32_common
*mips32
= target
->arch_info
;
223 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
225 /* read core registers */
226 mips32_pracc_read_regs(ejtag_info
, mips32
->core_regs
);
228 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
230 if (!mips32
->core_cache
->reg_list
[i
].valid
)
232 mips32
->read_core_reg(target
, i
);
239 int mips32_restore_context(struct target
*target
)
243 /* get pointers to arch-specific information */
244 struct mips32_common
*mips32
= target
->arch_info
;
245 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
247 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
249 if (mips32
->core_cache
->reg_list
[i
].dirty
)
251 mips32
->write_core_reg(target
, i
);
255 /* write core regs */
256 mips32_pracc_write_regs(ejtag_info
, mips32
->core_regs
);
261 int mips32_arch_state(struct target
*target
)
263 struct mips32_common
*mips32
= target
->arch_info
;
265 if (mips32
->common_magic
!= MIPS32_COMMON_MAGIC
)
267 LOG_ERROR("BUG: called for a non-MIPS32 target");
271 LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32
"",
272 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
273 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32));
278 static const struct reg_arch_type mips32_reg_type
= {
279 .get
= mips32_get_core_reg
,
280 .set
= mips32_set_core_reg
,
283 struct reg_cache
*mips32_build_reg_cache(struct target
*target
)
285 /* get pointers to arch-specific information */
286 struct mips32_common
*mips32
= target
->arch_info
;
288 int num_regs
= MIPS32NUMCOREREGS
;
289 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
290 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
291 struct reg
*reg_list
= malloc(sizeof(struct reg
) * num_regs
);
292 struct mips32_core_reg
*arch_info
= malloc(sizeof(struct mips32_core_reg
) * num_regs
);
295 register_init_dummy(&mips32_gdb_dummy_fp_reg
);
297 /* Build the process context cache */
298 cache
->name
= "mips32 registers";
300 cache
->reg_list
= reg_list
;
301 cache
->num_regs
= num_regs
;
303 mips32
->core_cache
= cache
;
305 for (i
= 0; i
< num_regs
; i
++)
307 arch_info
[i
] = mips32_core_reg_list_arch_info
[i
];
308 arch_info
[i
].target
= target
;
309 arch_info
[i
].mips32_common
= mips32
;
310 reg_list
[i
].name
= mips32_core_reg_list
[i
];
311 reg_list
[i
].size
= 32;
312 reg_list
[i
].value
= calloc(1, 4);
313 reg_list
[i
].dirty
= 0;
314 reg_list
[i
].valid
= 0;
315 reg_list
[i
].type
= &mips32_reg_type
;
316 reg_list
[i
].arch_info
= &arch_info
[i
];
322 int mips32_init_arch_info(struct target
*target
, struct mips32_common
*mips32
, struct jtag_tap
*tap
)
324 target
->arch_info
= mips32
;
325 mips32
->common_magic
= MIPS32_COMMON_MAGIC
;
327 /* has breakpoint/watchpint unit been scanned */
328 mips32
->bp_scanned
= 0;
329 mips32
->data_break_list
= NULL
;
331 mips32
->ejtag_info
.tap
= tap
;
332 mips32
->read_core_reg
= mips32_read_core_reg
;
333 mips32
->write_core_reg
= mips32_write_core_reg
;
338 int mips32_register_commands(struct command_context
*cmd_ctx
)
343 int mips32_run_algorithm(struct target
*target
, int num_mem_params
, struct mem_param
*mem_params
, int num_reg_params
, struct reg_param
*reg_params
, uint32_t entry_point
, uint32_t exit_point
, int timeout_ms
, void *arch_info
)
349 int mips32_examine(struct target
*target
)
351 struct mips32_common
*mips32
= target
->arch_info
;
353 if (!target_was_examined(target
))
355 target_set_examined(target
);
357 /* we will configure later */
358 mips32
->bp_scanned
= 0;
359 mips32
->num_inst_bpoints
= 0;
360 mips32
->num_data_bpoints
= 0;
361 mips32
->num_inst_bpoints_avail
= 0;
362 mips32
->num_data_bpoints_avail
= 0;
368 int mips32_configure_break_unit(struct target
*target
)
370 /* get pointers to arch-specific information */
371 struct mips32_common
*mips32
= target
->arch_info
;
373 uint32_t dcr
, bpinfo
;
376 if (mips32
->bp_scanned
)
379 /* get info about breakpoint support */
380 if ((retval
= target_read_u32(target
, EJTAG_DCR
, &dcr
)) != ERROR_OK
)
385 /* get number of inst breakpoints */
386 if ((retval
= target_read_u32(target
, EJTAG_IBS
, &bpinfo
)) != ERROR_OK
)
389 mips32
->num_inst_bpoints
= (bpinfo
>> 24) & 0x0F;
390 mips32
->num_inst_bpoints_avail
= mips32
->num_inst_bpoints
;
391 mips32
->inst_break_list
= calloc(mips32
->num_inst_bpoints
, sizeof(struct mips32_comparator
));
392 for (i
= 0; i
< mips32
->num_inst_bpoints
; i
++)
394 mips32
->inst_break_list
[i
].reg_address
= EJTAG_IBA1
+ (0x100 * i
);
398 if ((retval
= target_write_u32(target
, EJTAG_IBS
, 0)) != ERROR_OK
)
404 /* get number of data breakpoints */
405 if ((retval
= target_read_u32(target
, EJTAG_DBS
, &bpinfo
)) != ERROR_OK
)
408 mips32
->num_data_bpoints
= (bpinfo
>> 24) & 0x0F;
409 mips32
->num_data_bpoints_avail
= mips32
->num_data_bpoints
;
410 mips32
->data_break_list
= calloc(mips32
->num_data_bpoints
, sizeof(struct mips32_comparator
));
411 for (i
= 0; i
< mips32
->num_data_bpoints
; i
++)
413 mips32
->data_break_list
[i
].reg_address
= EJTAG_DBA1
+ (0x100 * i
);
417 if ((retval
= target_write_u32(target
, EJTAG_DBS
, 0)) != ERROR_OK
)
421 LOG_DEBUG("DCR 0x%" PRIx32
" numinst %i numdata %i", dcr
, mips32
->num_inst_bpoints
, mips32
->num_data_bpoints
);
423 mips32
->bp_scanned
= 1;
428 int mips32_enable_interrupts(struct target
*target
, int enable
)
434 /* read debug control register */
435 if ((retval
= target_read_u32(target
, EJTAG_DCR
, &dcr
)) != ERROR_OK
)
440 if (!(dcr
& (1 << 4)))
442 /* enable interrupts */
451 /* disable interrupts */
459 if ((retval
= target_write_u32(target
, EJTAG_DCR
, dcr
)) != ERROR_OK
)
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)