1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2007,2008 Øyvind Harboe *
8 * oyvind.harboe@zylin.com *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ***************************************************************************/
33 char* mips32_core_reg_list
[] =
35 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
36 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
37 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
38 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
39 "status", "lo", "hi", "badvaddr", "cause", "pc"
42 struct mips32_core_reg mips32_core_reg_list_arch_info
[MIPS32NUMCOREREGS
] =
85 /* number of mips dummy fp regs fp0 - fp31 + fsr and fir
86 * we also add 18 unknown registers to handle gdb requests */
88 #define MIPS32NUMFPREGS 34 + 18
90 uint8_t mips32_gdb_dummy_fp_value
[] = {0, 0, 0, 0};
92 struct reg mips32_gdb_dummy_fp_reg
=
94 .name
= "GDB dummy floating-point register",
95 .value
= mips32_gdb_dummy_fp_value
,
102 int mips32_get_core_reg(struct reg
*reg
)
105 struct mips32_core_reg
*mips32_reg
= reg
->arch_info
;
106 struct target
*target
= mips32_reg
->target
;
107 struct mips32_common
*mips32_target
= target
->arch_info
;
109 if (target
->state
!= TARGET_HALTED
)
111 return ERROR_TARGET_NOT_HALTED
;
114 retval
= mips32_target
->read_core_reg(target
, mips32_reg
->num
);
119 int mips32_set_core_reg(struct reg
*reg
, uint8_t *buf
)
121 struct mips32_core_reg
*mips32_reg
= reg
->arch_info
;
122 struct target
*target
= mips32_reg
->target
;
123 uint32_t value
= buf_get_u32(buf
, 0, 32);
125 if (target
->state
!= TARGET_HALTED
)
127 return ERROR_TARGET_NOT_HALTED
;
130 buf_set_u32(reg
->value
, 0, 32, value
);
137 int mips32_read_core_reg(struct target
*target
, int num
)
140 struct mips32_core_reg
*mips_core_reg
;
142 /* get pointers to arch-specific information */
143 struct mips32_common
*mips32
= target
->arch_info
;
145 if ((num
< 0) || (num
>= MIPS32NUMCOREREGS
))
146 return ERROR_INVALID_ARGUMENTS
;
148 mips_core_reg
= mips32
->core_cache
->reg_list
[num
].arch_info
;
149 reg_value
= mips32
->core_regs
[num
];
150 buf_set_u32(mips32
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
151 mips32
->core_cache
->reg_list
[num
].valid
= 1;
152 mips32
->core_cache
->reg_list
[num
].dirty
= 0;
157 int mips32_write_core_reg(struct target
*target
, int num
)
160 struct mips32_core_reg
*mips_core_reg
;
162 /* get pointers to arch-specific information */
163 struct mips32_common
*mips32
= target
->arch_info
;
165 if ((num
< 0) || (num
>= MIPS32NUMCOREREGS
))
166 return ERROR_INVALID_ARGUMENTS
;
168 reg_value
= buf_get_u32(mips32
->core_cache
->reg_list
[num
].value
, 0, 32);
169 mips_core_reg
= mips32
->core_cache
->reg_list
[num
].arch_info
;
170 mips32
->core_regs
[num
] = reg_value
;
171 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", num
, reg_value
);
172 mips32
->core_cache
->reg_list
[num
].valid
= 1;
173 mips32
->core_cache
->reg_list
[num
].dirty
= 0;
178 int mips32_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[], int *reg_list_size
)
180 /* get pointers to arch-specific information */
181 struct mips32_common
*mips32
= target
->arch_info
;
184 /* include floating point registers */
185 *reg_list_size
= MIPS32NUMCOREREGS
+ MIPS32NUMFPREGS
;
186 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
188 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
190 (*reg_list
)[i
] = &mips32
->core_cache
->reg_list
[i
];
193 /* add dummy floating points regs */
194 for (i
= MIPS32NUMCOREREGS
; i
< (MIPS32NUMCOREREGS
+ MIPS32NUMFPREGS
); i
++)
196 (*reg_list
)[i
] = &mips32_gdb_dummy_fp_reg
;
202 int mips32_save_context(struct target
*target
)
206 /* get pointers to arch-specific information */
207 struct mips32_common
*mips32
= target
->arch_info
;
208 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
210 /* read core registers */
211 mips32_pracc_read_regs(ejtag_info
, mips32
->core_regs
);
213 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
215 if (!mips32
->core_cache
->reg_list
[i
].valid
)
217 mips32
->read_core_reg(target
, i
);
224 int mips32_restore_context(struct target
*target
)
228 /* get pointers to arch-specific information */
229 struct mips32_common
*mips32
= target
->arch_info
;
230 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
232 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
234 if (mips32
->core_cache
->reg_list
[i
].dirty
)
236 mips32
->write_core_reg(target
, i
);
240 /* write core regs */
241 mips32_pracc_write_regs(ejtag_info
, mips32
->core_regs
);
246 int mips32_arch_state(struct target
*target
)
248 struct mips32_common
*mips32
= target
->arch_info
;
250 if (mips32
->common_magic
!= MIPS32_COMMON_MAGIC
)
252 LOG_ERROR("BUG: called for a non-MIPS32 target");
256 LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32
"",
257 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
258 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32));
263 static const struct reg_arch_type mips32_reg_type
= {
264 .get
= mips32_get_core_reg
,
265 .set
= mips32_set_core_reg
,
268 struct reg_cache
*mips32_build_reg_cache(struct target
*target
)
270 /* get pointers to arch-specific information */
271 struct mips32_common
*mips32
= target
->arch_info
;
273 int num_regs
= MIPS32NUMCOREREGS
;
274 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
275 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
276 struct reg
*reg_list
= malloc(sizeof(struct reg
) * num_regs
);
277 struct mips32_core_reg
*arch_info
= malloc(sizeof(struct mips32_core_reg
) * num_regs
);
280 register_init_dummy(&mips32_gdb_dummy_fp_reg
);
282 /* Build the process context cache */
283 cache
->name
= "mips32 registers";
285 cache
->reg_list
= reg_list
;
286 cache
->num_regs
= num_regs
;
288 mips32
->core_cache
= cache
;
290 for (i
= 0; i
< num_regs
; i
++)
292 arch_info
[i
] = mips32_core_reg_list_arch_info
[i
];
293 arch_info
[i
].target
= target
;
294 arch_info
[i
].mips32_common
= mips32
;
295 reg_list
[i
].name
= mips32_core_reg_list
[i
];
296 reg_list
[i
].size
= 32;
297 reg_list
[i
].value
= calloc(1, 4);
298 reg_list
[i
].dirty
= 0;
299 reg_list
[i
].valid
= 0;
300 reg_list
[i
].type
= &mips32_reg_type
;
301 reg_list
[i
].arch_info
= &arch_info
[i
];
307 int mips32_init_arch_info(struct target
*target
, struct mips32_common
*mips32
, struct jtag_tap
*tap
)
309 target
->arch_info
= mips32
;
310 mips32
->common_magic
= MIPS32_COMMON_MAGIC
;
312 /* has breakpoint/watchpint unit been scanned */
313 mips32
->bp_scanned
= 0;
314 mips32
->data_break_list
= NULL
;
316 mips32
->ejtag_info
.tap
= tap
;
317 mips32
->read_core_reg
= mips32_read_core_reg
;
318 mips32
->write_core_reg
= mips32_write_core_reg
;
323 int mips32_run_algorithm(struct target
*target
, int num_mem_params
, struct mem_param
*mem_params
, int num_reg_params
, struct reg_param
*reg_params
, uint32_t entry_point
, uint32_t exit_point
, int timeout_ms
, void *arch_info
)
329 int mips32_examine(struct target
*target
)
331 struct mips32_common
*mips32
= target
->arch_info
;
333 if (!target_was_examined(target
))
335 target_set_examined(target
);
337 /* we will configure later */
338 mips32
->bp_scanned
= 0;
339 mips32
->num_inst_bpoints
= 0;
340 mips32
->num_data_bpoints
= 0;
341 mips32
->num_inst_bpoints_avail
= 0;
342 mips32
->num_data_bpoints_avail
= 0;
348 int mips32_configure_break_unit(struct target
*target
)
350 /* get pointers to arch-specific information */
351 struct mips32_common
*mips32
= target
->arch_info
;
353 uint32_t dcr
, bpinfo
;
356 if (mips32
->bp_scanned
)
359 /* get info about breakpoint support */
360 if ((retval
= target_read_u32(target
, EJTAG_DCR
, &dcr
)) != ERROR_OK
)
365 /* get number of inst breakpoints */
366 if ((retval
= target_read_u32(target
, EJTAG_IBS
, &bpinfo
)) != ERROR_OK
)
369 mips32
->num_inst_bpoints
= (bpinfo
>> 24) & 0x0F;
370 mips32
->num_inst_bpoints_avail
= mips32
->num_inst_bpoints
;
371 mips32
->inst_break_list
= calloc(mips32
->num_inst_bpoints
, sizeof(struct mips32_comparator
));
372 for (i
= 0; i
< mips32
->num_inst_bpoints
; i
++)
374 mips32
->inst_break_list
[i
].reg_address
= EJTAG_IBA1
+ (0x100 * i
);
378 if ((retval
= target_write_u32(target
, EJTAG_IBS
, 0)) != ERROR_OK
)
384 /* get number of data breakpoints */
385 if ((retval
= target_read_u32(target
, EJTAG_DBS
, &bpinfo
)) != ERROR_OK
)
388 mips32
->num_data_bpoints
= (bpinfo
>> 24) & 0x0F;
389 mips32
->num_data_bpoints_avail
= mips32
->num_data_bpoints
;
390 mips32
->data_break_list
= calloc(mips32
->num_data_bpoints
, sizeof(struct mips32_comparator
));
391 for (i
= 0; i
< mips32
->num_data_bpoints
; i
++)
393 mips32
->data_break_list
[i
].reg_address
= EJTAG_DBA1
+ (0x100 * i
);
397 if ((retval
= target_write_u32(target
, EJTAG_DBS
, 0)) != ERROR_OK
)
401 LOG_DEBUG("DCR 0x%" PRIx32
" numinst %i numdata %i", dcr
, mips32
->num_inst_bpoints
, mips32
->num_data_bpoints
);
403 mips32
->bp_scanned
= 1;
408 int mips32_enable_interrupts(struct target
*target
, int enable
)
414 /* read debug control register */
415 if ((retval
= target_read_u32(target
, EJTAG_DCR
, &dcr
)) != ERROR_OK
)
420 if (!(dcr
& (1 << 4)))
422 /* enable interrupts */
431 /* disable interrupts */
439 if ((retval
= target_write_u32(target
, EJTAG_DCR
, dcr
)) != ERROR_OK
)
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