1 /***************************************************************************
2 * Copyright (C) 2009 by Paulius Zaleckas *
3 * paulius.zaleckas@gmail.com *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
22 * FA526 is very similar to ARM920T with following differences:
24 * - execution pipeline is 6 steps
26 * - has Branch Target Buffer
27 * - does not support reading of I/D cache contents
35 #include "target_type.h"
36 #include "arm_opcodes.h"
38 static void fa526_change_to_arm(struct target
*target
, uint32_t *r0
, uint32_t *pc
)
40 LOG_ERROR("%s: there is no Thumb state on FA526", __func__
);
43 static void fa526_read_core_regs(struct target
*target
,
44 uint32_t mask
, uint32_t* core_regs
[16])
47 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
48 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
50 /* STMIA r0-15, [r0] at debug speed
51 * register values will start to appear on 4th DCLK
53 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
55 /* fetch NOP, STM in DECODE stage */
56 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
57 /* fetch NOP, STM in SHIFT stage */
58 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
59 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
60 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
62 for (i
= 0; i
<= 15; i
++)
65 /* nothing fetched, STM in MEMORY (i'th cycle) */
66 arm9tdmi_clock_data_in(jtag_info
, core_regs
[i
]);
70 static void fa526_read_core_regs_target_buffer(struct target
*target
,
71 uint32_t mask
, void* buffer
, int size
)
74 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
75 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
76 int be
= (target
->endianness
== TARGET_BIG_ENDIAN
) ? 1 : 0;
77 uint32_t *buf_u32
= buffer
;
78 uint16_t *buf_u16
= buffer
;
79 uint8_t *buf_u8
= buffer
;
81 /* STMIA r0-15, [r0] at debug speed
82 * register values will start to appear on 4th DCLK
84 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
86 /* fetch NOP, STM in DECODE stage */
87 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
88 /* fetch NOP, STM in SHIFT stage */
89 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
90 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
91 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
93 for (i
= 0; i
<= 15; i
++)
96 /* nothing fetched, STM in MEMORY (i'th cycle) */
100 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u32
++, 4, be
);
103 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u16
++, 2, be
);
106 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u8
++, 1, be
);
112 static void fa526_read_xpsr(struct target
*target
, uint32_t *xpsr
, int spsr
)
114 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
115 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
118 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MRS(0, spsr
& 1), 0, NULL
, 0);
119 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
120 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
121 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
122 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
123 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
126 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STR(0, 15), 0, NULL
, 0);
127 /* fetch NOP, STR in DECODE stage */
128 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
129 /* fetch NOP, STR in SHIFT stage */
130 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
131 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
132 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
133 /* nothing fetched, STR in MEMORY */
134 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, xpsr
, 0);
137 static void fa526_write_xpsr(struct target
*target
, uint32_t xpsr
, int spsr
)
139 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
140 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
142 LOG_DEBUG("xpsr: %8.8" PRIx32
", spsr: %i", xpsr
, spsr
);
145 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr
& 0xff, 0, 1, spsr
), 0, NULL
, 0);
146 /* MSR2 fetched, MSR1 in DECODE */
147 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff00) >> 8, 0xc, 2, spsr
), 0, NULL
, 0);
148 /* MSR3 fetched, MSR1 in SHIFT, MSR2 in DECODE */
149 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff0000) >> 16, 0x8, 4, spsr
), 0, NULL
, 0);
150 /* MSR4 fetched, MSR1 in EXECUTE (1), MSR2 in SHIFT, MSR3 in DECODE */
151 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff000000) >> 24, 0x4, 8, spsr
), 0, NULL
, 0);
152 /* nothing fetched, MSR1 in EXECUTE (2) */
153 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
154 /* nothing fetched, MSR1 in EXECUTE (3) */
155 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
156 /* nothing fetched, MSR2 in EXECUTE (1), MSR3 in SHIFT, MSR4 in DECODE */
157 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
158 /* nothing fetched, MSR2 in EXECUTE (2) */
159 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
160 /* nothing fetched, MSR2 in EXECUTE (3) */
161 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
162 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in SHIFT */
163 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
164 /* nothing fetched, MSR3 in EXECUTE (2) */
165 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
166 /* nothing fetched, MSR3 in EXECUTE (3) */
167 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
168 /* NOP fetched, MSR4 in EXECUTE (1) */
169 /* last MSR writes flags, which takes only one cycle */
170 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
173 static void fa526_write_xpsr_im8(struct target
*target
,
174 uint8_t xpsr_im
, int rot
, int spsr
)
176 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
177 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
179 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im
, rot
, spsr
);
182 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr_im
, rot
, 1, spsr
), 0, NULL
, 0);
183 /* NOP fetched, MSR in DECODE */
184 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
185 /* NOP fetched, MSR in SHIFT */
186 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
187 /* NOP fetched, MSR in EXECUTE (1) */
188 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
190 /* rot == 4 writes flags, which takes only one cycle */
193 /* nothing fetched, MSR in EXECUTE (2) */
194 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
195 /* nothing fetched, MSR in EXECUTE (3) */
196 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
200 static void fa526_write_core_regs(struct target
*target
,
201 uint32_t mask
, uint32_t core_regs
[16])
204 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
205 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
207 /* LDMIA r0-15, [r0] at debug speed
208 * register values will start to appear on 4th DCLK
210 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
212 /* fetch NOP, LDM in DECODE stage */
213 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
214 /* fetch NOP, LDM in SHIFT stage */
215 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
216 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
217 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
219 for (i
= 0; i
<= 15; i
++)
222 /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */
223 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, core_regs
[i
], NULL
, 0);
225 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
228 static void fa526_write_pc(struct target
*target
, uint32_t pc
)
230 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
231 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
233 /* LDMIA r0-15, [r0] at debug speed
234 * register values will start to appear on 4th DCLK
236 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL
, 0);
238 /* fetch NOP, LDM in DECODE stage */
239 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
240 /* fetch NOP, LDM in SHIFT stage */
241 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
242 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
243 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
244 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
245 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, pc
, NULL
, 0);
246 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
247 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
248 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
249 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
250 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
251 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
254 static void fa526_branch_resume_thumb(struct target
*target
)
256 LOG_ERROR("%s: there is no Thumb state on FA526", __func__
);
259 static int fa526_init_arch_info_2(struct target
*target
,
260 struct arm7_9_common
*arm7_9
, struct jtag_tap
*tap
)
262 /* prepare JTAG information for the new target */
263 arm7_9
->jtag_info
.tap
= tap
;
264 arm7_9
->jtag_info
.scann_size
= 5;
266 /* register arch-specific functions */
267 arm7_9
->examine_debug_reason
= arm9tdmi_examine_debug_reason
;
268 arm7_9
->change_to_arm
= fa526_change_to_arm
;
269 arm7_9
->read_core_regs
= fa526_read_core_regs
;
270 arm7_9
->read_core_regs_target_buffer
= fa526_read_core_regs_target_buffer
;
271 arm7_9
->read_xpsr
= fa526_read_xpsr
;
273 arm7_9
->write_xpsr
= fa526_write_xpsr
;
274 arm7_9
->write_xpsr_im8
= fa526_write_xpsr_im8
;
275 arm7_9
->write_core_regs
= fa526_write_core_regs
;
277 arm7_9
->load_word_regs
= arm9tdmi_load_word_regs
;
278 arm7_9
->load_hword_reg
= arm9tdmi_load_hword_reg
;
279 arm7_9
->load_byte_reg
= arm9tdmi_load_byte_reg
;
281 arm7_9
->store_word_regs
= arm9tdmi_store_word_regs
;
282 arm7_9
->store_hword_reg
= arm9tdmi_store_hword_reg
;
283 arm7_9
->store_byte_reg
= arm9tdmi_store_byte_reg
;
285 arm7_9
->write_pc
= fa526_write_pc
;
286 arm7_9
->branch_resume
= arm9tdmi_branch_resume
;
287 arm7_9
->branch_resume_thumb
= fa526_branch_resume_thumb
;
289 arm7_9
->enable_single_step
= arm9tdmi_enable_single_step
;
290 arm7_9
->disable_single_step
= arm9tdmi_disable_single_step
;
292 arm7_9
->post_debug_entry
= NULL
;
294 arm7_9
->pre_restore_context
= NULL
;
296 /* initialize arch-specific breakpoint handling */
297 arm7_9
->arm_bkpt
= 0xdeeedeee;
298 arm7_9
->thumb_bkpt
= 0xdeee;
300 arm7_9
->dbgreq_adjust_pc
= 3;
302 arm7_9_init_arch_info(target
, arm7_9
);
304 /* override use of DBGRQ, this is safe on ARM9TDMI */
305 arm7_9
->use_dbgrq
= 1;
307 /* all ARM9s have the vector catch register */
308 arm7_9
->has_vector_catch
= 1;
313 static int fa526_init_arch_info(struct target
*target
,
314 struct arm920t_common
*arm920t
, struct jtag_tap
*tap
)
316 struct arm7_9_common
*arm7_9
= &arm920t
->arm7_9_common
;
318 /* initialize arm7/arm9 specific info (including armv4_5) */
319 fa526_init_arch_info_2(target
, arm7_9
, tap
);
321 arm920t
->common_magic
= ARM920T_COMMON_MAGIC
;
323 arm7_9
->post_debug_entry
= arm920t_post_debug_entry
;
324 arm7_9
->pre_restore_context
= arm920t_pre_restore_context
;
326 arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
327 arm920t
->armv4_5_mmu
.get_ttb
= arm920t_get_ttb
;
328 arm920t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
329 arm920t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
330 arm920t
->armv4_5_mmu
.disable_mmu_caches
= arm920t_disable_mmu_caches
;
331 arm920t
->armv4_5_mmu
.enable_mmu_caches
= arm920t_enable_mmu_caches
;
332 arm920t
->armv4_5_mmu
.has_tiny_pages
= 1;
333 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
335 /* disabling linefills leads to lockups, so keep them enabled for now
336 * this doesn't affect correctness, but might affect timing issues, if
337 * important data is evicted from the cache during the debug session
339 arm920t
->preserve_cache
= 0;
341 /* override hw single-step capability from ARM9TDMI */
342 arm7_9
->has_single_step
= 1;
347 static int fa526_target_create(struct target
*target
, Jim_Interp
*interp
)
349 struct arm920t_common
*arm920t
= calloc(1,sizeof(struct arm920t_common
));
351 return fa526_init_arch_info(target
, arm920t
, target
->tap
);
354 /** Holds methods for FA526 targets. */
355 struct target_type fa526_target
=
360 .arch_state
= arm920t_arch_state
,
362 .target_request_data
= arm7_9_target_request_data
,
365 .resume
= arm7_9_resume
,
368 .assert_reset
= arm7_9_assert_reset
,
369 .deassert_reset
= arm7_9_deassert_reset
,
370 .soft_reset_halt
= arm920t_soft_reset_halt
,
372 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
374 .read_memory
= arm920t_read_memory
,
375 .write_memory
= arm920t_write_memory
,
376 .bulk_write_memory
= arm7_9_bulk_write_memory
,
378 .checksum_memory
= arm_checksum_memory
,
379 .blank_check_memory
= arm_blank_check_memory
,
381 .run_algorithm
= armv4_5_run_algorithm
,
383 .add_breakpoint
= arm7_9_add_breakpoint
,
384 .remove_breakpoint
= arm7_9_remove_breakpoint
,
385 .add_watchpoint
= arm7_9_add_watchpoint
,
386 .remove_watchpoint
= arm7_9_remove_watchpoint
,
388 .commands
= arm920t_command_handlers
,
389 .target_create
= fa526_target_create
,
390 .init_target
= arm9tdmi_init_target
,
391 .examine
= arm7_9_examine
,
392 .check_reset
= arm7_9_check_reset
,
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