ETM trigger_percent becomes an ETB command
[openocd.git] / src / target / etm.h
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2007 by Vincent Palatin *
6 * vincent.palatin_openocd@m4x.org *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifndef ETM_H
24 #define ETM_H
25
26 #include "trace.h"
27 #include "arm_jtag.h"
28
29 struct image;
30
31 /* ETM registers (JTAG protocol) */
32 enum
33 {
34 ETM_CTRL = 0x00,
35 ETM_CONFIG = 0x01,
36 ETM_TRIG_EVENT = 0x02,
37 ETM_ASIC_CTRL = 0x03,
38 ETM_STATUS = 0x04,
39 ETM_SYS_CONFIG = 0x05,
40 ETM_TRACE_RESOURCE_CTRL = 0x06,
41 ETM_TRACE_EN_CTRL2 = 0x07,
42 ETM_TRACE_EN_EVENT = 0x08,
43 ETM_TRACE_EN_CTRL1 = 0x09,
44 /* optional FIFOFULL */
45 ETM_FIFOFULL_REGION = 0x0a,
46 ETM_FIFOFULL_LEVEL = 0x0b,
47 /* viewdata support */
48 ETM_VIEWDATA_EVENT = 0x0c,
49 ETM_VIEWDATA_CTRL1 = 0x0d,
50 ETM_VIEWDATA_CTRL2 = 0x0e, /* optional */
51 ETM_VIEWDATA_CTRL3 = 0x0f,
52 /* N pairs of ADDR_{COMPARATOR,ACCESS} registers */
53 ETM_ADDR_COMPARATOR_VALUE = 0x10,
54 ETM_ADDR_ACCESS_TYPE = 0x20,
55 /* N pairs of DATA_COMPARATOR_{VALUE,MASK} registers */
56 ETM_DATA_COMPARATOR_VALUE = 0x30,
57 ETM_DATA_COMPARATOR_MASK = 0x40,
58 /* N quads of COUNTER_{RELOAD_{VALUE,EVENT},ENABLE,VALUE} registers */
59 ETM_COUNTER_RELOAD_VALUE = 0x50,
60 ETM_COUNTER_ENABLE = 0x54,
61 ETM_COUNTER_RELOAD_EVENT = 0x58,
62 ETM_COUNTER_VALUE = 0x5c,
63 /* 6 sequencer event transitions */
64 ETM_SEQUENCER_EVENT = 0x60,
65 ETM_SEQUENCER_STATE = 0x67,
66 /* N triggered outputs */
67 ETM_EXTERNAL_OUTPUT = 0x68,
68 /* N task contexts */
69 ETM_CONTEXTID_COMPARATOR_VALUE = 0x6c,
70 ETM_CONTEXTID_COMPARATOR_MASK = 0x6f,
71 ETM_ID = 0x79,
72 };
73
74 struct etm_reg
75 {
76 uint32_t value;
77 const struct etm_reg_info *reg_info;
78 struct arm_jtag *jtag_info;
79 };
80
81 typedef enum
82 {
83 /* Port width */
84 ETM_PORT_4BIT = 0x00,
85 ETM_PORT_8BIT = 0x10,
86 ETM_PORT_16BIT = 0x20,
87 ETM_PORT_24BIT = 0x30,
88 ETM_PORT_32BIT = 0x40,
89 ETM_PORT_48BIT = 0x50,
90 ETM_PORT_64BIT = 0x60,
91 ETM_PORT_1BIT = 0x00 | (1 << 21),
92 ETM_PORT_2BIT = 0x10 | (1 << 21),
93 ETM_PORT_WIDTH_MASK = 0x70 | (1 << 21),
94 /* Port modes */
95 ETM_PORT_NORMAL = 0x00000,
96 ETM_PORT_MUXED = 0x10000,
97 ETM_PORT_DEMUXED = 0x20000,
98 ETM_PORT_MODE_MASK = 0x30000,
99 /* Clocking modes */
100 ETM_PORT_FULL_CLOCK = 0x0000,
101 ETM_PORT_HALF_CLOCK = 0x1000,
102 ETM_PORT_CLOCK_MASK = 0x1000,
103 } etm_portmode_t;
104
105 typedef enum
106 {
107 /* Data trace */
108 ETMV1_TRACE_NONE = 0x00,
109 ETMV1_TRACE_DATA = 0x01,
110 ETMV1_TRACE_ADDR = 0x02,
111 ETMV1_TRACE_MASK = 0x03,
112 /* ContextID */
113 ETMV1_CONTEXTID_NONE = 0x00,
114 ETMV1_CONTEXTID_8 = 0x10,
115 ETMV1_CONTEXTID_16 = 0x20,
116 ETMV1_CONTEXTID_32 = 0x30,
117 ETMV1_CONTEXTID_MASK = 0x30,
118 /* Misc */
119 ETMV1_CYCLE_ACCURATE = 0x100,
120 ETMV1_BRANCH_OUTPUT = 0x200
121 } etmv1_tracemode_t;
122
123 /* forward-declare ETM context */
124 struct etm_context;
125
126 struct etm_capture_driver
127 {
128 char *name;
129 const struct command_registration *commands;
130 int (*init)(struct etm_context *etm_ctx);
131 trace_status_t (*status)(struct etm_context *etm_ctx);
132 int (*read_trace)(struct etm_context *etm_ctx);
133 int (*start_capture)(struct etm_context *etm_ctx);
134 int (*stop_capture)(struct etm_context *etm_ctx);
135 };
136
137 enum
138 {
139 ETMV1_TRACESYNC_CYCLE = 0x1,
140 ETMV1_TRIGGER_CYCLE = 0x2,
141 };
142
143 struct etmv1_trace_data
144 {
145 uint8_t pipestat; /* bits 0-2 pipeline status */
146 uint16_t packet; /* packet data (4, 8 or 16 bit) */
147 int flags; /* ETMV1_TRACESYNC_CYCLE, ETMV1_TRIGGER_CYCLE */
148 };
149
150 /* describe a trace context
151 * if support for ETMv2 or ETMv3 is to be implemented,
152 * this will have to be split into version independent elements
153 * and a version specific part
154 */
155 struct etm_context
156 {
157 struct target *target; /* target this ETM is connected to */
158 struct reg_cache *reg_cache; /* ETM register cache */
159 struct etm_capture_driver *capture_driver; /* driver used to access ETM data */
160 void *capture_driver_priv; /* capture driver private data */
161 trace_status_t capture_status; /* current state of capture run */
162 struct etmv1_trace_data *trace_data; /* trace data */
163 uint32_t trace_depth; /* number of cycles to be analyzed, 0 if no data available */
164 etm_portmode_t portmode; /* normal, multiplexed or demultiplexed */
165 etmv1_tracemode_t tracemode; /* type of info trace contains */
166 int /*arm_state*/ core_state; /* current core state */
167 struct image *image; /* source for target opcodes */
168 uint32_t pipe_index; /* current trace cycle */
169 uint32_t data_index; /* cycle holding next data packet */
170 bool data_half; /* port half on a 16 bit port */
171 bool pc_ok; /* full PC has been acquired */
172 bool ptr_ok; /* whether last_ptr is valid */
173 uint8_t bcd_vers; /* e.g. 0x13 == ETMv1.3 */
174 uint32_t config; /* cache of ETM_CONFIG value */
175 uint32_t id; /* cache of ETM_ID value, or 0 */
176 uint32_t current_pc; /* current program counter */
177 uint32_t last_branch; /* last branch address output */
178 uint32_t last_branch_reason; /* type of last branch encountered */
179 uint32_t last_ptr; /* address of the last data access */
180 uint32_t last_instruction; /* index of last executed (to calc timings) */
181 };
182
183 /* PIPESTAT values */
184 typedef enum
185 {
186 STAT_IE = 0x0,
187 STAT_ID = 0x1,
188 STAT_IN = 0x2,
189 STAT_WT = 0x3,
190 STAT_BE = 0x4,
191 STAT_BD = 0x5,
192 STAT_TR = 0x6,
193 STAT_TD = 0x7
194 } etmv1_pipestat_t;
195
196 /* branch reason values */
197 typedef enum
198 {
199 BR_NORMAL = 0x0, /* Normal PC change : periodic synchro (ETMv1.1) */
200 BR_ENABLE = 0x1, /* Trace has been enabled */
201 BR_RESTART = 0x2, /* Trace restarted after a FIFO overflow */
202 BR_NODEBUG = 0x3, /* ARM has exited for debug state */
203 BR_PERIOD = 0x4, /* Peridioc synchronization point (ETM >= v1.2)*/
204 BR_RSVD5 = 0x5, /* reserved */
205 BR_RSVD6 = 0x6, /* reserved */
206 BR_RSVD7 = 0x7, /* reserved */
207 } etmv1_branch_reason_t;
208
209 struct reg_cache* etm_build_reg_cache(struct target *target,
210 struct arm_jtag *jtag_info, struct etm_context *etm_ctx);
211
212 int etm_setup(struct target *target);
213
214 extern const struct command_registration etm_command_handlers[];
215
216 #define ERROR_ETM_INVALID_DRIVER (-1300)
217 #define ERROR_ETM_PORTMODE_NOT_SUPPORTED (-1301)
218 #define ERROR_ETM_CAPTURE_INIT_FAILED (-1302)
219 #define ERROR_ETM_ANALYSIS_FAILED (-1303)
220
221 #endif /* ETM_H */