1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
28 #include "arm_disassembler.h"
30 #include "etm_dummy.h"
32 #if BUILD_OOCD_TRACE == 1
33 #include "oocd_trace.h"
38 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
40 * ETM modules collect instruction and/or data trace information, compress
41 * it, and transfer it to a debugging host through either a (buffered) trace
42 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
44 * There are several generations of these modules. Original versions have
45 * JTAG access through a dedicated scan chain. Recent versions have added
46 * access via coprocessor instructions, memory addressing, and the ARM Debug
47 * Interface v5 (ADIv5); and phased out direct JTAG access.
49 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
50 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
51 * implying non-JTAG connectivity options.
53 * Relevant documentation includes:
54 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
55 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
56 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
67 uint8_t size
; /* low-N of 32 bits */
68 uint8_t mode
; /* RO, WO, RW */
69 uint8_t bcd_vers
; /* 1.0, 2.0, etc */
74 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
75 * (Or on some processors, through coprocessor operations.)
76 * Newer versions of ETM make some W/O registers R/W, and
77 * provide definitions for some previously-unused bits.
80 /* core registers used to version/configure the ETM */
81 static const struct etm_reg_info etm_core
[] = {
82 /* NOTE: we "know" the order here ... */
83 { ETM_CONFIG
, 32, RO
, 0x10, "ETM_config", },
84 { ETM_ID
, 32, RO
, 0x20, "ETM_id", },
87 /* basic registers that are always there given the right ETM version */
88 static const struct etm_reg_info etm_basic
[] = {
89 /* ETM Trace Registers */
90 { ETM_CTRL
, 32, RW
, 0x10, "ETM_ctrl", },
91 { ETM_TRIG_EVENT
, 17, WO
, 0x10, "ETM_trig_event", },
92 { ETM_ASIC_CTRL
, 8, WO
, 0x10, "ETM_asic_ctrl", },
93 { ETM_STATUS
, 3, RO
, 0x11, "ETM_status", },
94 { ETM_SYS_CONFIG
, 9, RO
, 0x12, "ETM_sys_config", },
96 /* TraceEnable configuration */
97 { ETM_TRACE_RESOURCE_CTRL
, 32, WO
, 0x12, "ETM_trace_resource_ctrl", },
98 { ETM_TRACE_EN_CTRL2
, 16, WO
, 0x12, "ETM_trace_en_ctrl2", },
99 { ETM_TRACE_EN_EVENT
, 17, WO
, 0x10, "ETM_trace_en_event", },
100 { ETM_TRACE_EN_CTRL1
, 26, WO
, 0x10, "ETM_trace_en_ctrl1", },
102 /* ViewData configuration (data trace) */
103 { ETM_VIEWDATA_EVENT
, 17, WO
, 0x10, "ETM_viewdata_event", },
104 { ETM_VIEWDATA_CTRL1
, 32, WO
, 0x10, "ETM_viewdata_ctrl1", },
105 { ETM_VIEWDATA_CTRL2
, 32, WO
, 0x10, "ETM_viewdata_ctrl2", },
106 { ETM_VIEWDATA_CTRL3
, 17, WO
, 0x10, "ETM_viewdata_ctrl3", },
108 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
110 { 0x78, 12, WO
, 0x20, "ETM_sync_freq", },
111 { 0x7a, 22, RO
, 0x31, "ETM_config_code_ext", },
112 { 0x7b, 32, WO
, 0x31, "ETM_ext_input_select", },
113 { 0x7c, 32, WO
, 0x34, "ETM_trace_start_stop", },
114 { 0x7d, 8, WO
, 0x34, "ETM_behavior_control", },
117 static const struct etm_reg_info etm_fifofull
[] = {
118 /* FIFOFULL configuration */
119 { ETM_FIFOFULL_REGION
, 25, WO
, 0x10, "ETM_fifofull_region", },
120 { ETM_FIFOFULL_LEVEL
, 8, WO
, 0x10, "ETM_fifofull_level", },
123 static const struct etm_reg_info etm_addr_comp
[] = {
124 /* Address comparator register pairs */
125 #define ADDR_COMPARATOR(i) \
126 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
127 "ETM_addr_" #i "_comparator_value", }, \
128 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
129 "ETM_addr_" #i "_access_type", }
148 #undef ADDR_COMPARATOR
151 static const struct etm_reg_info etm_data_comp
[] = {
152 /* Data Value Comparators (NOTE: odd addresses are reserved) */
153 #define DATA_COMPARATOR(i) \
154 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
155 "ETM_data_" #i "_comparator_value", }, \
156 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
157 "ETM_data_" #i "_comparator_mask", }
167 #undef DATA_COMPARATOR
170 static const struct etm_reg_info etm_counters
[] = {
171 #define ETM_COUNTER(i) \
172 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
173 "ETM_counter_" #i "_reload_value", }, \
174 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
175 "ETM_counter_" #i "_enable", }, \
176 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
177 "ETM_counter_" #i "_reload_event", }, \
178 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
179 "ETM_counter_" #i "_value", }
188 static const struct etm_reg_info etm_sequencer
[] = {
190 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
191 "ETM_sequencer_event" #i, }
192 ETM_SEQ(0), /* 1->2 */
193 ETM_SEQ(1), /* 2->1 */
194 ETM_SEQ(2), /* 2->3 */
195 ETM_SEQ(3), /* 3->1 */
196 ETM_SEQ(4), /* 3->2 */
197 ETM_SEQ(5), /* 1->3 */
200 { ETM_SEQUENCER_STATE
, 2, RO
, 0x10, "ETM_sequencer_state", },
203 static const struct etm_reg_info etm_outputs
[] = {
204 #define ETM_OUTPUT(i) \
205 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
206 "ETM_external_output" #i, }
217 /* registers from 0x6c..0x7f were added after ETMv1.3 */
219 /* Context ID Comparators */
220 { 0x6c, 32, RO
, 0x20, "ETM_contextid_comparator_value1", }
221 { 0x6d, 32, RO
, 0x20, "ETM_contextid_comparator_value2", }
222 { 0x6e, 32, RO
, 0x20, "ETM_contextid_comparator_value3", }
223 { 0x6f, 32, RO
, 0x20, "ETM_contextid_comparator_mask", }
226 static int etm_get_reg(struct reg
*reg
);
227 static int etm_read_reg_w_check(struct reg
*reg
,
228 uint8_t *check_value
, uint8_t *check_mask
);
229 static int etm_register_user_commands(struct command_context
*cmd_ctx
);
230 static int etm_set_reg_w_exec(struct reg
*reg
, uint8_t *buf
);
231 static int etm_write_reg(struct reg
*reg
, uint32_t value
);
233 static const struct reg_arch_type etm_scan6_type
= {
235 .set
= etm_set_reg_w_exec
,
238 /* Look up register by ID ... most ETM instances only
239 * support a subset of the possible registers.
241 static struct reg
*etm_reg_lookup(struct etm_context
*etm_ctx
, unsigned id
)
243 struct reg_cache
*cache
= etm_ctx
->reg_cache
;
246 for (i
= 0; i
< cache
->num_regs
; i
++) {
247 struct etm_reg
*reg
= cache
->reg_list
[i
].arch_info
;
249 if (reg
->reg_info
->addr
== id
)
250 return &cache
->reg_list
[i
];
253 /* caller asking for nonexistent register is a bug!
254 * REVISIT say which of the N targets was involved */
255 LOG_ERROR("ETM: register 0x%02x not available", id
);
259 static void etm_reg_add(unsigned bcd_vers
, struct arm_jtag
*jtag_info
,
260 struct reg_cache
*cache
, struct etm_reg
*ereg
,
261 const struct etm_reg_info
*r
, unsigned nreg
)
263 struct reg
*reg
= cache
->reg_list
;
265 reg
+= cache
->num_regs
;
266 ereg
+= cache
->num_regs
;
268 /* add up to "nreg" registers from "r", if supported by this
269 * version of the ETM, to the specified cache.
271 for (; nreg
--; r
++) {
272 /* No more registers to add */
274 LOG_ERROR("etm_reg_add is requested to add non-existing registers, ETM config might be bogus");
278 /* this ETM may be too old to have some registers */
279 if (r
->bcd_vers
> bcd_vers
)
284 reg
->value
= &ereg
->value
;
285 reg
->arch_info
= ereg
;
286 reg
->type
= &etm_scan6_type
;
291 ereg
->jtag_info
= jtag_info
;
296 struct reg_cache
*etm_build_reg_cache(struct target
*target
,
297 struct arm_jtag
*jtag_info
, struct etm_context
*etm_ctx
)
299 struct reg_cache
*reg_cache
= malloc(sizeof(struct reg_cache
));
300 struct reg
*reg_list
= NULL
;
301 struct etm_reg
*arch_info
= NULL
;
302 unsigned bcd_vers
, config
;
304 /* the actual registers are kept in two arrays */
305 reg_list
= calloc(128, sizeof(struct reg
));
306 arch_info
= calloc(128, sizeof(struct etm_reg
));
308 /* fill in values for the reg cache */
309 reg_cache
->name
= "etm registers";
310 reg_cache
->next
= NULL
;
311 reg_cache
->reg_list
= reg_list
;
312 reg_cache
->num_regs
= 0;
314 /* add ETM_CONFIG, then parse its values to see
315 * which other registers exist in this ETM
317 etm_reg_add(0x10, jtag_info
, reg_cache
, arch_info
,
320 etm_get_reg(reg_list
);
321 etm_ctx
->config
= buf_get_u32(arch_info
->value
, 0, 32);
322 config
= etm_ctx
->config
;
324 /* figure ETM version then add base registers */
325 if (config
& (1 << 31)) {
326 LOG_WARNING("ETMv2+ support is incomplete");
328 /* REVISIT more registers may exist; they may now be
329 * readable; more register bits have defined meanings;
330 * don't presume trace start/stop support is present;
331 * and include any context ID comparator registers.
333 etm_reg_add(0x20, jtag_info
, reg_cache
, arch_info
,
335 etm_get_reg(reg_list
+ 1);
336 etm_ctx
->id
= buf_get_u32(
337 arch_info
[1].value
, 0, 32);
338 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx
->id
);
339 bcd_vers
= 0x10 + (((etm_ctx
->id
) >> 4) & 0xff);
342 switch (config
>> 28) {
359 LOG_WARNING("Bad ETMv1 protocol %d", config
>> 28);
363 etm_ctx
->bcd_vers
= bcd_vers
;
364 LOG_INFO("ETM v%d.%d", bcd_vers
>> 4, bcd_vers
& 0xf);
366 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
367 etm_basic
, ARRAY_SIZE(etm_basic
));
369 /* address and data comparators; counters; outputs */
370 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
371 etm_addr_comp
, 4 * (0x0f & (config
>> 0)));
372 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
373 etm_data_comp
, 2 * (0x0f & (config
>> 4)));
374 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
375 etm_counters
, 4 * (0x07 & (config
>> 13)));
376 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
377 etm_outputs
, (0x07 & (config
>> 20)));
379 /* FIFOFULL presence is optional
380 * REVISIT for ETMv1.2 and later, don't bother adding this
381 * unless ETM_SYS_CONFIG says it's also *supported* ...
383 if (config
& (1 << 23))
384 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
385 etm_fifofull
, ARRAY_SIZE(etm_fifofull
));
387 /* sequencer is optional (for state-dependant triggering) */
388 if (config
& (1 << 16))
389 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
390 etm_sequencer
, ARRAY_SIZE(etm_sequencer
));
392 /* REVISIT could realloc and likely save half the memory
393 * in the two chunks we allocated...
396 /* the ETM might have an ETB connected */
397 if (strcmp(etm_ctx
->capture_driver
->name
, "etb") == 0) {
398 struct etb
*etb
= etm_ctx
->capture_driver_priv
;
401 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
405 reg_cache
->next
= etb_build_reg_cache(etb
);
407 etb
->reg_cache
= reg_cache
->next
;
410 etm_ctx
->reg_cache
= reg_cache
;
420 static int etm_read_reg(struct reg
*reg
)
422 return etm_read_reg_w_check(reg
, NULL
, NULL
);
425 static int etm_store_reg(struct reg
*reg
)
427 return etm_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
430 int etm_setup(struct target
*target
)
433 uint32_t etm_ctrl_value
;
434 struct arm
*arm
= target_to_arm(target
);
435 struct etm_context
*etm_ctx
= arm
->etm
;
436 struct reg
*etm_ctrl_reg
;
438 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
442 /* initialize some ETM control register settings */
443 etm_get_reg(etm_ctrl_reg
);
444 etm_ctrl_value
= buf_get_u32(etm_ctrl_reg
->value
, 0, 32);
446 /* clear the ETM powerdown bit (0) */
447 etm_ctrl_value
&= ~ETM_CTRL_POWERDOWN
;
449 /* configure port width (21,6:4), mode (13,17:16) and
450 * for older modules clocking (13)
452 etm_ctrl_value
= (etm_ctrl_value
453 & ~ETM_PORT_WIDTH_MASK
454 & ~ETM_PORT_MODE_MASK
456 & ~ETM_PORT_CLOCK_MASK
)
459 buf_set_u32(etm_ctrl_reg
->value
, 0, 32, etm_ctrl_value
);
460 etm_store_reg(etm_ctrl_reg
);
462 etm_ctx
->control
= etm_ctrl_value
;
464 retval
= jtag_execute_queue();
465 if (retval
!= ERROR_OK
)
468 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
469 * verify that those width and mode settings are OK ...
472 retval
= etm_ctx
->capture_driver
->init(etm_ctx
);
473 if (retval
!= ERROR_OK
) {
474 LOG_ERROR("ETM capture driver initialization failed");
480 static int etm_get_reg(struct reg
*reg
)
484 retval
= etm_read_reg(reg
);
485 if (retval
!= ERROR_OK
) {
486 LOG_ERROR("BUG: error scheduling etm register read");
490 retval
= jtag_execute_queue();
491 if (retval
!= ERROR_OK
) {
492 LOG_ERROR("register read failed");
499 static int etm_read_reg_w_check(struct reg
*reg
,
500 uint8_t *check_value
, uint8_t *check_mask
)
502 struct etm_reg
*etm_reg
= reg
->arch_info
;
503 const struct etm_reg_info
*r
= etm_reg
->reg_info
;
504 uint8_t reg_addr
= r
->addr
& 0x7f;
505 struct scan_field fields
[3];
508 if (etm_reg
->reg_info
->mode
== WO
) {
509 LOG_ERROR("BUG: can't read write-only register %s", r
->name
);
510 return ERROR_COMMAND_SYNTAX_ERROR
;
513 LOG_DEBUG("%s (%u)", r
->name
, reg_addr
);
515 retval
= arm_jtag_scann(etm_reg
->jtag_info
, 0x6, TAP_IDLE
);
516 if (retval
!= ERROR_OK
)
518 retval
= arm_jtag_set_instr(etm_reg
->jtag_info
,
519 etm_reg
->jtag_info
->intest_instr
,
522 if (retval
!= ERROR_OK
)
525 fields
[0].num_bits
= 32;
526 fields
[0].out_value
= reg
->value
;
527 fields
[0].in_value
= NULL
;
528 fields
[0].check_value
= NULL
;
529 fields
[0].check_mask
= NULL
;
531 fields
[1].num_bits
= 7;
533 fields
[1].out_value
= &temp1
;
534 buf_set_u32(&temp1
, 0, 7, reg_addr
);
535 fields
[1].in_value
= NULL
;
536 fields
[1].check_value
= NULL
;
537 fields
[1].check_mask
= NULL
;
539 fields
[2].num_bits
= 1;
541 fields
[2].out_value
= &temp2
;
542 buf_set_u32(&temp2
, 0, 1, 0);
543 fields
[2].in_value
= NULL
;
544 fields
[2].check_value
= NULL
;
545 fields
[2].check_mask
= NULL
;
547 jtag_add_dr_scan(etm_reg
->jtag_info
->tap
, 3, fields
, TAP_IDLE
);
549 fields
[0].in_value
= reg
->value
;
550 fields
[0].check_value
= check_value
;
551 fields
[0].check_mask
= check_mask
;
553 jtag_add_dr_scan_check(etm_reg
->jtag_info
->tap
, 3, fields
, TAP_IDLE
);
558 static int etm_set_reg(struct reg
*reg
, uint32_t value
)
560 int retval
= etm_write_reg(reg
, value
);
561 if (retval
!= ERROR_OK
) {
562 LOG_ERROR("BUG: error scheduling etm register write");
566 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
573 static int etm_set_reg_w_exec(struct reg
*reg
, uint8_t *buf
)
577 etm_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
579 retval
= jtag_execute_queue();
580 if (retval
!= ERROR_OK
) {
581 LOG_ERROR("register write failed");
587 static int etm_write_reg(struct reg
*reg
, uint32_t value
)
589 struct etm_reg
*etm_reg
= reg
->arch_info
;
590 const struct etm_reg_info
*r
= etm_reg
->reg_info
;
591 uint8_t reg_addr
= r
->addr
& 0x7f;
592 struct scan_field fields
[3];
595 if (etm_reg
->reg_info
->mode
== RO
) {
596 LOG_ERROR("BUG: can't write read--only register %s", r
->name
);
597 return ERROR_COMMAND_SYNTAX_ERROR
;
600 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32
"", r
->name
, reg_addr
, value
);
602 retval
= arm_jtag_scann(etm_reg
->jtag_info
, 0x6, TAP_IDLE
);
603 if (retval
!= ERROR_OK
)
605 retval
= arm_jtag_set_instr(etm_reg
->jtag_info
,
606 etm_reg
->jtag_info
->intest_instr
,
609 if (retval
!= ERROR_OK
)
612 fields
[0].num_bits
= 32;
614 fields
[0].out_value
= tmp1
;
615 buf_set_u32(tmp1
, 0, 32, value
);
616 fields
[0].in_value
= NULL
;
618 fields
[1].num_bits
= 7;
620 fields
[1].out_value
= &tmp2
;
621 buf_set_u32(&tmp2
, 0, 7, reg_addr
);
622 fields
[1].in_value
= NULL
;
624 fields
[2].num_bits
= 1;
626 fields
[2].out_value
= &tmp3
;
627 buf_set_u32(&tmp3
, 0, 1, 1);
628 fields
[2].in_value
= NULL
;
630 jtag_add_dr_scan(etm_reg
->jtag_info
->tap
, 3, fields
, TAP_IDLE
);
636 /* ETM trace analysis functionality */
638 static struct etm_capture_driver
*etm_capture_drivers
[] = {
640 &etm_dummy_capture_driver
,
641 #if BUILD_OOCD_TRACE == 1
642 &oocd_trace_capture_driver
,
647 static int etm_read_instruction(struct etm_context
*ctx
, struct arm_instruction
*instruction
)
656 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
658 /* search for the section the current instruction belongs to */
659 for (i
= 0; i
< ctx
->image
->num_sections
; i
++) {
660 if ((ctx
->image
->sections
[i
].base_address
<= ctx
->current_pc
) &&
661 (ctx
->image
->sections
[i
].base_address
+ ctx
->image
->sections
[i
].size
>
669 /* current instruction couldn't be found in the image */
670 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
673 if (ctx
->core_state
== ARM_STATE_ARM
) {
675 retval
= image_read_section(ctx
->image
, section
,
677 ctx
->image
->sections
[section
].base_address
,
679 if (retval
!= ERROR_OK
) {
680 LOG_ERROR("error while reading instruction");
681 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
683 opcode
= target_buffer_get_u32(ctx
->target
, buf
);
684 arm_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
685 } else if (ctx
->core_state
== ARM_STATE_THUMB
) {
687 retval
= image_read_section(ctx
->image
, section
,
689 ctx
->image
->sections
[section
].base_address
,
691 if (retval
!= ERROR_OK
) {
692 LOG_ERROR("error while reading instruction");
693 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
695 opcode
= target_buffer_get_u16(ctx
->target
, buf
);
696 thumb_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
697 } else if (ctx
->core_state
== ARM_STATE_JAZELLE
) {
698 LOG_ERROR("BUG: tracing of jazelle code not supported");
701 LOG_ERROR("BUG: unknown core state encountered");
708 static int etmv1_next_packet(struct etm_context
*ctx
, uint8_t *packet
, int apo
)
710 while (ctx
->data_index
< ctx
->trace_depth
) {
711 /* if the caller specified an address packet offset, skip until the
712 * we reach the n-th cycle marked with tracesync */
714 if (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRACESYNC_CYCLE
)
724 /* no tracedata output during a TD cycle
725 * or in a trigger cycle */
726 if ((ctx
->trace_data
[ctx
->data_index
].pipestat
== STAT_TD
)
727 || (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRIGGER_CYCLE
)) {
733 /* FIXME there are more port widths than these... */
734 if ((ctx
->control
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_16BIT
) {
735 if (ctx
->data_half
== 0) {
736 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
739 *packet
= (ctx
->trace_data
[ctx
->data_index
].packet
& 0xff00) >> 8;
743 } else if ((ctx
->control
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
) {
744 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
747 /* on a 4-bit port, a packet will be output during two consecutive cycles */
748 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
751 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xf;
752 *packet
|= (ctx
->trace_data
[ctx
->data_index
+ 1].packet
& 0xf) << 4;
753 ctx
->data_index
+= 2;
762 static int etmv1_branch_address(struct etm_context
*ctx
)
770 /* quit analysis if less than two cycles are left in the trace
771 * because we can't extract the APO */
772 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
775 /* a BE could be output during an APO cycle, skip the current
776 * and continue with the new one */
777 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x4)
779 if (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x4)
782 /* address packet offset encoded in the next two cycles' pipestat bits */
783 apo
= ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x3;
784 apo
|= (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x3) << 2;
786 /* count number of tracesync cycles between current pipe_index and data_index
787 * i.e. the number of tracesyncs that data_index already passed by
788 * to subtract them from the APO */
789 for (i
= ctx
->pipe_index
; i
< ctx
->data_index
; i
++) {
790 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& ETMV1_TRACESYNC_CYCLE
)
794 /* extract up to four 7-bit packets */
796 retval
= etmv1_next_packet(ctx
, &packet
, (shift
== 0) ? apo
+ 1 : 0);
799 ctx
->last_branch
&= ~(0x7f << shift
);
800 ctx
->last_branch
|= (packet
& 0x7f) << shift
;
802 } while ((packet
& 0x80) && (shift
< 28));
804 /* one last packet holding 4 bits of the address, plus the branch reason code */
805 if ((shift
== 28) && (packet
& 0x80)) {
806 retval
= etmv1_next_packet(ctx
, &packet
, 0);
809 ctx
->last_branch
&= 0x0fffffff;
810 ctx
->last_branch
|= (packet
& 0x0f) << 28;
811 ctx
->last_branch_reason
= (packet
& 0x70) >> 4;
814 ctx
->last_branch_reason
= 0;
819 /* if a full address was output, we might have branched into Jazelle state */
820 if ((shift
== 32) && (packet
& 0x80))
821 ctx
->core_state
= ARM_STATE_JAZELLE
;
823 /* if we didn't branch into Jazelle state, the current processor state is
824 * encoded in bit 0 of the branch target address */
825 if (ctx
->last_branch
& 0x1) {
826 ctx
->core_state
= ARM_STATE_THUMB
;
827 ctx
->last_branch
&= ~0x1;
829 ctx
->core_state
= ARM_STATE_ARM
;
830 ctx
->last_branch
&= ~0x3;
837 static int etmv1_data(struct etm_context
*ctx
, int size
, uint32_t *data
)
843 for (j
= 0; j
< size
; j
++) {
844 retval
= etmv1_next_packet(ctx
, &buf
[j
], 0);
850 LOG_ERROR("TODO: add support for 64-bit values");
852 } else if (size
== 4)
853 *data
= target_buffer_get_u32(ctx
->target
, buf
);
855 *data
= target_buffer_get_u16(ctx
->target
, buf
);
864 static int etmv1_analyze_trace(struct etm_context
*ctx
, struct command_context
*cmd_ctx
)
867 struct arm_instruction instruction
;
869 /* read the trace data if it wasn't read already */
870 if (ctx
->trace_depth
== 0)
871 ctx
->capture_driver
->read_trace(ctx
);
873 if (ctx
->trace_depth
== 0) {
874 command_print(cmd_ctx
, "Trace is empty.");
878 /* start at the beginning of the captured trace */
883 /* neither the PC nor the data pointer are valid */
887 while (ctx
->pipe_index
< ctx
->trace_depth
) {
888 uint8_t pipestat
= ctx
->trace_data
[ctx
->pipe_index
].pipestat
;
889 uint32_t next_pc
= ctx
->current_pc
;
890 uint32_t old_data_index
= ctx
->data_index
;
891 uint32_t old_data_half
= ctx
->data_half
;
892 uint32_t old_index
= ctx
->pipe_index
;
893 uint32_t last_instruction
= ctx
->last_instruction
;
895 int current_pc_ok
= ctx
->pc_ok
;
897 if (ctx
->trace_data
[ctx
->pipe_index
].flags
& ETMV1_TRIGGER_CYCLE
)
898 command_print(cmd_ctx
, "--- trigger ---");
900 /* instructions execute in IE/D or BE/D cycles */
901 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
902 ctx
->last_instruction
= ctx
->pipe_index
;
904 /* if we don't have a valid pc skip until we reach an indirect branch */
905 if ((!ctx
->pc_ok
) && (pipestat
!= STAT_BE
)) {
910 /* any indirect branch could have interrupted instruction flow
911 * - the branch reason code could indicate a trace discontinuity
912 * - a branch to the exception vectors indicates an exception
914 if ((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
)) {
915 /* backup current data index, to be able to consume the branch address
916 * before examining data address and values
918 old_data_index
= ctx
->data_index
;
919 old_data_half
= ctx
->data_half
;
921 ctx
->last_instruction
= ctx
->pipe_index
;
923 retval
= etmv1_branch_address(ctx
);
925 /* negative return value from etmv1_branch_address means we ran out of packets,
926 * quit analysing the trace */
930 /* a positive return values means the current branch was abandoned,
931 * and a new branch was encountered in cycle ctx->pipe_index + retval;
934 "abandoned branch encountered, correctness of analysis uncertain");
935 ctx
->pipe_index
+= retval
;
939 /* skip over APO cycles */
940 ctx
->pipe_index
+= 2;
942 switch (ctx
->last_branch_reason
) {
943 case 0x0: /* normal PC change */
944 next_pc
= ctx
->last_branch
;
946 case 0x1: /* tracing enabled */
947 command_print(cmd_ctx
,
948 "--- tracing enabled at 0x%8.8" PRIx32
" ---",
950 ctx
->current_pc
= ctx
->last_branch
;
954 case 0x2: /* trace restarted after FIFO overflow */
955 command_print(cmd_ctx
,
956 "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32
" ---",
958 ctx
->current_pc
= ctx
->last_branch
;
962 case 0x3: /* exit from debug state */
963 command_print(cmd_ctx
,
964 "--- exit from debug state at 0x%8.8" PRIx32
" ---",
966 ctx
->current_pc
= ctx
->last_branch
;
970 case 0x4: /* periodic synchronization point */
971 next_pc
= ctx
->last_branch
;
972 /* if we had no valid PC prior to this synchronization point,
973 * we have to move on with the next trace cycle
975 if (!current_pc_ok
) {
976 command_print(cmd_ctx
,
977 "--- periodic synchronization point at 0x%8.8" PRIx32
" ---",
979 ctx
->current_pc
= next_pc
;
984 default: /* reserved */
986 "BUG: branch reason code 0x%" PRIx32
" is reserved",
987 ctx
->last_branch_reason
);
991 /* if we got here the branch was a normal PC change
992 * (or a periodic synchronization point, which means the same for that matter)
993 * if we didn't acquire a complete PC continue with the next cycle
998 /* indirect branch to the exception vector means an exception occurred */
999 if ((ctx
->last_branch
<= 0x20)
1000 || ((ctx
->last_branch
>= 0xffff0000) &&
1001 (ctx
->last_branch
<= 0xffff0020))) {
1002 if ((ctx
->last_branch
& 0xff) == 0x10)
1003 command_print(cmd_ctx
, "data abort");
1005 command_print(cmd_ctx
,
1006 "exception vector 0x%2.2" PRIx32
"",
1008 ctx
->current_pc
= ctx
->last_branch
;
1015 /* an instruction was executed (or not, depending on the condition flags)
1016 * retrieve it from the image for displaying */
1017 if (ctx
->pc_ok
&& (pipestat
!= STAT_WT
) && (pipestat
!= STAT_TD
) &&
1018 !(((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
)) &&
1019 ((ctx
->last_branch_reason
!= 0x0) && (ctx
->last_branch_reason
!= 0x4)))) {
1020 retval
= etm_read_instruction(ctx
, &instruction
);
1021 if (retval
!= ERROR_OK
) {
1022 /* can't continue tracing with no image available */
1023 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
1025 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
) {
1026 /* TODO: handle incomplete images
1027 * for now we just quit the analysis*/
1032 cycles
= old_index
- last_instruction
;
1035 if ((pipestat
== STAT_ID
) || (pipestat
== STAT_BD
)) {
1036 uint32_t new_data_index
= ctx
->data_index
;
1037 uint32_t new_data_half
= ctx
->data_half
;
1039 /* in case of a branch with data, the branch target address was consumed before
1040 * we temporarily go back to the saved data index */
1041 if (pipestat
== STAT_BD
) {
1042 ctx
->data_index
= old_data_index
;
1043 ctx
->data_half
= old_data_half
;
1046 if (ctx
->control
& ETM_CTRL_TRACE_ADDR
) {
1051 retval
= etmv1_next_packet(ctx
, &packet
, 0);
1053 return ERROR_ETM_ANALYSIS_FAILED
;
1054 ctx
->last_ptr
&= ~(0x7f << shift
);
1055 ctx
->last_ptr
|= (packet
& 0x7f) << shift
;
1057 } while ((packet
& 0x80) && (shift
< 32));
1063 command_print(cmd_ctx
,
1064 "address: 0x%8.8" PRIx32
"",
1068 if (ctx
->control
& ETM_CTRL_TRACE_DATA
) {
1069 if ((instruction
.type
== ARM_LDM
) ||
1070 (instruction
.type
== ARM_STM
)) {
1072 for (i
= 0; i
< 16; i
++) {
1073 if (instruction
.info
.load_store_multiple
.
1074 register_list
& (1 << i
)) {
1076 if (etmv1_data(ctx
, 4, &data
) != 0)
1077 return ERROR_ETM_ANALYSIS_FAILED
;
1078 command_print(cmd_ctx
,
1079 "data: 0x%8.8" PRIx32
"",
1083 } else if ((instruction
.type
>= ARM_LDR
) &&
1084 (instruction
.type
<= ARM_STRH
)) {
1086 if (etmv1_data(ctx
, arm_access_size(&instruction
),
1088 return ERROR_ETM_ANALYSIS_FAILED
;
1089 command_print(cmd_ctx
, "data: 0x%8.8" PRIx32
"", data
);
1093 /* restore data index after consuming BD address and data */
1094 if (pipestat
== STAT_BD
) {
1095 ctx
->data_index
= new_data_index
;
1096 ctx
->data_half
= new_data_half
;
1101 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
)) {
1102 if (((instruction
.type
== ARM_B
) ||
1103 (instruction
.type
== ARM_BL
) ||
1104 (instruction
.type
== ARM_BLX
)) &&
1105 (instruction
.info
.b_bl_bx_blx
.target_address
!= 0xffffffff))
1106 next_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
1108 next_pc
+= (ctx
->core_state
== ARM_STATE_ARM
) ? 4 : 2;
1109 } else if (pipestat
== STAT_IN
)
1110 next_pc
+= (ctx
->core_state
== ARM_STATE_ARM
) ? 4 : 2;
1112 if ((pipestat
!= STAT_TD
) && (pipestat
!= STAT_WT
)) {
1113 char cycles_text
[32] = "";
1115 /* if the trace was captured with cycle accurate tracing enabled,
1116 * output the number of cycles since the last executed instruction
1118 if (ctx
->control
& ETM_CTRL_CYCLE_ACCURATE
) {
1119 snprintf(cycles_text
, 32, " (%i %s)",
1121 (cycles
== 1) ? "cycle" : "cycles");
1124 command_print(cmd_ctx
, "%s%s%s",
1126 (pipestat
== STAT_IN
) ? " (not executed)" : "",
1129 ctx
->current_pc
= next_pc
;
1131 /* packets for an instruction don't start on or before the preceding
1132 * functional pipestat (i.e. other than WT or TD)
1134 if (ctx
->data_index
<= ctx
->pipe_index
) {
1135 ctx
->data_index
= ctx
->pipe_index
+ 1;
1140 ctx
->pipe_index
+= 1;
1146 static COMMAND_HELPER(handle_etm_tracemode_command_update
,
1151 /* what parts of data access are traced? */
1152 if (strcmp(CMD_ARGV
[0], "none") == 0)
1154 else if (strcmp(CMD_ARGV
[0], "data") == 0)
1155 tracemode
= ETM_CTRL_TRACE_DATA
;
1156 else if (strcmp(CMD_ARGV
[0], "address") == 0)
1157 tracemode
= ETM_CTRL_TRACE_ADDR
;
1158 else if (strcmp(CMD_ARGV
[0], "all") == 0)
1159 tracemode
= ETM_CTRL_TRACE_DATA
| ETM_CTRL_TRACE_ADDR
;
1161 command_print(CMD_CTX
, "invalid option '%s'", CMD_ARGV
[0]);
1162 return ERROR_COMMAND_SYNTAX_ERROR
;
1166 COMMAND_PARSE_NUMBER(u8
, CMD_ARGV
[1], context_id
);
1167 switch (context_id
) {
1169 tracemode
|= ETM_CTRL_CONTEXTID_NONE
;
1172 tracemode
|= ETM_CTRL_CONTEXTID_8
;
1175 tracemode
|= ETM_CTRL_CONTEXTID_16
;
1178 tracemode
|= ETM_CTRL_CONTEXTID_32
;
1181 command_print(CMD_CTX
, "invalid option '%s'", CMD_ARGV
[1]);
1182 return ERROR_COMMAND_SYNTAX_ERROR
;
1185 bool etmv1_cycle_accurate
;
1186 COMMAND_PARSE_ENABLE(CMD_ARGV
[2], etmv1_cycle_accurate
);
1187 if (etmv1_cycle_accurate
)
1188 tracemode
|= ETM_CTRL_CYCLE_ACCURATE
;
1190 bool etmv1_branch_output
;
1191 COMMAND_PARSE_ENABLE(CMD_ARGV
[3], etmv1_branch_output
);
1192 if (etmv1_branch_output
)
1193 tracemode
|= ETM_CTRL_BRANCH_OUTPUT
;
1196 * - CPRT tracing (coprocessor register transfers)
1197 * - debug request (causes debug entry on trigger)
1198 * - stall on FIFOFULL (preventing tracedata loss)
1205 COMMAND_HANDLER(handle_etm_tracemode_command
)
1207 struct target
*target
= get_current_target(CMD_CTX
);
1208 struct arm
*arm
= target_to_arm(target
);
1209 struct etm_context
*etm
;
1212 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1218 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1222 uint32_t tracemode
= etm
->control
;
1228 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update
,
1232 return ERROR_COMMAND_SYNTAX_ERROR
;
1236 * todo: fail if parameters were invalid for this hardware,
1237 * or couldn't be written; display actual hardware state...
1240 command_print(CMD_CTX
, "current tracemode configuration:");
1242 switch (tracemode
& ETM_CTRL_TRACE_MASK
) {
1244 command_print(CMD_CTX
, "data tracing: none");
1246 case ETM_CTRL_TRACE_DATA
:
1247 command_print(CMD_CTX
, "data tracing: data only");
1249 case ETM_CTRL_TRACE_ADDR
:
1250 command_print(CMD_CTX
, "data tracing: address only");
1252 case ETM_CTRL_TRACE_DATA
| ETM_CTRL_TRACE_ADDR
:
1253 command_print(CMD_CTX
, "data tracing: address and data");
1257 switch (tracemode
& ETM_CTRL_CONTEXTID_MASK
) {
1258 case ETM_CTRL_CONTEXTID_NONE
:
1259 command_print(CMD_CTX
, "contextid tracing: none");
1261 case ETM_CTRL_CONTEXTID_8
:
1262 command_print(CMD_CTX
, "contextid tracing: 8 bit");
1264 case ETM_CTRL_CONTEXTID_16
:
1265 command_print(CMD_CTX
, "contextid tracing: 16 bit");
1267 case ETM_CTRL_CONTEXTID_32
:
1268 command_print(CMD_CTX
, "contextid tracing: 32 bit");
1272 if (tracemode
& ETM_CTRL_CYCLE_ACCURATE
)
1273 command_print(CMD_CTX
, "cycle-accurate tracing enabled");
1275 command_print(CMD_CTX
, "cycle-accurate tracing disabled");
1277 if (tracemode
& ETM_CTRL_BRANCH_OUTPUT
)
1278 command_print(CMD_CTX
, "full branch address output enabled");
1280 command_print(CMD_CTX
, "full branch address output disabled");
1282 #define TRACEMODE_MASK ( \
1283 ETM_CTRL_CONTEXTID_MASK \
1284 | ETM_CTRL_BRANCH_OUTPUT \
1285 | ETM_CTRL_CYCLE_ACCURATE \
1286 | ETM_CTRL_TRACE_MASK \
1289 /* only update ETM_CTRL register if tracemode changed */
1290 if ((etm
->control
& TRACEMODE_MASK
) != tracemode
) {
1291 struct reg
*etm_ctrl_reg
;
1293 etm_ctrl_reg
= etm_reg_lookup(etm
, ETM_CTRL
);
1297 etm
->control
&= ~TRACEMODE_MASK
;
1298 etm
->control
|= tracemode
& TRACEMODE_MASK
;
1300 buf_set_u32(etm_ctrl_reg
->value
, 0, 32, etm
->control
);
1301 etm_store_reg(etm_ctrl_reg
);
1303 /* invalidate old trace data */
1304 etm
->capture_status
= TRACE_IDLE
;
1305 if (etm
->trace_depth
> 0) {
1306 free(etm
->trace_data
);
1307 etm
->trace_data
= NULL
;
1309 etm
->trace_depth
= 0;
1312 #undef TRACEMODE_MASK
1317 COMMAND_HANDLER(handle_etm_config_command
)
1319 struct target
*target
;
1321 uint32_t portmode
= 0x0;
1322 struct etm_context
*etm_ctx
;
1326 return ERROR_COMMAND_SYNTAX_ERROR
;
1328 target
= get_target(CMD_ARGV
[0]);
1330 LOG_ERROR("target '%s' not defined", CMD_ARGV
[0]);
1334 arm
= target_to_arm(target
);
1336 command_print(CMD_CTX
, "target '%s' is '%s'; not an ARM",
1337 target_name(target
),
1338 target_type_name(target
));
1342 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1343 * version we'll be using!! -- so we can't know how to validate
1344 * params yet. "etm config" should likely be *AFTER* hookup...
1346 * - Many more widths might be supported ... and we can easily
1347 * check whether our setting "took".
1349 * - The "clock" and "mode" bits are interpreted differently.
1350 * See ARM IHI 0014O table 2-17 for the old behaviour, and
1351 * table 2-18 for the new. With ETB it's best to specify
1355 COMMAND_PARSE_NUMBER(u8
, CMD_ARGV
[1], port_width
);
1356 switch (port_width
) {
1357 /* before ETMv3.0 */
1359 portmode
|= ETM_PORT_4BIT
;
1362 portmode
|= ETM_PORT_8BIT
;
1365 portmode
|= ETM_PORT_16BIT
;
1367 /* ETMv3.0 and later*/
1369 portmode
|= ETM_PORT_24BIT
;
1372 portmode
|= ETM_PORT_32BIT
;
1375 portmode
|= ETM_PORT_48BIT
;
1378 portmode
|= ETM_PORT_64BIT
;
1381 portmode
|= ETM_PORT_1BIT
;
1384 portmode
|= ETM_PORT_2BIT
;
1387 command_print(CMD_CTX
,
1388 "unsupported ETM port width '%s'", CMD_ARGV
[1]);
1392 if (strcmp("normal", CMD_ARGV
[2]) == 0)
1393 portmode
|= ETM_PORT_NORMAL
;
1394 else if (strcmp("multiplexed", CMD_ARGV
[2]) == 0)
1395 portmode
|= ETM_PORT_MUXED
;
1396 else if (strcmp("demultiplexed", CMD_ARGV
[2]) == 0)
1397 portmode
|= ETM_PORT_DEMUXED
;
1399 command_print(CMD_CTX
,
1400 "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'",
1405 if (strcmp("half", CMD_ARGV
[3]) == 0)
1406 portmode
|= ETM_PORT_HALF_CLOCK
;
1407 else if (strcmp("full", CMD_ARGV
[3]) == 0)
1408 portmode
|= ETM_PORT_FULL_CLOCK
;
1410 command_print(CMD_CTX
,
1411 "unsupported ETM port clocking '%s', must be 'full' or 'half'",
1416 etm_ctx
= calloc(1, sizeof(struct etm_context
));
1418 LOG_DEBUG("out of memory");
1422 for (i
= 0; etm_capture_drivers
[i
]; i
++) {
1423 if (strcmp(CMD_ARGV
[4], etm_capture_drivers
[i
]->name
) == 0) {
1424 int retval
= register_commands(CMD_CTX
, NULL
,
1425 etm_capture_drivers
[i
]->commands
);
1426 if (ERROR_OK
!= retval
) {
1431 etm_ctx
->capture_driver
= etm_capture_drivers
[i
];
1437 if (!etm_capture_drivers
[i
]) {
1438 /* no supported capture driver found, don't register an ETM */
1440 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV
[4]);
1444 etm_ctx
->target
= target
;
1445 etm_ctx
->trace_data
= NULL
;
1446 etm_ctx
->control
= portmode
;
1447 etm_ctx
->core_state
= ARM_STATE_ARM
;
1451 return etm_register_user_commands(CMD_CTX
);
1454 COMMAND_HANDLER(handle_etm_info_command
)
1456 struct target
*target
;
1458 struct etm_context
*etm
;
1459 struct reg
*etm_sys_config_reg
;
1463 target
= get_current_target(CMD_CTX
);
1464 arm
= target_to_arm(target
);
1466 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1472 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1476 command_print(CMD_CTX
, "ETM v%d.%d",
1477 etm
->bcd_vers
>> 4, etm
->bcd_vers
& 0xf);
1478 command_print(CMD_CTX
, "pairs of address comparators: %i",
1479 (int) (etm
->config
>> 0) & 0x0f);
1480 command_print(CMD_CTX
, "data comparators: %i",
1481 (int) (etm
->config
>> 4) & 0x0f);
1482 command_print(CMD_CTX
, "memory map decoders: %i",
1483 (int) (etm
->config
>> 8) & 0x1f);
1484 command_print(CMD_CTX
, "number of counters: %i",
1485 (int) (etm
->config
>> 13) & 0x07);
1486 command_print(CMD_CTX
, "sequencer %spresent",
1487 (int) (etm
->config
& (1 << 16)) ? "" : "not ");
1488 command_print(CMD_CTX
, "number of ext. inputs: %i",
1489 (int) (etm
->config
>> 17) & 0x07);
1490 command_print(CMD_CTX
, "number of ext. outputs: %i",
1491 (int) (etm
->config
>> 20) & 0x07);
1492 command_print(CMD_CTX
, "FIFO full %spresent",
1493 (int) (etm
->config
& (1 << 23)) ? "" : "not ");
1494 if (etm
->bcd_vers
< 0x20)
1495 command_print(CMD_CTX
, "protocol version: %i",
1496 (int) (etm
->config
>> 28) & 0x07);
1498 command_print(CMD_CTX
,
1499 "coprocessor and memory access %ssupported",
1500 (etm
->config
& (1 << 26)) ? "" : "not ");
1501 command_print(CMD_CTX
, "trace start/stop %spresent",
1502 (etm
->config
& (1 << 26)) ? "" : "not ");
1503 command_print(CMD_CTX
, "number of context comparators: %i",
1504 (int) (etm
->config
>> 24) & 0x03);
1507 /* SYS_CONFIG isn't present before ETMv1.2 */
1508 etm_sys_config_reg
= etm_reg_lookup(etm
, ETM_SYS_CONFIG
);
1509 if (!etm_sys_config_reg
)
1512 etm_get_reg(etm_sys_config_reg
);
1513 config
= buf_get_u32(etm_sys_config_reg
->value
, 0, 32);
1515 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config
);
1517 max_port_size
= config
& 0x7;
1518 if (etm
->bcd_vers
>= 0x30)
1519 max_port_size
|= (config
>> 6) & 0x08;
1520 switch (max_port_size
) {
1521 /* before ETMv3.0 */
1531 /* ETMv3.0 and later*/
1551 LOG_ERROR("Illegal max_port_size");
1554 command_print(CMD_CTX
, "max. port size: %i", max_port_size
);
1556 if (etm
->bcd_vers
< 0x30) {
1557 command_print(CMD_CTX
, "half-rate clocking %ssupported",
1558 (config
& (1 << 3)) ? "" : "not ");
1559 command_print(CMD_CTX
, "full-rate clocking %ssupported",
1560 (config
& (1 << 4)) ? "" : "not ");
1561 command_print(CMD_CTX
, "normal trace format %ssupported",
1562 (config
& (1 << 5)) ? "" : "not ");
1563 command_print(CMD_CTX
, "multiplex trace format %ssupported",
1564 (config
& (1 << 6)) ? "" : "not ");
1565 command_print(CMD_CTX
, "demultiplex trace format %ssupported",
1566 (config
& (1 << 7)) ? "" : "not ");
1568 /* REVISIT show which size and format are selected ... */
1569 command_print(CMD_CTX
, "current port size %ssupported",
1570 (config
& (1 << 10)) ? "" : "not ");
1571 command_print(CMD_CTX
, "current trace format %ssupported",
1572 (config
& (1 << 11)) ? "" : "not ");
1574 if (etm
->bcd_vers
>= 0x21)
1575 command_print(CMD_CTX
, "fetch comparisons %ssupported",
1576 (config
& (1 << 17)) ? "not " : "");
1577 command_print(CMD_CTX
, "FIFO full %ssupported",
1578 (config
& (1 << 8)) ? "" : "not ");
1583 COMMAND_HANDLER(handle_etm_status_command
)
1585 struct target
*target
;
1587 struct etm_context
*etm
;
1588 trace_status_t trace_status
;
1590 target
= get_current_target(CMD_CTX
);
1591 arm
= target_to_arm(target
);
1593 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1599 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1604 if (etm
->bcd_vers
>= 0x11) {
1607 reg
= etm_reg_lookup(etm
, ETM_STATUS
);
1610 if (etm_get_reg(reg
) == ERROR_OK
) {
1611 unsigned s
= buf_get_u32(reg
->value
, 0, reg
->size
);
1613 command_print(CMD_CTX
, "etm: %s%s%s%s",
1614 /* bit(1) == progbit */
1615 (etm
->bcd_vers
>= 0x12)
1617 ? "disabled" : "enabled")
1619 ((s
& (1 << 3)) && etm
->bcd_vers
>= 0x31)
1620 ? " triggered" : "",
1621 ((s
& (1 << 2)) && etm
->bcd_vers
>= 0x12)
1622 ? " start/stop" : "",
1623 ((s
& (1 << 0)) && etm
->bcd_vers
>= 0x11)
1624 ? " untraced-overflow" : "");
1625 } /* else ignore and try showing trace port status */
1628 /* Trace Port Driver status */
1629 trace_status
= etm
->capture_driver
->status(etm
);
1630 if (trace_status
== TRACE_IDLE
)
1631 command_print(CMD_CTX
, "%s: idle", etm
->capture_driver
->name
);
1633 static char *completed
= " completed";
1634 static char *running
= " is running";
1635 static char *overflowed
= ", overflowed";
1636 static char *triggered
= ", triggered";
1638 command_print(CMD_CTX
, "%s: trace collection%s%s%s",
1639 etm
->capture_driver
->name
,
1640 (trace_status
& TRACE_RUNNING
) ? running
: completed
,
1641 (trace_status
& TRACE_OVERFLOWED
) ? overflowed
: "",
1642 (trace_status
& TRACE_TRIGGERED
) ? triggered
: "");
1644 if (etm
->trace_depth
> 0) {
1645 command_print(CMD_CTX
, "%i frames of trace data read",
1646 (int)(etm
->trace_depth
));
1653 COMMAND_HANDLER(handle_etm_image_command
)
1655 struct target
*target
;
1657 struct etm_context
*etm_ctx
;
1660 return ERROR_COMMAND_SYNTAX_ERROR
;
1662 target
= get_current_target(CMD_CTX
);
1663 arm
= target_to_arm(target
);
1665 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1671 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1675 if (etm_ctx
->image
) {
1676 image_close(etm_ctx
->image
);
1677 free(etm_ctx
->image
);
1678 command_print(CMD_CTX
, "previously loaded image found and closed");
1681 etm_ctx
->image
= malloc(sizeof(struct image
));
1682 etm_ctx
->image
->base_address_set
= 0;
1683 etm_ctx
->image
->start_address_set
= 0;
1685 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1686 if (CMD_ARGC
>= 2) {
1687 etm_ctx
->image
->base_address_set
= 1;
1688 COMMAND_PARSE_NUMBER(llong
, CMD_ARGV
[1], etm_ctx
->image
->base_address
);
1690 etm_ctx
->image
->base_address_set
= 0;
1692 if (image_open(etm_ctx
->image
, CMD_ARGV
[0],
1693 (CMD_ARGC
>= 3) ? CMD_ARGV
[2] : NULL
) != ERROR_OK
) {
1694 free(etm_ctx
->image
);
1695 etm_ctx
->image
= NULL
;
1702 COMMAND_HANDLER(handle_etm_dump_command
)
1705 struct target
*target
;
1707 struct etm_context
*etm_ctx
;
1711 return ERROR_COMMAND_SYNTAX_ERROR
;
1713 target
= get_current_target(CMD_CTX
);
1714 arm
= target_to_arm(target
);
1716 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1722 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1726 if (etm_ctx
->capture_driver
->status
== TRACE_IDLE
) {
1727 command_print(CMD_CTX
, "trace capture wasn't enabled, no trace data captured");
1731 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
) {
1732 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1733 command_print(CMD_CTX
, "trace capture not completed");
1737 /* read the trace data if it wasn't read already */
1738 if (etm_ctx
->trace_depth
== 0)
1739 etm_ctx
->capture_driver
->read_trace(etm_ctx
);
1741 if (fileio_open(&file
, CMD_ARGV
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
1744 fileio_write_u32(&file
, etm_ctx
->capture_status
);
1745 fileio_write_u32(&file
, etm_ctx
->control
);
1746 fileio_write_u32(&file
, etm_ctx
->trace_depth
);
1748 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++) {
1749 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].pipestat
);
1750 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].packet
);
1751 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].flags
);
1754 fileio_close(&file
);
1759 COMMAND_HANDLER(handle_etm_load_command
)
1762 struct target
*target
;
1764 struct etm_context
*etm_ctx
;
1768 return ERROR_COMMAND_SYNTAX_ERROR
;
1770 target
= get_current_target(CMD_CTX
);
1771 arm
= target_to_arm(target
);
1773 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1779 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1783 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
) {
1784 command_print(CMD_CTX
, "trace capture running, stop first");
1788 if (fileio_open(&file
, CMD_ARGV
[0], FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1792 int retval
= fileio_size(&file
, &filesize
);
1793 if (retval
!= ERROR_OK
) {
1794 fileio_close(&file
);
1799 command_print(CMD_CTX
, "size isn't a multiple of 4, no valid trace data");
1800 fileio_close(&file
);
1804 if (etm_ctx
->trace_depth
> 0) {
1805 free(etm_ctx
->trace_data
);
1806 etm_ctx
->trace_data
= NULL
;
1811 fileio_read_u32(&file
, &tmp
); etm_ctx
->capture_status
= tmp
;
1812 fileio_read_u32(&file
, &tmp
); etm_ctx
->control
= tmp
;
1813 fileio_read_u32(&file
, &etm_ctx
->trace_depth
);
1815 etm_ctx
->trace_data
= malloc(sizeof(struct etmv1_trace_data
) * etm_ctx
->trace_depth
);
1816 if (etm_ctx
->trace_data
== NULL
) {
1817 command_print(CMD_CTX
, "not enough memory to perform operation");
1818 fileio_close(&file
);
1822 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++) {
1823 uint32_t pipestat
, packet
, flags
;
1824 fileio_read_u32(&file
, &pipestat
);
1825 fileio_read_u32(&file
, &packet
);
1826 fileio_read_u32(&file
, &flags
);
1827 etm_ctx
->trace_data
[i
].pipestat
= pipestat
& 0xff;
1828 etm_ctx
->trace_data
[i
].packet
= packet
& 0xffff;
1829 etm_ctx
->trace_data
[i
].flags
= flags
;
1832 fileio_close(&file
);
1837 COMMAND_HANDLER(handle_etm_start_command
)
1839 struct target
*target
;
1841 struct etm_context
*etm_ctx
;
1842 struct reg
*etm_ctrl_reg
;
1844 target
= get_current_target(CMD_CTX
);
1845 arm
= target_to_arm(target
);
1847 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1853 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1857 /* invalidate old tracing data */
1858 etm_ctx
->capture_status
= TRACE_IDLE
;
1859 if (etm_ctx
->trace_depth
> 0) {
1860 free(etm_ctx
->trace_data
);
1861 etm_ctx
->trace_data
= NULL
;
1863 etm_ctx
->trace_depth
= 0;
1865 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
1869 etm_get_reg(etm_ctrl_reg
);
1871 /* Clear programming bit (10), set port selection bit (11) */
1872 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x2);
1874 etm_store_reg(etm_ctrl_reg
);
1875 jtag_execute_queue();
1877 etm_ctx
->capture_driver
->start_capture(etm_ctx
);
1882 COMMAND_HANDLER(handle_etm_stop_command
)
1884 struct target
*target
;
1886 struct etm_context
*etm_ctx
;
1887 struct reg
*etm_ctrl_reg
;
1889 target
= get_current_target(CMD_CTX
);
1890 arm
= target_to_arm(target
);
1892 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1898 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1902 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
1906 etm_get_reg(etm_ctrl_reg
);
1908 /* Set programming bit (10), clear port selection bit (11) */
1909 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x1);
1911 etm_store_reg(etm_ctrl_reg
);
1912 jtag_execute_queue();
1914 etm_ctx
->capture_driver
->stop_capture(etm_ctx
);
1919 COMMAND_HANDLER(handle_etm_trigger_debug_command
)
1921 struct target
*target
;
1923 struct etm_context
*etm
;
1925 target
= get_current_target(CMD_CTX
);
1926 arm
= target_to_arm(target
);
1928 command_print(CMD_CTX
, "ETM: %s isn't an ARM",
1929 target_name(target
));
1935 command_print(CMD_CTX
, "ETM: no ETM configured for %s",
1936 target_name(target
));
1940 if (CMD_ARGC
== 1) {
1941 struct reg
*etm_ctrl_reg
;
1944 etm_ctrl_reg
= etm_reg_lookup(etm
, ETM_CTRL
);
1948 COMMAND_PARSE_ENABLE(CMD_ARGV
[0], dbgrq
);
1950 etm
->control
|= ETM_CTRL_DBGRQ
;
1952 etm
->control
&= ~ETM_CTRL_DBGRQ
;
1954 /* etm->control will be written to hardware
1955 * the next time an "etm start" is issued.
1957 buf_set_u32(etm_ctrl_reg
->value
, 0, 32, etm
->control
);
1960 command_print(CMD_CTX
, "ETM: %s debug halt",
1961 (etm
->control
& ETM_CTRL_DBGRQ
)
1963 : "does not trigger");
1967 COMMAND_HANDLER(handle_etm_analyze_command
)
1969 struct target
*target
;
1971 struct etm_context
*etm_ctx
;
1974 target
= get_current_target(CMD_CTX
);
1975 arm
= target_to_arm(target
);
1977 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1983 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1987 retval
= etmv1_analyze_trace(etm_ctx
, CMD_CTX
);
1988 if (retval
!= ERROR_OK
) {
1989 /* FIX! error should be reported inside etmv1_analyze_trace() */
1991 case ERROR_ETM_ANALYSIS_FAILED
:
1992 command_print(CMD_CTX
,
1993 "further analysis failed (corrupted trace data or just end of data");
1995 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE
:
1996 command_print(CMD_CTX
,
1997 "no instruction for current address available, analysis aborted");
1999 case ERROR_TRACE_IMAGE_UNAVAILABLE
:
2000 command_print(CMD_CTX
, "no image available for trace analysis");
2003 command_print(CMD_CTX
, "unknown error");
2010 static const struct command_registration etm_config_command_handlers
[] = {
2012 /* NOTE: with ADIv5, ETMs are accessed by DAP operations,
2013 * possibly over SWD, not JTAG scanchain 6 of 'target'.
2015 * Also, these parameters don't match ETM v3+ modules...
2018 .handler
= handle_etm_config_command
,
2019 .mode
= COMMAND_CONFIG
,
2020 .help
= "Set up ETM output port.",
2021 .usage
= "target port_width port_mode clocking capture_driver",
2023 COMMAND_REGISTRATION_DONE
2025 const struct command_registration etm_command_handlers
[] = {
2028 .mode
= COMMAND_ANY
,
2029 .help
= "Embedded Trace Macrocell command group",
2031 .chain
= etm_config_command_handlers
,
2033 COMMAND_REGISTRATION_DONE
2036 static const struct command_registration etm_exec_command_handlers
[] = {
2038 .name
= "tracemode",
2039 .handler
= handle_etm_tracemode_command
,
2040 .mode
= COMMAND_EXEC
,
2041 .help
= "configure/display trace mode",
2042 .usage
= "('none'|'data'|'address'|'all') "
2044 "['enable'|'disable'] "
2045 "['enable'|'disable']",
2049 .handler
= handle_etm_info_command
,
2050 .mode
= COMMAND_EXEC
,
2052 .help
= "display info about the current target's ETM",
2056 .handler
= handle_etm_status_command
,
2057 .mode
= COMMAND_EXEC
,
2059 .help
= "display current target's ETM status",
2063 .handler
= handle_etm_start_command
,
2064 .mode
= COMMAND_EXEC
,
2066 .help
= "start ETM trace collection",
2070 .handler
= handle_etm_stop_command
,
2071 .mode
= COMMAND_EXEC
,
2073 .help
= "stop ETM trace collection",
2076 .name
= "trigger_debug",
2077 .handler
= handle_etm_trigger_debug_command
,
2078 .mode
= COMMAND_EXEC
,
2079 .help
= "enable/disable debug entry on trigger",
2080 .usage
= "['enable'|'disable']",
2084 .handler
= handle_etm_analyze_command
,
2085 .mode
= COMMAND_EXEC
,
2087 .help
= "analyze collected ETM trace",
2091 .handler
= handle_etm_image_command
,
2092 .mode
= COMMAND_EXEC
,
2093 .help
= "load image from file with optional offset",
2094 .usage
= "<file> [base address] [type]",
2098 .handler
= handle_etm_dump_command
,
2099 .mode
= COMMAND_EXEC
,
2100 .help
= "dump captured trace data to file",
2101 .usage
= "filename",
2105 .handler
= handle_etm_load_command
,
2106 .mode
= COMMAND_EXEC
,
2108 .help
= "load trace data for analysis <file>",
2110 COMMAND_REGISTRATION_DONE
2113 static int etm_register_user_commands(struct command_context
*cmd_ctx
)
2115 struct command
*etm_cmd
= command_find_in_context(cmd_ctx
, "etm");
2116 return register_commands(cmd_ctx
, etm_cmd
, etm_exec_command_handlers
);
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