1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "embeddedice.h"
27 #include "arm7_9_common.h"
32 #include "binarybuffer.h"
39 bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc
[] =
47 int embeddedice_reg_arch_info
[] =
50 0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
51 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
55 char* embeddedice_reg_list
[] =
67 "watch 0 control value",
68 "watch 0 control mask",
74 "watch 1 control value",
75 "watch 1 control mask",
80 int embeddedice_reg_arch_type
= -1;
82 int embeddedice_get_reg(reg_t
*reg
);
83 int embeddedice_set_reg(reg_t
*reg
, u32 value
);
84 int embeddedice_set_reg_w_exec(reg_t
*reg
, u8
*buf
);
86 int embeddedice_write_reg(reg_t
*reg
, u32 value
);
87 int embeddedice_read_reg(reg_t
*reg
);
89 reg_cache_t
* embeddedice_build_reg_cache(target_t
*target
, arm7_9_common_t
*arm7_9
)
91 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
92 reg_t
*reg_list
= NULL
;
93 embeddedice_reg_t
*arch_info
= NULL
;
94 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
99 /* register a register arch-type for EmbeddedICE registers only once */
100 if (embeddedice_reg_arch_type
== -1)
101 embeddedice_reg_arch_type
= register_reg_arch_type(embeddedice_get_reg
, embeddedice_set_reg_w_exec
);
103 if (arm7_9
->has_vector_catch
)
108 /* the actual registers are kept in two arrays */
109 reg_list
= calloc(num_regs
, sizeof(reg_t
));
110 arch_info
= calloc(num_regs
, sizeof(embeddedice_reg_t
));
112 /* fill in values for the reg cache */
113 reg_cache
->name
= "EmbeddedICE registers";
114 reg_cache
->next
= NULL
;
115 reg_cache
->reg_list
= reg_list
;
116 reg_cache
->num_regs
= num_regs
;
118 /* set up registers */
119 for (i
= 0; i
< num_regs
; i
++)
121 reg_list
[i
].name
= embeddedice_reg_list
[i
];
122 reg_list
[i
].size
= 32;
123 reg_list
[i
].dirty
= 0;
124 reg_list
[i
].valid
= 0;
125 reg_list
[i
].bitfield_desc
= NULL
;
126 reg_list
[i
].num_bitfields
= 0;
127 reg_list
[i
].value
= calloc(1, 4);
128 reg_list
[i
].arch_info
= &arch_info
[i
];
129 reg_list
[i
].arch_type
= embeddedice_reg_arch_type
;
130 arch_info
[i
].addr
= embeddedice_reg_arch_info
[i
];
131 arch_info
[i
].jtag_info
= jtag_info
;
134 /* identify EmbeddedICE version by reading DCC control register */
135 embeddedice_read_reg(®_list
[EICE_COMMS_CTRL
]);
136 jtag_execute_queue();
138 eice_version
= buf_get_u32(reg_list
[EICE_COMMS_CTRL
].value
, 28, 4);
140 switch (eice_version
)
143 reg_list
[EICE_DBG_CTRL
].size
= 3;
144 reg_list
[EICE_DBG_STAT
].size
= 5;
147 reg_list
[EICE_DBG_CTRL
].size
= 4;
148 reg_list
[EICE_DBG_STAT
].size
= 5;
149 arm7_9
->has_single_step
= 1;
152 ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
153 reg_list
[EICE_DBG_CTRL
].size
= 6;
154 reg_list
[EICE_DBG_STAT
].size
= 5;
155 arm7_9
->has_single_step
= 1;
156 arm7_9
->has_monitor_mode
= 1;
159 reg_list
[EICE_DBG_CTRL
].size
= 6;
160 reg_list
[EICE_DBG_STAT
].size
= 5;
161 arm7_9
->has_monitor_mode
= 1;
164 reg_list
[EICE_DBG_CTRL
].size
= 6;
165 reg_list
[EICE_DBG_STAT
].size
= 5;
166 arm7_9
->has_single_step
= 1;
167 arm7_9
->has_monitor_mode
= 1;
170 reg_list
[EICE_DBG_CTRL
].size
= 6;
171 reg_list
[EICE_DBG_STAT
].size
= 10;
172 arm7_9
->has_monitor_mode
= 1;
175 ERROR("unknown EmbeddedICE version (comms ctrl: 0x%4.4x)", buf_get_u32(reg_list
[EICE_COMMS_CTRL
].value
, 0, 32));
181 int embeddedice_get_reg(reg_t
*reg
)
183 if (embeddedice_read_reg(reg
) != ERROR_OK
)
185 ERROR("BUG: error scheduling EmbeddedICE register read");
189 if (jtag_execute_queue() != ERROR_OK
)
191 ERROR("register read failed");
197 int embeddedice_read_reg_w_check(reg_t
*reg
, u8
* check_value
, u8
* check_mask
)
199 embeddedice_reg_t
*ice_reg
= reg
->arch_info
;
200 u8 reg_addr
= ice_reg
->addr
& 0x1f;
201 scan_field_t fields
[3];
203 DEBUG("%i", ice_reg
->addr
);
205 jtag_add_end_state(TAP_RTI
);
206 arm_jtag_scann(ice_reg
->jtag_info
, 0x2);
207 arm_jtag_set_instr(ice_reg
->jtag_info
, ice_reg
->jtag_info
->intest_instr
);
209 fields
[0].device
= ice_reg
->jtag_info
->chain_pos
;
210 fields
[0].num_bits
= 32;
211 fields
[0].out_value
= reg
->value
;
212 fields
[0].out_mask
= NULL
;
213 fields
[0].in_value
= NULL
;
214 fields
[0].in_check_value
= NULL
;
215 fields
[0].in_check_mask
= NULL
;
216 fields
[0].in_handler
= NULL
;
217 fields
[0].in_handler_priv
= NULL
;
219 fields
[1].device
= ice_reg
->jtag_info
->chain_pos
;
220 fields
[1].num_bits
= 5;
221 fields
[1].out_value
= malloc(1);
222 buf_set_u32(fields
[1].out_value
, 0, 5, reg_addr
);
223 fields
[1].out_mask
= NULL
;
224 fields
[1].in_value
= NULL
;
225 fields
[1].in_check_value
= NULL
;
226 fields
[1].in_check_mask
= NULL
;
227 fields
[1].in_handler
= NULL
;
228 fields
[1].in_handler_priv
= NULL
;
230 fields
[2].device
= ice_reg
->jtag_info
->chain_pos
;
231 fields
[2].num_bits
= 1;
232 fields
[2].out_value
= malloc(1);
233 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
234 fields
[2].out_mask
= NULL
;
235 fields
[2].in_value
= NULL
;
236 fields
[2].in_check_value
= NULL
;
237 fields
[2].in_check_mask
= NULL
;
238 fields
[2].in_handler
= NULL
;
239 fields
[2].in_handler_priv
= NULL
;
241 jtag_add_dr_scan(3, fields
, -1);
243 fields
[0].in_value
= reg
->value
;
244 fields
[0].in_check_value
= check_value
;
245 fields
[0].in_check_mask
= check_mask
;
247 /* when reading the DCC data register, leaving the address field set to
248 * EICE_COMMS_DATA would read the register twice
249 * reading the control register is safe
251 buf_set_u32(fields
[1].out_value
, 0, 5, embeddedice_reg_arch_info
[EICE_COMMS_CTRL
]);
253 jtag_add_dr_scan(3, fields
, -1);
255 free(fields
[1].out_value
);
256 free(fields
[2].out_value
);
261 int embeddedice_read_reg(reg_t
*reg
)
263 return embeddedice_read_reg_w_check(reg
, NULL
, NULL
);
266 int embeddedice_set_reg(reg_t
*reg
, u32 value
)
268 if (embeddedice_write_reg(reg
, value
) != ERROR_OK
)
270 ERROR("BUG: error scheduling EmbeddedICE register write");
274 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
281 int embeddedice_set_reg_w_exec(reg_t
*reg
, u8
*buf
)
283 embeddedice_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
285 if (jtag_execute_queue() != ERROR_OK
)
287 ERROR("register write failed");
293 int embeddedice_write_reg(reg_t
*reg
, u32 value
)
295 embeddedice_reg_t
*ice_reg
= reg
->arch_info
;
296 u8 reg_addr
= ice_reg
->addr
& 0x1f;
297 scan_field_t fields
[3];
299 DEBUG("%i: 0x%8.8x", ice_reg
->addr
, value
);
301 jtag_add_end_state(TAP_RTI
);
302 arm_jtag_scann(ice_reg
->jtag_info
, 0x2);
303 arm_jtag_set_instr(ice_reg
->jtag_info
, ice_reg
->jtag_info
->intest_instr
);
305 fields
[0].device
= ice_reg
->jtag_info
->chain_pos
;
306 fields
[0].num_bits
= 32;
307 fields
[0].out_value
= malloc(4);
308 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
309 fields
[0].out_mask
= NULL
;
310 fields
[0].in_value
= NULL
;
311 fields
[0].in_check_value
= NULL
;
312 fields
[0].in_check_mask
= NULL
;
313 fields
[0].in_handler
= NULL
;
314 fields
[0].in_handler_priv
= NULL
;
316 fields
[1].device
= ice_reg
->jtag_info
->chain_pos
;
317 fields
[1].num_bits
= 5;
318 fields
[1].out_value
= malloc(1);
319 buf_set_u32(fields
[1].out_value
, 0, 5, reg_addr
);
320 fields
[1].out_mask
= NULL
;
321 fields
[1].in_value
= NULL
;
322 fields
[1].in_check_value
= NULL
;
323 fields
[1].in_check_mask
= NULL
;
324 fields
[1].in_handler
= NULL
;
325 fields
[1].in_handler_priv
= NULL
;
327 fields
[2].device
= ice_reg
->jtag_info
->chain_pos
;
328 fields
[2].num_bits
= 1;
329 fields
[2].out_value
= malloc(1);
330 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
331 fields
[2].out_mask
= NULL
;
332 fields
[2].in_value
= NULL
;
333 fields
[2].in_check_value
= NULL
;
334 fields
[2].in_check_mask
= NULL
;
335 fields
[2].in_handler
= NULL
;
336 fields
[2].in_handler_priv
= NULL
;
338 jtag_add_dr_scan(3, fields
, -1);
340 free(fields
[0].out_value
);
341 free(fields
[1].out_value
);
342 free(fields
[2].out_value
);
347 int embeddedice_store_reg(reg_t
*reg
)
349 return embeddedice_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
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