1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
30 #include "embeddedice.h"
33 #include "arm7_9_common.h"
38 #include "binarybuffer.h"
45 bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc
[] =
53 int embeddedice_reg_arch_info
[] =
56 0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
57 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
61 char* embeddedice_reg_list
[] =
73 "watch 0 control value",
74 "watch 0 control mask",
80 "watch 1 control value",
81 "watch 1 control mask",
86 int embeddedice_reg_arch_type
= -1;
88 int embeddedice_get_reg(reg_t
*reg
);
89 void embeddedice_set_reg(reg_t
*reg
, u32 value
);
90 int embeddedice_set_reg_w_exec(reg_t
*reg
, u8
*buf
);
92 void embeddedice_write_reg(reg_t
*reg
, u32 value
);
93 int embeddedice_read_reg(reg_t
*reg
);
95 reg_cache_t
* embeddedice_build_reg_cache(target_t
*target
, arm7_9_common_t
*arm7_9
)
98 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
99 reg_t
*reg_list
= NULL
;
100 embeddedice_reg_t
*arch_info
= NULL
;
101 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
104 int eice_version
= 0;
106 /* register a register arch-type for EmbeddedICE registers only once */
107 if (embeddedice_reg_arch_type
== -1)
108 embeddedice_reg_arch_type
= register_reg_arch_type(embeddedice_get_reg
, embeddedice_set_reg_w_exec
);
110 if (arm7_9
->has_vector_catch
)
115 /* the actual registers are kept in two arrays */
116 reg_list
= calloc(num_regs
, sizeof(reg_t
));
117 arch_info
= calloc(num_regs
, sizeof(embeddedice_reg_t
));
119 /* fill in values for the reg cache */
120 reg_cache
->name
= "EmbeddedICE registers";
121 reg_cache
->next
= NULL
;
122 reg_cache
->reg_list
= reg_list
;
123 reg_cache
->num_regs
= num_regs
;
125 /* set up registers */
126 for (i
= 0; i
< num_regs
; i
++)
128 reg_list
[i
].name
= embeddedice_reg_list
[i
];
129 reg_list
[i
].size
= 32;
130 reg_list
[i
].dirty
= 0;
131 reg_list
[i
].valid
= 0;
132 reg_list
[i
].bitfield_desc
= NULL
;
133 reg_list
[i
].num_bitfields
= 0;
134 reg_list
[i
].value
= calloc(1, 4);
135 reg_list
[i
].arch_info
= &arch_info
[i
];
136 reg_list
[i
].arch_type
= embeddedice_reg_arch_type
;
137 arch_info
[i
].addr
= embeddedice_reg_arch_info
[i
];
138 arch_info
[i
].jtag_info
= jtag_info
;
141 /* identify EmbeddedICE version by reading DCC control register */
142 embeddedice_read_reg(®_list
[EICE_COMMS_CTRL
]);
143 if ((retval
=jtag_execute_queue())!=ERROR_OK
)
145 for (i
= 0; i
< num_regs
; i
++)
147 free(reg_list
[i
].value
);
154 eice_version
= buf_get_u32(reg_list
[EICE_COMMS_CTRL
].value
, 28, 4);
156 switch (eice_version
)
159 reg_list
[EICE_DBG_CTRL
].size
= 3;
160 reg_list
[EICE_DBG_STAT
].size
= 5;
163 reg_list
[EICE_DBG_CTRL
].size
= 4;
164 reg_list
[EICE_DBG_STAT
].size
= 5;
165 arm7_9
->has_single_step
= 1;
168 LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
169 reg_list
[EICE_DBG_CTRL
].size
= 6;
170 reg_list
[EICE_DBG_STAT
].size
= 5;
171 arm7_9
->has_single_step
= 1;
172 arm7_9
->has_monitor_mode
= 1;
175 reg_list
[EICE_DBG_CTRL
].size
= 6;
176 reg_list
[EICE_DBG_STAT
].size
= 5;
177 arm7_9
->has_monitor_mode
= 1;
180 reg_list
[EICE_DBG_CTRL
].size
= 6;
181 reg_list
[EICE_DBG_STAT
].size
= 5;
182 arm7_9
->has_single_step
= 1;
183 arm7_9
->has_monitor_mode
= 1;
186 reg_list
[EICE_DBG_CTRL
].size
= 6;
187 reg_list
[EICE_DBG_STAT
].size
= 10;
188 arm7_9
->has_monitor_mode
= 1;
191 LOG_WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
192 reg_list
[EICE_DBG_CTRL
].size
= 6;
193 reg_list
[EICE_DBG_STAT
].size
= 5;
194 arm7_9
->has_monitor_mode
= 1;
197 LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list
[EICE_COMMS_CTRL
].value
, 0, 32));
203 int embeddedice_setup(target_t
*target
)
206 armv4_5_common_t
*armv4_5
= target
->arch_info
;
207 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
209 /* explicitly disable monitor mode */
210 if (arm7_9
->has_monitor_mode
)
212 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
214 embeddedice_read_reg(dbg_ctrl
);
215 if ((retval
=jtag_execute_queue())!=ERROR_OK
)
217 buf_set_u32(dbg_ctrl
->value
, 4, 1, 0);
218 embeddedice_set_reg_w_exec(dbg_ctrl
, dbg_ctrl
->value
);
220 return jtag_execute_queue();
223 int embeddedice_get_reg(reg_t
*reg
)
226 if ((retval
= embeddedice_read_reg(reg
)) != ERROR_OK
)
228 LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
232 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
234 LOG_ERROR("register read failed");
241 int embeddedice_read_reg_w_check(reg_t
*reg
, u8
* check_value
, u8
* check_mask
)
243 embeddedice_reg_t
*ice_reg
= reg
->arch_info
;
244 u8 reg_addr
= ice_reg
->addr
& 0x1f;
245 scan_field_t fields
[3];
249 jtag_add_end_state(TAP_RTI
);
250 arm_jtag_scann(ice_reg
->jtag_info
, 0x2);
252 arm_jtag_set_instr(ice_reg
->jtag_info
, ice_reg
->jtag_info
->intest_instr
, NULL
);
254 fields
[0].device
= ice_reg
->jtag_info
->chain_pos
;
255 fields
[0].num_bits
= 32;
256 fields
[0].out_value
= reg
->value
;
257 fields
[0].out_mask
= NULL
;
258 fields
[0].in_value
= NULL
;
259 fields
[0].in_check_value
= NULL
;
260 fields
[0].in_check_mask
= NULL
;
261 fields
[0].in_handler
= NULL
;
262 fields
[0].in_handler_priv
= NULL
;
264 fields
[1].device
= ice_reg
->jtag_info
->chain_pos
;
265 fields
[1].num_bits
= 5;
266 fields
[1].out_value
= field1_out
;
267 buf_set_u32(fields
[1].out_value
, 0, 5, reg_addr
);
268 fields
[1].out_mask
= NULL
;
269 fields
[1].in_value
= NULL
;
270 fields
[1].in_check_value
= NULL
;
271 fields
[1].in_check_mask
= NULL
;
272 fields
[1].in_handler
= NULL
;
273 fields
[1].in_handler_priv
= NULL
;
275 fields
[2].device
= ice_reg
->jtag_info
->chain_pos
;
276 fields
[2].num_bits
= 1;
277 fields
[2].out_value
= field2_out
;
278 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
279 fields
[2].out_mask
= NULL
;
280 fields
[2].in_value
= NULL
;
281 fields
[2].in_check_value
= NULL
;
282 fields
[2].in_check_mask
= NULL
;
283 fields
[2].in_handler
= NULL
;
284 fields
[2].in_handler_priv
= NULL
;
286 jtag_add_dr_scan(3, fields
, -1);
288 fields
[0].in_value
= reg
->value
;
289 jtag_set_check_value(fields
+0, check_value
, check_mask
, NULL
);
291 /* when reading the DCC data register, leaving the address field set to
292 * EICE_COMMS_DATA would read the register twice
293 * reading the control register is safe
295 buf_set_u32(fields
[1].out_value
, 0, 5, embeddedice_reg_arch_info
[EICE_COMMS_CTRL
]);
297 jtag_add_dr_scan(3, fields
, -1);
302 /* receive <size> words of 32 bit from the DCC
303 * we pretend the target is always going to be fast enough
304 * (relative to the JTAG clock), so we don't need to handshake
306 int embeddedice_receive(arm_jtag_t
*jtag_info
, u32
*data
, u32 size
)
308 scan_field_t fields
[3];
312 jtag_add_end_state(TAP_RTI
);
313 arm_jtag_scann(jtag_info
, 0x2);
314 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
316 fields
[0].device
= jtag_info
->chain_pos
;
317 fields
[0].num_bits
= 32;
318 fields
[0].out_value
= NULL
;
319 fields
[0].out_mask
= NULL
;
320 fields
[0].in_value
= NULL
;
321 fields
[0].in_check_value
= NULL
;
322 fields
[0].in_check_mask
= NULL
;
323 fields
[0].in_handler
= NULL
;
324 fields
[0].in_handler_priv
= NULL
;
326 fields
[1].device
= jtag_info
->chain_pos
;
327 fields
[1].num_bits
= 5;
328 fields
[1].out_value
= field1_out
;
329 buf_set_u32(fields
[1].out_value
, 0, 5, embeddedice_reg_arch_info
[EICE_COMMS_DATA
]);
330 fields
[1].out_mask
= NULL
;
331 fields
[1].in_value
= NULL
;
332 fields
[1].in_check_value
= NULL
;
333 fields
[1].in_check_mask
= NULL
;
334 fields
[1].in_handler
= NULL
;
335 fields
[1].in_handler_priv
= NULL
;
337 fields
[2].device
= jtag_info
->chain_pos
;
338 fields
[2].num_bits
= 1;
339 fields
[2].out_value
= field2_out
;
340 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
341 fields
[2].out_mask
= NULL
;
342 fields
[2].in_value
= NULL
;
343 fields
[2].in_check_value
= NULL
;
344 fields
[2].in_check_mask
= NULL
;
345 fields
[2].in_handler
= NULL
;
346 fields
[2].in_handler_priv
= NULL
;
348 jtag_add_dr_scan(3, fields
, -1);
352 /* when reading the last item, set the register address to the DCC control reg,
353 * to avoid reading additional data from the DCC data reg
356 buf_set_u32(fields
[1].out_value
, 0, 5, embeddedice_reg_arch_info
[EICE_COMMS_CTRL
]);
358 fields
[0].in_handler
= arm_jtag_buf_to_u32
;
359 fields
[0].in_handler_priv
= data
;
360 jtag_add_dr_scan(3, fields
, -1);
366 return jtag_execute_queue();
369 int embeddedice_read_reg(reg_t
*reg
)
371 return embeddedice_read_reg_w_check(reg
, NULL
, NULL
);
374 void embeddedice_set_reg(reg_t
*reg
, u32 value
)
376 embeddedice_write_reg(reg
, value
);
378 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
384 int embeddedice_set_reg_w_exec(reg_t
*reg
, u8
*buf
)
387 embeddedice_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
389 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
391 LOG_ERROR("register write failed");
397 void embeddedice_write_reg(reg_t
*reg
, u32 value
)
399 embeddedice_reg_t
*ice_reg
= reg
->arch_info
;
401 LOG_DEBUG("%i: 0x%8.8x", ice_reg
->addr
, value
);
403 jtag_add_end_state(TAP_RTI
);
404 arm_jtag_scann(ice_reg
->jtag_info
, 0x2);
406 arm_jtag_set_instr(ice_reg
->jtag_info
, ice_reg
->jtag_info
->intest_instr
, NULL
);
408 u8 reg_addr
= ice_reg
->addr
& 0x1f;
409 embeddedice_write_reg_inner(ice_reg
->jtag_info
->chain_pos
, reg_addr
, value
);
413 void embeddedice_store_reg(reg_t
*reg
)
415 embeddedice_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
418 /* send <size> words of 32 bit to the DCC
419 * we pretend the target is always going to be fast enough
420 * (relative to the JTAG clock), so we don't need to handshake
422 int embeddedice_send(arm_jtag_t
*jtag_info
, u32
*data
, u32 size
)
424 scan_field_t fields
[3];
429 jtag_add_end_state(TAP_RTI
);
430 arm_jtag_scann(jtag_info
, 0x2);
431 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
433 fields
[0].device
= jtag_info
->chain_pos
;
434 fields
[0].num_bits
= 32;
435 fields
[0].out_value
= field0_out
;
436 fields
[0].out_mask
= NULL
;
437 fields
[0].in_value
= NULL
;
438 fields
[0].in_check_value
= NULL
;
439 fields
[0].in_check_mask
= NULL
;
440 fields
[0].in_handler
= NULL
;
441 fields
[0].in_handler_priv
= NULL
;
443 fields
[1].device
= jtag_info
->chain_pos
;
444 fields
[1].num_bits
= 5;
445 fields
[1].out_value
= field1_out
;
446 buf_set_u32(fields
[1].out_value
, 0, 5, embeddedice_reg_arch_info
[EICE_COMMS_DATA
]);
447 fields
[1].out_mask
= NULL
;
448 fields
[1].in_value
= NULL
;
449 fields
[1].in_check_value
= NULL
;
450 fields
[1].in_check_mask
= NULL
;
451 fields
[1].in_handler
= NULL
;
452 fields
[1].in_handler_priv
= NULL
;
454 fields
[2].device
= jtag_info
->chain_pos
;
455 fields
[2].num_bits
= 1;
456 fields
[2].out_value
= field2_out
;
457 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
458 fields
[2].out_mask
= NULL
;
459 fields
[2].in_value
= NULL
;
460 fields
[2].in_check_value
= NULL
;
461 fields
[2].in_check_mask
= NULL
;
462 fields
[2].in_handler
= NULL
;
463 fields
[2].in_handler_priv
= NULL
;
467 buf_set_u32(fields
[0].out_value
, 0, 32, *data
);
468 jtag_add_dr_scan(3, fields
, -1);
474 /* call to jtag_execute_queue() intentionally omitted */
478 /* wait for DCC control register R/W handshake bit to become active
480 int embeddedice_handshake(arm_jtag_t
*jtag_info
, int hsbit
, u32 timeout
)
482 scan_field_t fields
[3];
491 if (hsbit
== EICE_COMM_CTRL_WBIT
)
493 else if (hsbit
== EICE_COMM_CTRL_RBIT
)
496 return ERROR_INVALID_ARGUMENTS
;
498 jtag_add_end_state(TAP_RTI
);
499 arm_jtag_scann(jtag_info
, 0x2);
500 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
502 fields
[0].device
= jtag_info
->chain_pos
;
503 fields
[0].num_bits
= 32;
504 fields
[0].out_value
= NULL
;
505 fields
[0].out_mask
= NULL
;
506 fields
[0].in_value
= field0_in
;
507 fields
[0].in_check_value
= NULL
;
508 fields
[0].in_check_mask
= NULL
;
509 fields
[0].in_handler
= NULL
;
510 fields
[0].in_handler_priv
= NULL
;
512 fields
[1].device
= jtag_info
->chain_pos
;
513 fields
[1].num_bits
= 5;
514 fields
[1].out_value
= field1_out
;
515 buf_set_u32(fields
[1].out_value
, 0, 5, embeddedice_reg_arch_info
[EICE_COMMS_CTRL
]);
516 fields
[1].out_mask
= NULL
;
517 fields
[1].in_value
= NULL
;
518 fields
[1].in_check_value
= NULL
;
519 fields
[1].in_check_mask
= NULL
;
520 fields
[1].in_handler
= NULL
;
521 fields
[1].in_handler_priv
= NULL
;
523 fields
[2].device
= jtag_info
->chain_pos
;
524 fields
[2].num_bits
= 1;
525 fields
[2].out_value
= field2_out
;
526 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
527 fields
[2].out_mask
= NULL
;
528 fields
[2].in_value
= NULL
;
529 fields
[2].in_check_value
= NULL
;
530 fields
[2].in_check_mask
= NULL
;
531 fields
[2].in_handler
= NULL
;
532 fields
[2].in_handler_priv
= NULL
;
534 jtag_add_dr_scan(3, fields
, -1);
535 gettimeofday(&lap
, NULL
);
538 jtag_add_dr_scan(3, fields
, -1);
539 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
542 if (buf_get_u32(field0_in
, hsbit
, 1) == hsact
)
545 gettimeofday(&now
, NULL
);
547 while ((now
.tv_sec
-lap
.tv_sec
)*1000 + (now
.tv_usec
-lap
.tv_usec
)/1000 <= timeout
);
549 return ERROR_TARGET_TIMEOUT
;
552 /* this is the inner loop of the open loop DCC write of data to target */
553 void MINIDRIVER(embeddedice_write_dcc
)(int chain_pos
, int reg_addr
, u8
*buffer
, int little
, int count
)
556 for (i
= 0; i
< count
; i
++)
558 embeddedice_write_reg_inner(chain_pos
, reg_addr
, fast_target_buffer_get_u32(buffer
, little
));
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