1 /***************************************************************************
2 * Copyright (C) 2009-2011 by Mathias Kuester *
3 * mkdorg@users.sourceforge.net *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "target_type.h"
28 #include "algorithm.h"
31 #include "dsp563xx_once.h"
33 #define ASM_REG_W_R0 0x60F400
34 #define ASM_REG_W_R1 0x61F400
35 #define ASM_REG_W_R2 0x62F400
36 #define ASM_REG_W_R3 0x63F400
37 #define ASM_REG_W_R4 0x64F400
38 #define ASM_REG_W_R5 0x65F400
39 #define ASM_REG_W_R6 0x66F400
40 #define ASM_REG_W_R7 0x67F400
42 #define ASM_REG_W_N0 0x70F400
43 #define ASM_REG_W_N1 0x71F400
44 #define ASM_REG_W_N2 0x72F400
45 #define ASM_REG_W_N3 0x73F400
46 #define ASM_REG_W_N4 0x74F400
47 #define ASM_REG_W_N5 0x75F400
48 #define ASM_REG_W_N6 0x76F400
49 #define ASM_REG_W_N7 0x77F400
51 #define ASM_REG_W_M0 0x05F420
52 #define ASM_REG_W_M1 0x05F421
53 #define ASM_REG_W_M2 0x05F422
54 #define ASM_REG_W_M3 0x05F423
55 #define ASM_REG_W_M4 0x05F424
56 #define ASM_REG_W_M5 0x05F425
57 #define ASM_REG_W_M6 0x05F426
58 #define ASM_REG_W_M7 0x05F427
60 #define ASM_REG_W_X0 0x44F400
61 #define ASM_REG_W_X1 0x45F400
63 #define ASM_REG_W_Y0 0x46F400
64 #define ASM_REG_W_Y1 0x47F400
66 #define ASM_REG_W_A0 0x50F400
67 #define ASM_REG_W_A1 0x54F400
68 #define ASM_REG_W_A2 0x52F400
70 #define ASM_REG_W_B0 0x51F400
71 #define ASM_REG_W_B1 0x55F400
72 #define ASM_REG_W_B2 0x53F400
74 #define ASM_REG_W_VBA 0x05F430
75 #define ASM_REG_W_OMR 0x05F43A
76 #define ASM_REG_W_EP 0x05F42A
77 #define ASM_REG_W_SC 0x05F431
78 #define ASM_REG_W_SZ 0x05F438
79 #define ASM_REG_W_SR 0x05F439
80 #define ASM_REG_W_SP 0x05F43B
81 #define ASM_REG_W_SSH 0x05F43C
82 #define ASM_REG_W_SSL 0x05F43D
83 #define ASM_REG_W_LA 0x05F43E
84 #define ASM_REG_W_LC 0x05F43F
85 #define ASM_REG_W_PC 0x000000
86 #define ASM_REG_W_IPRC 0xFFFFFF
87 #define ASM_REG_W_IPRP 0xFFFFFE
89 #define ASM_REG_W_BCR 0xFFFFFB
90 #define ASM_REG_W_DCR 0xFFFFFA
91 #define ASM_REG_W_AAR0 0xFFFFF9
92 #define ASM_REG_W_AAR1 0xFFFFF8
93 #define ASM_REG_W_AAR2 0xFFFFF7
94 #define ASM_REG_W_AAR3 0xFFFFF6
100 ONCE_REG_IDX_OMLR0
=3,
101 ONCE_REG_IDX_OMLR1
=4,
102 ONCE_REG_IDX_OGDBR
=5,
103 ONCE_REG_IDX_OPDBR
=6,
104 ONCE_REG_IDX_OPILR
=7,
107 ONCE_REG_IDX_OPABFR
=10,
108 ONCE_REG_IDX_OPABDR
=11,
109 ONCE_REG_IDX_OPABEX
=12,
110 ONCE_REG_IDX_OPABF0
=13,
111 ONCE_REG_IDX_OPABF1
=14,
112 ONCE_REG_IDX_OPABF2
=15,
113 ONCE_REG_IDX_OPABF3
=16,
114 ONCE_REG_IDX_OPABF4
=17,
115 ONCE_REG_IDX_OPABF5
=18,
116 ONCE_REG_IDX_OPABF6
=19,
117 ONCE_REG_IDX_OPABF7
=20,
118 ONCE_REG_IDX_OPABF8
=21,
119 ONCE_REG_IDX_OPABF9
=22,
120 ONCE_REG_IDX_OPABF10
=23,
121 ONCE_REG_IDX_OPABF11
=24,
124 static struct once_reg once_regs
[] = {
125 {ONCE_REG_IDX_OSCR
, DSP563XX_ONCE_OSCR
, 24, "OSCR", 0},
126 {ONCE_REG_IDX_OMBC
, DSP563XX_ONCE_OMBC
, 24, "OMBC", 0},
127 {ONCE_REG_IDX_OBCR
, DSP563XX_ONCE_OBCR
, 24, "OBCR", 0},
128 {ONCE_REG_IDX_OMLR0
, DSP563XX_ONCE_OMLR0
, 24, "OMLR0", 0},
129 {ONCE_REG_IDX_OMLR1
, DSP563XX_ONCE_OMLR1
, 24, "OMLR1", 0},
130 {ONCE_REG_IDX_OGDBR
, DSP563XX_ONCE_OGDBR
, 24, "OGDBR", 0},
131 {ONCE_REG_IDX_OPDBR
, DSP563XX_ONCE_OPDBR
, 24, "OPDBR", 0},
132 {ONCE_REG_IDX_OPILR
, DSP563XX_ONCE_OPILR
, 24, "OPILR", 0},
133 {ONCE_REG_IDX_PDB
, DSP563XX_ONCE_PDBGOTO
, 24, "PDB", 0},
134 {ONCE_REG_IDX_OTC
, DSP563XX_ONCE_OTC
, 24, "OTC", 0},
135 {ONCE_REG_IDX_OPABFR
, DSP563XX_ONCE_OPABFR
, 24, "OPABFR", 0},
136 {ONCE_REG_IDX_OPABDR
, DSP563XX_ONCE_OPABDR
, 24, "OPABDR", 0},
137 {ONCE_REG_IDX_OPABEX
, DSP563XX_ONCE_OPABEX
, 24, "OPABEX", 0},
138 {ONCE_REG_IDX_OPABF0
, DSP563XX_ONCE_OPABF11
, 25, "OPABF0", 0},
139 {ONCE_REG_IDX_OPABF1
, DSP563XX_ONCE_OPABF11
, 25, "OPABF1", 0},
140 {ONCE_REG_IDX_OPABF2
, DSP563XX_ONCE_OPABF11
, 25, "OPABF2", 0},
141 {ONCE_REG_IDX_OPABF3
, DSP563XX_ONCE_OPABF11
, 25, "OPABF3", 0},
142 {ONCE_REG_IDX_OPABF4
, DSP563XX_ONCE_OPABF11
, 25, "OPABF4", 0},
143 {ONCE_REG_IDX_OPABF5
, DSP563XX_ONCE_OPABF11
, 25, "OPABF5", 0},
144 {ONCE_REG_IDX_OPABF6
, DSP563XX_ONCE_OPABF11
, 25, "OPABF6", 0},
145 {ONCE_REG_IDX_OPABF7
, DSP563XX_ONCE_OPABF11
, 25, "OPABF7", 0},
146 {ONCE_REG_IDX_OPABF8
, DSP563XX_ONCE_OPABF11
, 25, "OPABF8", 0},
147 {ONCE_REG_IDX_OPABF9
, DSP563XX_ONCE_OPABF11
, 25, "OPABF9", 0},
148 {ONCE_REG_IDX_OPABF10
, DSP563XX_ONCE_OPABF11
, 25, "OPABF10", 0},
149 {ONCE_REG_IDX_OPABF11
, DSP563XX_ONCE_OPABF11
, 25, "OPABF11", 0},
150 // {25,0x1f,24,"NRSEL",0},
153 enum dsp563xx_reg_idx
{
154 DSP563XX_REG_IDX_R0
=0,
155 DSP563XX_REG_IDX_R1
=1,
156 DSP563XX_REG_IDX_R2
=2,
157 DSP563XX_REG_IDX_R3
=3,
158 DSP563XX_REG_IDX_R4
=4,
159 DSP563XX_REG_IDX_R5
=5,
160 DSP563XX_REG_IDX_R6
=6,
161 DSP563XX_REG_IDX_R7
=7,
162 DSP563XX_REG_IDX_N0
=8,
163 DSP563XX_REG_IDX_N1
=9,
164 DSP563XX_REG_IDX_N2
=10,
165 DSP563XX_REG_IDX_N3
=11,
166 DSP563XX_REG_IDX_N4
=12,
167 DSP563XX_REG_IDX_N5
=13,
168 DSP563XX_REG_IDX_N6
=14,
169 DSP563XX_REG_IDX_N7
=15,
170 DSP563XX_REG_IDX_M0
=16,
171 DSP563XX_REG_IDX_M1
=17,
172 DSP563XX_REG_IDX_M2
=18,
173 DSP563XX_REG_IDX_M3
=19,
174 DSP563XX_REG_IDX_M4
=20,
175 DSP563XX_REG_IDX_M5
=21,
176 DSP563XX_REG_IDX_M6
=22,
177 DSP563XX_REG_IDX_M7
=23,
178 DSP563XX_REG_IDX_X0
=24,
179 DSP563XX_REG_IDX_X1
=25,
180 DSP563XX_REG_IDX_Y0
=26,
181 DSP563XX_REG_IDX_Y1
=27,
182 DSP563XX_REG_IDX_A0
=28,
183 DSP563XX_REG_IDX_A1
=29,
184 DSP563XX_REG_IDX_A2
=30,
185 DSP563XX_REG_IDX_B0
=31,
186 DSP563XX_REG_IDX_B1
=32,
187 DSP563XX_REG_IDX_B2
=33,
188 DSP563XX_REG_IDX_SSH
=34,
189 DSP563XX_REG_IDX_SSL
=35,
190 DSP563XX_REG_IDX_SP
=36,
191 DSP563XX_REG_IDX_EP
=37,
192 DSP563XX_REG_IDX_SZ
=38,
193 DSP563XX_REG_IDX_SC
=39,
194 DSP563XX_REG_IDX_PC
=40,
195 DSP563XX_REG_IDX_SR
=41,
196 DSP563XX_REG_IDX_OMR
=42,
197 DSP563XX_REG_IDX_LA
=43,
198 DSP563XX_REG_IDX_LC
=44,
199 DSP563XX_REG_IDX_VBA
=45,
200 DSP563XX_REG_IDX_IPRC
=46,
201 DSP563XX_REG_IDX_IPRP
=47,
202 DSP563XX_REG_IDX_BCR
=48,
203 DSP563XX_REG_IDX_DCR
=49,
204 DSP563XX_REG_IDX_AAR0
=50,
205 DSP563XX_REG_IDX_AAR1
=51,
206 DSP563XX_REG_IDX_AAR2
=52,
207 DSP563XX_REG_IDX_AAR3
=53,
215 /* effective addressing mode encoding */
221 /* address registers */
222 {DSP563XX_REG_IDX_R0
, "r0", 24, 0x10, ASM_REG_W_R0
},
223 {DSP563XX_REG_IDX_R1
, "r1", 24, 0x11, ASM_REG_W_R1
},
224 {DSP563XX_REG_IDX_R2
, "r2", 24, 0x12, ASM_REG_W_R2
},
225 {DSP563XX_REG_IDX_R3
, "r3", 24, 0x13, ASM_REG_W_R3
},
226 {DSP563XX_REG_IDX_R4
, "r4", 24, 0x14, ASM_REG_W_R4
},
227 {DSP563XX_REG_IDX_R5
, "r5", 24, 0x15, ASM_REG_W_R5
},
228 {DSP563XX_REG_IDX_R6
, "r6", 24, 0x16, ASM_REG_W_R6
},
229 {DSP563XX_REG_IDX_R7
, "r7", 24, 0x17, ASM_REG_W_R7
},
230 /* offset registers */
231 {DSP563XX_REG_IDX_N0
, "n0", 24, 0x18, ASM_REG_W_N0
},
232 {DSP563XX_REG_IDX_N1
, "n1", 24, 0x19, ASM_REG_W_N1
},
233 {DSP563XX_REG_IDX_N2
, "n2", 24, 0x1a, ASM_REG_W_N2
},
234 {DSP563XX_REG_IDX_N3
, "n3", 24, 0x1b, ASM_REG_W_N3
},
235 {DSP563XX_REG_IDX_N4
, "n4", 24, 0x1c, ASM_REG_W_N4
},
236 {DSP563XX_REG_IDX_N5
, "n5", 24, 0x1d, ASM_REG_W_N5
},
237 {DSP563XX_REG_IDX_N6
, "n6", 24, 0x1e, ASM_REG_W_N6
},
238 {DSP563XX_REG_IDX_N7
, "n7", 24, 0x1f, ASM_REG_W_N7
},
239 /* modifier registers */
240 {DSP563XX_REG_IDX_M0
, "m0", 24, 0x20, ASM_REG_W_M0
},
241 {DSP563XX_REG_IDX_M1
, "m1", 24, 0x21, ASM_REG_W_M1
},
242 {DSP563XX_REG_IDX_M2
, "m2", 24, 0x22, ASM_REG_W_M2
},
243 {DSP563XX_REG_IDX_M3
, "m3", 24, 0x23, ASM_REG_W_M3
},
244 {DSP563XX_REG_IDX_M4
, "m4", 24, 0x24, ASM_REG_W_M4
},
245 {DSP563XX_REG_IDX_M5
, "m5", 24, 0x25, ASM_REG_W_M5
},
246 {DSP563XX_REG_IDX_M6
, "m6", 24, 0x26, ASM_REG_W_M6
},
247 {DSP563XX_REG_IDX_M7
, "m7", 24, 0x27, ASM_REG_W_M7
},
248 /* data alu input register */
249 {DSP563XX_REG_IDX_X0
, "x0", 24, 0x04, ASM_REG_W_X0
},
250 {DSP563XX_REG_IDX_X1
, "x1", 24, 0x05, ASM_REG_W_X1
},
251 {DSP563XX_REG_IDX_Y0
, "y0", 24, 0x06, ASM_REG_W_Y0
},
252 {DSP563XX_REG_IDX_Y1
, "y1", 24, 0x07, ASM_REG_W_Y1
},
253 /* data alu accumulator register */
254 {DSP563XX_REG_IDX_A0
, "a0", 24, 0x08, ASM_REG_W_A0
},
255 {DSP563XX_REG_IDX_A1
, "a1", 24, 0x0c, ASM_REG_W_A1
},
256 {DSP563XX_REG_IDX_A2
, "a2", 8, 0x0a, ASM_REG_W_A2
},
257 {DSP563XX_REG_IDX_B0
, "b0", 24, 0x09, ASM_REG_W_B0
},
258 {DSP563XX_REG_IDX_B1
, "b1", 24, 0x0d, ASM_REG_W_B1
},
259 {DSP563XX_REG_IDX_B2
, "b2", 8, 0x0b, ASM_REG_W_B2
},
261 {DSP563XX_REG_IDX_SSH
, "ssh",24, 0x3c, ASM_REG_W_SSH
},
262 {DSP563XX_REG_IDX_SSL
, "ssl",24, 0x3d, ASM_REG_W_SSL
},
263 {DSP563XX_REG_IDX_SP
, "sp", 24, 0x3b, ASM_REG_W_SP
},
264 {DSP563XX_REG_IDX_EP
, "ep", 24, 0x2a, ASM_REG_W_EP
},
265 {DSP563XX_REG_IDX_SZ
, "sz", 24, 0x38, ASM_REG_W_SZ
},
266 {DSP563XX_REG_IDX_SC
, "sc", 24, 0x31, ASM_REG_W_SC
},
268 {DSP563XX_REG_IDX_PC
, "pc", 24, 0x00, ASM_REG_W_PC
},
269 {DSP563XX_REG_IDX_SR
, "sr", 24, 0x39, ASM_REG_W_SR
},
270 {DSP563XX_REG_IDX_OMR
, "omr",24, 0x3a, ASM_REG_W_OMR
},
271 {DSP563XX_REG_IDX_LA
, "la", 24, 0x3e, ASM_REG_W_LA
},
272 {DSP563XX_REG_IDX_LC
, "lc", 24, 0x3f, ASM_REG_W_LC
},
274 {DSP563XX_REG_IDX_VBA
, "vba", 24, 0x30, ASM_REG_W_VBA
},
275 {DSP563XX_REG_IDX_IPRC
, "iprc",24, 0x00, ASM_REG_W_IPRC
},
276 {DSP563XX_REG_IDX_IPRP
, "iprp",24, 0x00, ASM_REG_W_IPRP
},
278 {DSP563XX_REG_IDX_BCR
, "bcr", 24, 0x00, ASM_REG_W_BCR
},
279 {DSP563XX_REG_IDX_DCR
, "dcr", 24, 0x00, ASM_REG_W_DCR
},
280 {DSP563XX_REG_IDX_AAR0
, "aar0",24, 0x00, ASM_REG_W_AAR0
},
281 {DSP563XX_REG_IDX_AAR1
, "aar1",24, 0x00, ASM_REG_W_AAR1
},
282 {DSP563XX_REG_IDX_AAR2
, "aar2",24, 0x00, ASM_REG_W_AAR2
},
283 {DSP563XX_REG_IDX_AAR3
, "aar3",24, 0x00, ASM_REG_W_AAR3
},
295 #define INSTR_JUMP 0x0AF080
296 /* Effective Addressing Mode Encoding */
298 /* instrcution encoder */
300 * s - peripheral space X/Y (X=0,Y=1)
302 * d - source/destination register
303 * p - IO short address
305 #define INSTR_MOVEP_REG_HIO(s,w,d,p) (0x084000 | ((s & 1)<<16) | ((w&1)<<15) | ((d & 0x3f)<<8) | (p & 0x3f))
307 /* the gdb register list is send in this order */
308 uint8_t gdb_reg_list_idx
[] = {
309 DSP563XX_REG_IDX_X1
, DSP563XX_REG_IDX_X0
, DSP563XX_REG_IDX_Y1
, DSP563XX_REG_IDX_Y0
,
310 DSP563XX_REG_IDX_A2
, DSP563XX_REG_IDX_A1
, DSP563XX_REG_IDX_A0
, DSP563XX_REG_IDX_B2
,
311 DSP563XX_REG_IDX_B1
, DSP563XX_REG_IDX_B0
, DSP563XX_REG_IDX_PC
, DSP563XX_REG_IDX_SR
,
312 DSP563XX_REG_IDX_OMR
,DSP563XX_REG_IDX_LA
, DSP563XX_REG_IDX_LC
, DSP563XX_REG_IDX_SSH
,
313 DSP563XX_REG_IDX_SSL
,DSP563XX_REG_IDX_SP
, DSP563XX_REG_IDX_EP
, DSP563XX_REG_IDX_SZ
,
314 DSP563XX_REG_IDX_SC
, DSP563XX_REG_IDX_VBA
,DSP563XX_REG_IDX_IPRC
, DSP563XX_REG_IDX_IPRP
,
315 DSP563XX_REG_IDX_BCR
,DSP563XX_REG_IDX_DCR
,DSP563XX_REG_IDX_AAR0
,DSP563XX_REG_IDX_AAR1
,
316 DSP563XX_REG_IDX_AAR2
,DSP563XX_REG_IDX_AAR3
,DSP563XX_REG_IDX_R0
,DSP563XX_REG_IDX_R1
,
317 DSP563XX_REG_IDX_R2
, DSP563XX_REG_IDX_R3
, DSP563XX_REG_IDX_R4
, DSP563XX_REG_IDX_R5
,
318 DSP563XX_REG_IDX_R6
, DSP563XX_REG_IDX_R7
, DSP563XX_REG_IDX_N0
, DSP563XX_REG_IDX_N1
,
319 DSP563XX_REG_IDX_N2
, DSP563XX_REG_IDX_N3
, DSP563XX_REG_IDX_N4
, DSP563XX_REG_IDX_N5
,
320 DSP563XX_REG_IDX_N6
, DSP563XX_REG_IDX_N7
, DSP563XX_REG_IDX_M0
, DSP563XX_REG_IDX_M1
,
321 DSP563XX_REG_IDX_M2
, DSP563XX_REG_IDX_M3
, DSP563XX_REG_IDX_M4
, DSP563XX_REG_IDX_M5
,
322 DSP563XX_REG_IDX_M6
, DSP563XX_REG_IDX_M7
,
325 static int dsp563xx_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[], int *reg_list_size
)
328 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
330 if (target
->state
!= TARGET_HALTED
)
332 return ERROR_TARGET_NOT_HALTED
;
335 *reg_list_size
= DSP563XX_NUMCOREREGS
;
336 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
339 return ERROR_INVALID_ARGUMENTS
;
341 for (i
= 0; i
< DSP563XX_NUMCOREREGS
; i
++)
343 (*reg_list
)[i
] = &dsp563xx
->core_cache
->reg_list
[gdb_reg_list_idx
[i
]];
350 static int dsp563xx_read_core_reg(struct target
*target
, int num
)
353 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
355 if ((num
< 0) || (num
>= DSP563XX_NUMCOREREGS
))
356 return ERROR_INVALID_ARGUMENTS
;
358 reg_value
= dsp563xx
->core_regs
[num
];
359 buf_set_u32(dsp563xx
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
360 dsp563xx
->core_cache
->reg_list
[num
].valid
= 1;
361 dsp563xx
->core_cache
->reg_list
[num
].dirty
= 0;
366 static int dsp563xx_write_core_reg(struct target
*target
, int num
)
369 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
371 if ((num
< 0) || (num
>= DSP563XX_NUMCOREREGS
))
372 return ERROR_INVALID_ARGUMENTS
;
374 reg_value
= buf_get_u32(dsp563xx
->core_cache
->reg_list
[num
].value
, 0, 32);
375 dsp563xx
->core_regs
[num
] = reg_value
;
376 dsp563xx
->core_cache
->reg_list
[num
].valid
= 1;
377 dsp563xx
->core_cache
->reg_list
[num
].dirty
= 0;
382 static int dsp563xx_get_core_reg(struct reg
*reg
)
384 struct dsp563xx_core_reg
*dsp563xx_reg
= reg
->arch_info
;
385 struct target
*target
= dsp563xx_reg
->target
;
386 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
388 LOG_DEBUG("%s", __FUNCTION__
);
390 if (target
->state
!= TARGET_HALTED
)
392 return ERROR_TARGET_NOT_HALTED
;
395 return dsp563xx
->read_core_reg(target
, dsp563xx_reg
->num
);
398 static int dsp563xx_set_core_reg(struct reg
*reg
, uint8_t * buf
)
400 LOG_DEBUG("%s", __FUNCTION__
);
402 struct dsp563xx_core_reg
*dsp563xx_reg
= reg
->arch_info
;
403 struct target
*target
= dsp563xx_reg
->target
;
404 uint32_t value
= buf_get_u32(buf
, 0, 32);
406 if (target
->state
!= TARGET_HALTED
)
408 return ERROR_TARGET_NOT_HALTED
;
411 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
418 static const struct reg_arch_type dsp563xx_reg_type
= {
419 .get
= dsp563xx_get_core_reg
,
420 .set
= dsp563xx_set_core_reg
,
423 static void dsp563xx_build_reg_cache(struct target
*target
)
425 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
427 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
428 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
429 struct reg
*reg_list
= malloc(sizeof(struct reg
) * DSP563XX_NUMCOREREGS
);
430 struct dsp563xx_core_reg
*arch_info
= malloc(sizeof(struct dsp563xx_core_reg
) * DSP563XX_NUMCOREREGS
);
433 /* Build the process context cache */
434 cache
->name
= "dsp563xx registers";
436 cache
->reg_list
= reg_list
;
437 cache
->num_regs
= DSP563XX_NUMCOREREGS
;
439 dsp563xx
->core_cache
= cache
;
441 for (i
= 0; i
< DSP563XX_NUMCOREREGS
; i
++)
443 arch_info
[i
].num
= dsp563xx_regs
[i
].id
;
444 arch_info
[i
].name
= dsp563xx_regs
[i
].name
;
445 arch_info
[i
].size
= dsp563xx_regs
[i
].bits
;
446 arch_info
[i
].eame
= dsp563xx_regs
[i
].eame
;
447 arch_info
[i
].instr_mask
= dsp563xx_regs
[i
].instr_mask
;
448 arch_info
[i
].target
= target
;
449 arch_info
[i
].dsp563xx_common
= dsp563xx
;
450 reg_list
[i
].name
= dsp563xx_regs
[i
].name
;
451 reg_list
[i
].size
= 32; //dsp563xx_regs[i].bits;
452 reg_list
[i
].value
= calloc(1, 4);
453 reg_list
[i
].dirty
= 0;
454 reg_list
[i
].valid
= 0;
455 reg_list
[i
].type
= &dsp563xx_reg_type
;
456 reg_list
[i
].arch_info
= &arch_info
[i
];
460 static int dsp563xx_read_register(struct target
*target
, int num
, int force
);
461 static int dsp563xx_write_register(struct target
*target
, int num
, int force
);
463 static int dsp563xx_reg_read_high_io(struct target
*target
, uint32_t instr_mask
, uint32_t * data
)
467 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
469 /* we use r0 to store temporary data */
470 if (!dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_R0
].valid
)
471 dsp563xx
->read_core_reg(target
, DSP563XX_REG_IDX_R0
);
473 /* move source memory to r0 */
474 instr
= INSTR_MOVEP_REG_HIO(MEM_X
, 0, EAME_R0
, instr_mask
);
475 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, 0, instr
)) != ERROR_OK
)
477 /* move r0 to debug register */
478 instr
= INSTR_MOVEP_REG_HIO(MEM_X
, 1, EAME_R0
, 0xfffffc);
479 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, 1, instr
)) != ERROR_OK
)
481 /* read debug register */
482 if ((err
= dsp563xx_once_reg_read(target
->tap
, 1, DSP563XX_ONCE_OGDBR
, data
)) != ERROR_OK
)
484 /* r0 is no longer valid on target */
485 dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_R0
].dirty
= 1;
490 static int dsp563xx_reg_write_high_io(struct target
*target
, uint32_t instr_mask
, uint32_t data
)
494 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
496 /* we use r0 to store temporary data */
497 if (!dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_R0
].valid
)
498 dsp563xx
->read_core_reg(target
, DSP563XX_REG_IDX_R0
);
500 /* move data to r0 */
501 if ((err
= dsp563xx_once_execute_dw_ir(target
->tap
, 0, 0x60F400, data
)) != ERROR_OK
)
503 /* move r0 to destination memory */
504 instr
= INSTR_MOVEP_REG_HIO(MEM_X
, 1, EAME_R0
, instr_mask
);
505 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, 1, instr
)) != ERROR_OK
)
508 /* r0 is no longer valid on target */
509 dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_R0
].dirty
= 1;
514 static int dsp563xx_reg_read(struct target
*target
, uint32_t eame
, uint32_t * data
)
519 instr
= INSTR_MOVEP_REG_HIO(MEM_X
, 1, eame
, 0xfffffc);
520 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, 0, instr
)) != ERROR_OK
)
523 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, 1, 0x000000)) != ERROR_OK
)
525 /* read debug register */
526 return dsp563xx_once_reg_read(target
->tap
, 1, DSP563XX_ONCE_OGDBR
, data
);
529 static int dsp563xx_reg_write(struct target
*target
, uint32_t instr_mask
, uint32_t data
)
533 if ((err
= dsp563xx_once_execute_dw_ir(target
->tap
, 0, instr_mask
, data
)) != ERROR_OK
)
536 return dsp563xx_once_execute_sw_ir(target
->tap
, 1, 0x000000);
539 static int dsp563xx_reg_pc_read(struct target
*target
)
541 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
543 /* pc was changed, nothing todo */
544 if (dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_PC
].dirty
)
547 /* conditional branch check */
548 if ( once_regs
[ONCE_REG_IDX_OPABDR
].reg
== once_regs
[ONCE_REG_IDX_OPABEX
].reg
)
550 if ( (once_regs
[ONCE_REG_IDX_OPABF11
].reg
& 1) == 0 )
552 LOG_DEBUG("%s conditional branch not supported yet (0x%x 0x%x 0x%x)", __FUNCTION__
,
553 (once_regs
[ONCE_REG_IDX_OPABF11
].reg
>> 1),
554 once_regs
[ONCE_REG_IDX_OPABDR
].reg
,
555 once_regs
[ONCE_REG_IDX_OPABEX
].reg
);
557 /* TODO: use disassembly to set correct pc offset
558 * read 2 words from OPABF11 and disasm the instruction
560 dsp563xx
->core_regs
[DSP563XX_REG_IDX_PC
] = (once_regs
[ONCE_REG_IDX_OPABF11
].reg
>> 1) & 0x00FFFFFF;
564 if ( once_regs
[ONCE_REG_IDX_OPABEX
].reg
== once_regs
[ONCE_REG_IDX_OPABFR
].reg
)
566 dsp563xx
->core_regs
[DSP563XX_REG_IDX_PC
] = once_regs
[ONCE_REG_IDX_OPABEX
].reg
;
570 dsp563xx
->core_regs
[DSP563XX_REG_IDX_PC
] = once_regs
[ONCE_REG_IDX_OPABEX
].reg
- 1;
576 dsp563xx
->core_regs
[DSP563XX_REG_IDX_PC
] = once_regs
[ONCE_REG_IDX_OPABEX
].reg
;
579 dsp563xx
->read_core_reg(target
, DSP563XX_REG_IDX_PC
);
584 static int dsp563xx_reg_ssh_read(struct target
*target
)
588 struct dsp563xx_core_reg
*arch_info
;
589 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
591 arch_info
= dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_SSH
].arch_info
;
593 /* get a valid stack pointer */
594 if ((err
= dsp563xx_read_register(target
, DSP563XX_REG_IDX_SP
, 0)) != ERROR_OK
)
596 sp
= dsp563xx
->core_regs
[DSP563XX_REG_IDX_SP
];
597 if ((err
= dsp563xx_write_register(target
, DSP563XX_REG_IDX_SP
, 0)) != ERROR_OK
)
600 /* get a valid stack count */
601 if ((err
= dsp563xx_read_register(target
, DSP563XX_REG_IDX_SC
, 0)) != ERROR_OK
)
604 if ((err
= dsp563xx_write_register(target
, DSP563XX_REG_IDX_SC
, 0)) != ERROR_OK
)
607 /* get a valid extended pointer */
608 if ((err
= dsp563xx_read_register(target
, DSP563XX_REG_IDX_EP
, 0)) != ERROR_OK
)
611 if ((err
= dsp563xx_write_register(target
, DSP563XX_REG_IDX_EP
, 0)) != ERROR_OK
)
620 if ((err
= dsp563xx_reg_read(target
, arch_info
->eame
, &sp
)) != ERROR_OK
)
623 if ((err
= dsp563xx_write_register(target
, DSP563XX_REG_IDX_SC
, 1)) != ERROR_OK
)
625 if ((err
= dsp563xx_write_register(target
, DSP563XX_REG_IDX_SP
, 1)) != ERROR_OK
)
627 if ((err
= dsp563xx_write_register(target
, DSP563XX_REG_IDX_EP
, 1)) != ERROR_OK
)
631 dsp563xx
->core_regs
[DSP563XX_REG_IDX_SSH
] = sp
;
632 dsp563xx
->read_core_reg(target
, DSP563XX_REG_IDX_SSH
);
637 static int dsp563xx_reg_ssh_write(struct target
*target
)
641 struct dsp563xx_core_reg
*arch_info
;
642 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
644 arch_info
= dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_SSH
].arch_info
;
646 /* get a valid stack pointer */
647 if ((err
= dsp563xx_read_register(target
, DSP563XX_REG_IDX_SP
, 0)) != ERROR_OK
)
649 sp
= dsp563xx
->core_regs
[DSP563XX_REG_IDX_SP
];
654 /* write new stackpointer */
655 dsp563xx
->core_regs
[DSP563XX_REG_IDX_SP
] = sp
;
656 if ((err
= dsp563xx
->read_core_reg(target
, DSP563XX_REG_IDX_SP
)) != ERROR_OK
)
658 if ((err
= dsp563xx_write_register(target
, DSP563XX_REG_IDX_SP
, 1)) != ERROR_OK
)
661 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, dsp563xx
->core_regs
[DSP563XX_REG_IDX_SSH
])) != ERROR_OK
)
664 if ((err
= dsp563xx_read_register(target
, DSP563XX_REG_IDX_SP
, 1)) != ERROR_OK
)
666 if ((err
= dsp563xx_read_register(target
, DSP563XX_REG_IDX_SSH
, 1)) != ERROR_OK
)
673 static int dsp563xx_reg_ssl_read(struct target
*target
)
677 struct dsp563xx_core_reg
*arch_info
;
678 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
680 arch_info
= dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_SSL
].arch_info
;
682 /* get a valid stack pointer */
683 if ((err
= dsp563xx_read_register(target
, DSP563XX_REG_IDX_SP
, 0)) != ERROR_OK
)
685 sp
= dsp563xx
->core_regs
[DSP563XX_REG_IDX_SP
];
693 if ((err
= dsp563xx_reg_read(target
, arch_info
->eame
, &sp
)) != ERROR_OK
)
697 dsp563xx
->core_regs
[DSP563XX_REG_IDX_SSL
] = sp
;
698 dsp563xx
->read_core_reg(target
, DSP563XX_REG_IDX_SSL
);
703 static int dsp563xx_read_register(struct target
*target
, int num
, int force
)
707 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
708 struct dsp563xx_core_reg
*arch_info
;
711 dsp563xx
->core_cache
->reg_list
[num
].valid
= 0;
713 if (!dsp563xx
->core_cache
->reg_list
[num
].valid
)
715 arch_info
= dsp563xx
->core_cache
->reg_list
[num
].arch_info
;
717 switch (arch_info
->num
)
719 case DSP563XX_REG_IDX_SSH
:
720 err
= dsp563xx_reg_ssh_read(target
);
722 case DSP563XX_REG_IDX_SSL
:
723 err
= dsp563xx_reg_ssl_read(target
);
725 case DSP563XX_REG_IDX_PC
:
726 err
= dsp563xx_reg_pc_read(target
);
728 case DSP563XX_REG_IDX_IPRC
:
729 case DSP563XX_REG_IDX_IPRP
:
730 case DSP563XX_REG_IDX_BCR
:
731 case DSP563XX_REG_IDX_DCR
:
732 case DSP563XX_REG_IDX_AAR0
:
733 case DSP563XX_REG_IDX_AAR1
:
734 case DSP563XX_REG_IDX_AAR2
:
735 case DSP563XX_REG_IDX_AAR3
:
736 err
= dsp563xx_reg_read_high_io(target
, arch_info
->instr_mask
, &data
);
739 dsp563xx
->core_regs
[num
] = data
;
740 dsp563xx
->read_core_reg(target
, num
);
744 err
= dsp563xx_reg_read(target
, arch_info
->eame
, &data
);
747 dsp563xx
->core_regs
[num
] = data
;
748 dsp563xx
->read_core_reg(target
, num
);
758 static int dsp563xx_write_register(struct target
*target
, int num
, int force
)
761 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
762 struct dsp563xx_core_reg
*arch_info
;
765 dsp563xx
->core_cache
->reg_list
[num
].dirty
= 1;
767 if (dsp563xx
->core_cache
->reg_list
[num
].dirty
)
769 arch_info
= dsp563xx
->core_cache
->reg_list
[num
].arch_info
;
771 dsp563xx
->write_core_reg(target
, num
);
773 switch (arch_info
->num
)
775 case DSP563XX_REG_IDX_SSH
:
776 err
= dsp563xx_reg_ssh_write(target
);
778 case DSP563XX_REG_IDX_PC
:
779 /* pc is updated on resume, no need to write it here */
781 case DSP563XX_REG_IDX_IPRC
:
782 case DSP563XX_REG_IDX_IPRP
:
783 case DSP563XX_REG_IDX_BCR
:
784 case DSP563XX_REG_IDX_DCR
:
785 case DSP563XX_REG_IDX_AAR0
:
786 case DSP563XX_REG_IDX_AAR1
:
787 case DSP563XX_REG_IDX_AAR2
:
788 case DSP563XX_REG_IDX_AAR3
:
789 err
= dsp563xx_reg_write_high_io(target
, arch_info
->instr_mask
, dsp563xx
->core_regs
[num
]);
792 err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, dsp563xx
->core_regs
[num
]);
794 if ((err
== ERROR_OK
) && (arch_info
->num
== DSP563XX_REG_IDX_SP
))
796 dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_SSH
].valid
= 0;
797 dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_SSL
].valid
= 0;
807 static int dsp563xx_save_context(struct target
*target
)
809 int i
, err
= ERROR_OK
;
811 for (i
= 0; i
< DSP563XX_NUMCOREREGS
; i
++)
813 if ((err
= dsp563xx_read_register(target
, i
, 0)) != ERROR_OK
)
820 static int dsp563xx_restore_context(struct target
*target
)
822 int i
, err
= ERROR_OK
;
824 for (i
= 0; i
< DSP563XX_NUMCOREREGS
; i
++)
826 if ((err
= dsp563xx_write_register(target
, i
, 0)) != ERROR_OK
)
833 static void dsp563xx_invalidate_x_context(struct target
*target
, uint32_t addr_start
, uint32_t addr_end
)
836 struct dsp563xx_core_reg
*arch_info
;
837 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
839 if ( addr_start
> ASM_REG_W_IPRC
)
841 if ( addr_start
< ASM_REG_W_AAR3
)
844 for (i
= DSP563XX_REG_IDX_IPRC
; i
< DSP563XX_NUMCOREREGS
; i
++)
846 arch_info
= dsp563xx
->core_cache
->reg_list
[i
].arch_info
;
848 if ( (arch_info
->instr_mask
>= addr_start
) &&
849 (arch_info
->instr_mask
<= addr_end
))
851 dsp563xx
->core_cache
->reg_list
[i
].valid
= 0;
852 dsp563xx
->core_cache
->reg_list
[i
].dirty
= 0;
857 static int dsp563xx_target_create(struct target
*target
, Jim_Interp
* interp
)
859 struct dsp563xx_common
*dsp563xx
= calloc(1, sizeof(struct dsp563xx_common
));
862 return ERROR_INVALID_ARGUMENTS
;
864 dsp563xx
->jtag_info
.tap
= target
->tap
;
865 target
->arch_info
= dsp563xx
;
866 dsp563xx
->read_core_reg
= dsp563xx_read_core_reg
;
867 dsp563xx
->write_core_reg
= dsp563xx_write_core_reg
;
872 static int dsp563xx_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
874 LOG_DEBUG("%s", __FUNCTION__
);
876 dsp563xx_build_reg_cache(target
);
881 static int dsp563xx_examine(struct target
*target
)
885 if (target
->tap
->hasidcode
== false)
887 LOG_ERROR("no IDCODE present on device");
889 return ERROR_INVALID_ARGUMENTS
;
892 if (!target_was_examined(target
))
894 target_set_examined(target
);
896 /* examine core and chip derivate number */
897 chip
= (target
->tap
->idcode
>>12)&0x3ff;
898 /* core number 0 means DSP563XX */
899 if ( ((chip
>>5)&0x1f) == 0 )
902 LOG_INFO("DSP56%03d device found",chip
);
908 static int dsp563xx_arch_state(struct target
*target
)
910 LOG_DEBUG("%s", __FUNCTION__
);
914 #define DSP563XX_SR_SA (1<<17)
915 #define DSP563XX_SR_SC (1<<13)
917 static int dsp563xx_debug_once_init(struct target
*target
)
919 return dsp563xx_once_read_register(target
->tap
, 1, once_regs
, DSP563XX_NUMONCEREGS
);
922 static int dsp563xx_debug_init(struct target
*target
)
926 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
927 struct dsp563xx_core_reg
*arch_info
;
929 if ((err
= dsp563xx_debug_once_init(target
)) != ERROR_OK
)
932 arch_info
= dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_SR
].arch_info
;
934 /* check 24bit mode */
935 if ((err
= dsp563xx_read_register(target
, DSP563XX_REG_IDX_SR
, 0)) != ERROR_OK
)
938 sr
= dsp563xx
->core_regs
[DSP563XX_REG_IDX_SR
];
940 if (sr
& (DSP563XX_SR_SA
| DSP563XX_SR_SC
))
942 sr
&= ~(DSP563XX_SR_SA
| DSP563XX_SR_SC
);
944 if ((err
= dsp563xx_once_execute_dw_ir(target
->tap
, 1, arch_info
->instr_mask
, sr
)) != ERROR_OK
)
946 dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_SR
].dirty
= 1;
949 if ((err
= dsp563xx_read_register(target
, DSP563XX_REG_IDX_N0
, 0)) != ERROR_OK
)
951 if ((err
= dsp563xx_read_register(target
, DSP563XX_REG_IDX_N1
, 0)) != ERROR_OK
)
953 if ((err
= dsp563xx_read_register(target
, DSP563XX_REG_IDX_M0
, 0)) != ERROR_OK
)
955 if ((err
= dsp563xx_read_register(target
, DSP563XX_REG_IDX_M1
, 0)) != ERROR_OK
)
958 if (dsp563xx
->core_regs
[DSP563XX_REG_IDX_N0
] != 0x000000)
960 arch_info
= dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_N0
].arch_info
;
961 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, 0x000000)) != ERROR_OK
)
964 dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_N0
].dirty
= 1;
966 if (dsp563xx
->core_regs
[DSP563XX_REG_IDX_N1
] != 0x000000)
968 arch_info
= dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_N1
].arch_info
;
969 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, 0x000000)) != ERROR_OK
)
972 dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_N1
].dirty
= 1;
974 if (dsp563xx
->core_regs
[DSP563XX_REG_IDX_M0
] != 0xffffff)
976 arch_info
= dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_M0
].arch_info
;
977 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, 0xffffff)) != ERROR_OK
)
980 dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_M0
].dirty
= 1;
982 if (dsp563xx
->core_regs
[DSP563XX_REG_IDX_M1
] != 0xffffff)
984 arch_info
= dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_M1
].arch_info
;
985 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, 0xffffff)) != ERROR_OK
)
988 dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_M1
].dirty
= 1;
990 if ((err
= dsp563xx_save_context(target
)) != ERROR_OK
)
996 static int dsp563xx_jtag_debug_request(struct target
*target
)
998 return dsp563xx_once_request_debug(target
->tap
, target
->state
== TARGET_RESET
);
1001 static int dsp563xx_poll(struct target
*target
)
1004 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
1005 uint32_t once_status
=0;
1008 state
= dsp563xx_once_target_status(target
->tap
);
1010 if (state
== TARGET_UNKNOWN
)
1012 target
->state
= state
;
1013 LOG_ERROR("jtag status contains invalid mode value - communication failure");
1014 return ERROR_TARGET_FAILURE
;
1017 if ((err
= dsp563xx_once_reg_read(target
->tap
, 1, DSP563XX_ONCE_OSCR
, &once_status
)) != ERROR_OK
)
1020 if ((once_status
& DSP563XX_ONCE_OSCR_DEBUG_M
) == DSP563XX_ONCE_OSCR_DEBUG_M
)
1022 if (target
->state
!= TARGET_HALTED
)
1024 target
->state
= TARGET_HALTED
;
1026 if ((err
= dsp563xx_debug_init(target
)) != ERROR_OK
)
1029 if ( once_status
& (DSP563XX_ONCE_OSCR_MBO
|DSP563XX_ONCE_OSCR_SWO
) )
1031 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
1035 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1038 LOG_DEBUG("target->state: %s (%x)", target_state_name(target
),once_status
);
1040 LOG_INFO("halted: PC: 0x%x", dsp563xx
->core_regs
[DSP563XX_REG_IDX_PC
] );
1047 static int dsp563xx_halt(struct target
*target
)
1051 LOG_DEBUG("%s", __FUNCTION__
);
1053 if (target
->state
== TARGET_HALTED
)
1055 LOG_DEBUG("target was already halted");
1059 if (target
->state
== TARGET_UNKNOWN
)
1061 LOG_WARNING("target was in unknown state when halt was requested");
1064 if ((err
= dsp563xx_jtag_debug_request(target
)) != ERROR_OK
)
1067 target
->debug_reason
= DBG_REASON_DBGRQ
;
1072 static int dsp563xx_resume(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
)
1075 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
1077 /* check if pc was changed and resume want to execute the next address
1078 * if pc was changed from gdb or other interface we will
1079 * jump to this address and don't execute the next address
1080 * this will not affect the resume command with an address argument
1081 * because current is set to zero then
1083 if ( current
&& dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_PC
].dirty
)
1085 dsp563xx_write_core_reg(target
,DSP563XX_REG_IDX_PC
);
1086 address
= dsp563xx
->core_regs
[DSP563XX_REG_IDX_PC
];
1090 LOG_DEBUG("%s %08X %08X", __FUNCTION__
, current
, (unsigned) address
);
1092 if ((err
= dsp563xx_restore_context(target
)) != ERROR_OK
)
1094 register_cache_invalidate(dsp563xx
->core_cache
);
1098 /* restore pipeline registers and go */
1099 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OPDBR
, once_regs
[ONCE_REG_IDX_OPILR
].reg
)) != ERROR_OK
)
1102 dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OPDBR
| DSP563XX_ONCE_OCR_EX
| DSP563XX_ONCE_OCR_GO
,
1103 once_regs
[ONCE_REG_IDX_OPDBR
].reg
)) != ERROR_OK
)
1108 /* set to go register and jump */
1109 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OPDBR
, INSTR_JUMP
)) != ERROR_OK
)
1111 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_PDBGOTO
| DSP563XX_ONCE_OCR_EX
| DSP563XX_ONCE_OCR_GO
, address
)) != ERROR_OK
)
1115 target
->state
= TARGET_RUNNING
;
1117 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1122 static int dsp563xx_step_ex(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int steps
)
1125 uint32_t once_status
;
1126 uint32_t dr_in
, cnt
;
1127 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
1129 if (target
->state
!= TARGET_HALTED
)
1131 LOG_DEBUG("target was not halted");
1135 /* check if pc was changed and step want to execute the next address
1136 * if pc was changed from gdb or other interface we will
1137 * jump to this address and don't execute the next address
1138 * this will not affect the step command with an address argument
1139 * because current is set to zero then
1141 if ( current
&& dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_PC
].dirty
)
1143 dsp563xx_write_core_reg(target
,DSP563XX_REG_IDX_PC
);
1144 address
= dsp563xx
->core_regs
[DSP563XX_REG_IDX_PC
];
1148 LOG_DEBUG("%s %08X %08X", __FUNCTION__
, current
, (unsigned) address
);
1150 if ((err
= dsp563xx_jtag_debug_request(target
)) != ERROR_OK
)
1152 if ((err
= dsp563xx_restore_context(target
)) != ERROR_OK
)
1155 /* reset trace mode */
1156 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OSCR
, 0x000000)) != ERROR_OK
)
1158 /* enable trace mode */
1159 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OSCR
, DSP563XX_ONCE_OSCR_TME
)) != ERROR_OK
)
1164 /* on JUMP we need one extra cycle */
1168 /* load step counter with N-1 */
1169 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OTC
, cnt
)) != ERROR_OK
)
1174 /* restore pipeline registers and go */
1175 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OPDBR
, once_regs
[ONCE_REG_IDX_OPILR
].reg
)) != ERROR_OK
)
1178 dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OPDBR
| DSP563XX_ONCE_OCR_EX
| DSP563XX_ONCE_OCR_GO
,
1179 once_regs
[ONCE_REG_IDX_OPDBR
].reg
)) != ERROR_OK
)
1184 /* set to go register and jump */
1185 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OPDBR
, INSTR_JUMP
)) != ERROR_OK
)
1187 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_PDBGOTO
| DSP563XX_ONCE_OCR_EX
| DSP563XX_ONCE_OCR_GO
, address
)) != ERROR_OK
)
1193 if ((err
= dsp563xx_once_reg_read(target
->tap
, 1, DSP563XX_ONCE_OSCR
, &once_status
)) != ERROR_OK
)
1196 if (once_status
& DSP563XX_ONCE_OSCR_TO
)
1198 if ((err
= dsp563xx_once_reg_read(target
->tap
, 1, DSP563XX_ONCE_OPABFR
, &dr_in
)) != ERROR_OK
)
1200 LOG_DEBUG("fetch: %08X", (unsigned) dr_in
&0x00ffffff);
1201 if ((err
= dsp563xx_once_reg_read(target
->tap
, 1, DSP563XX_ONCE_OPABDR
, &dr_in
)) != ERROR_OK
)
1203 LOG_DEBUG("decode: %08X", (unsigned) dr_in
&0x00ffffff);
1204 if ((err
= dsp563xx_once_reg_read(target
->tap
, 1, DSP563XX_ONCE_OPABEX
, &dr_in
)) != ERROR_OK
)
1206 LOG_DEBUG("execute: %08X", (unsigned) dr_in
&0x00ffffff);
1208 /* reset trace mode */
1209 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OSCR
, 0x000000)) != ERROR_OK
)
1212 register_cache_invalidate(dsp563xx
->core_cache
);
1213 if ((err
= dsp563xx_debug_init(target
)) != ERROR_OK
)
1223 static int dsp563xx_step(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
)
1226 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
1228 if (target
->state
!= TARGET_HALTED
)
1230 LOG_WARNING("target not halted");
1231 return ERROR_TARGET_NOT_HALTED
;
1234 if ( (err
=dsp563xx_step_ex(target
, current
, address
, handle_breakpoints
, 0)) != ERROR_OK
)
1239 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1240 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1242 LOG_INFO("halted: PC: 0x%x", dsp563xx
->core_regs
[DSP563XX_REG_IDX_PC
] );
1247 static int dsp563xx_assert_reset(struct target
*target
)
1250 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
1251 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1253 if (jtag_reset_config
& RESET_HAS_SRST
)
1255 /* default to asserting srst */
1256 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
1258 jtag_add_reset(1, 1);
1262 jtag_add_reset(0, 1);
1266 target
->state
= TARGET_RESET
;
1267 jtag_add_sleep(5000);
1269 /* registers are now invalid */
1270 register_cache_invalidate(dsp563xx
->core_cache
);
1272 if (target
->reset_halt
)
1274 if ((retval
= target_halt(target
)) != ERROR_OK
)
1278 LOG_DEBUG("%s", __FUNCTION__
);
1282 static int dsp563xx_deassert_reset(struct target
*target
)
1286 /* deassert reset lines */
1287 jtag_add_reset(0, 0);
1289 if ((err
= dsp563xx_poll(target
)) != ERROR_OK
)
1292 if (target
->reset_halt
)
1294 if (target
->state
== TARGET_HALTED
)
1296 /* after a reset the cpu jmp to the
1297 * reset vector and need 2 cycles to fill
1298 * the cache (fetch,decode,excecute)
1300 if ((err
= dsp563xx_step_ex(target
, 1, 0, 1, 1)) != ERROR_OK
)
1306 target
->state
= TARGET_RUNNING
;
1309 LOG_DEBUG("%s", __FUNCTION__
);
1313 static int dsp563xx_soft_reset_halt(struct target
*target
)
1315 LOG_DEBUG("%s", __FUNCTION__
);
1319 static int dsp563xx_run_algorithm(struct target
*target
,
1320 int num_mem_params
, struct mem_param
*mem_params
,
1321 int num_reg_params
, struct reg_param
*reg_params
,
1322 uint32_t entry_point
, uint32_t exit_point
,
1323 int timeout_ms
, void *arch_info
)
1326 int retval
= ERROR_OK
;
1327 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
1329 if (target
->state
!= TARGET_HALTED
)
1331 LOG_WARNING("target not halted");
1332 return ERROR_TARGET_NOT_HALTED
;
1335 for (i
= 0; i
< num_mem_params
; i
++)
1337 if ((retval
= target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
)) != ERROR_OK
)
1343 for (i
= 0; i
< num_reg_params
; i
++)
1345 struct reg
*reg
= register_get_by_name(dsp563xx
->core_cache
, reg_params
[i
].reg_name
, 0);
1349 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1353 if (reg
->size
!= reg_params
[i
].size
)
1355 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1359 if ((retval
= dsp563xx_set_core_reg(reg
, reg_params
[i
].value
)) != ERROR_OK
)
1366 if ((retval
= target_resume(target
, 0, entry_point
, 1, 1)) != ERROR_OK
)
1371 if ((retval
= target_wait_state(target
, TARGET_HALTED
, timeout_ms
)) != ERROR_OK
)
1376 for (i
= 0; i
< num_mem_params
; i
++)
1378 if (mem_params
[i
].direction
!= PARAM_OUT
)
1379 retval
= target_read_buffer(target
,
1380 mem_params
[i
].address
,
1382 mem_params
[i
].value
);
1383 if (retval
!= ERROR_OK
)
1387 for (i
= 0; i
< num_reg_params
; i
++)
1389 if (reg_params
[i
].direction
!= PARAM_OUT
)
1392 struct reg
*reg
= register_get_by_name(dsp563xx
->core_cache
, reg_params
[i
].reg_name
, 0);
1395 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1399 if (reg
->size
!= reg_params
[i
].size
)
1401 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1405 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
1412 /* global command context from openocd.c */
1413 extern struct command_context
*global_cmd_ctx
;
1415 static int dsp563xx_get_default_memory(void)
1421 if ( !global_cmd_ctx
)
1424 interp
= global_cmd_ctx
->interp
;
1429 memspace
= Jim_GetGlobalVariableStr(interp
,"memspace", JIM_NONE
);
1434 c
= (char*)Jim_GetString(memspace
,NULL
);
1454 static int dsp563xx_read_memory_core(struct target
*target
, int mem_type
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t * buffer
)
1457 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
1459 uint32_t data
, move_cmd
= 0;
1462 LOG_DEBUG("memtype: %d address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", mem_type
,address
, size
, count
);
1464 if (target
->state
!= TARGET_HALTED
)
1466 LOG_WARNING("target not halted");
1467 return ERROR_TARGET_NOT_HALTED
;
1473 /* TODO: mark effected queued registers */
1474 move_cmd
= 0x61d800;
1477 move_cmd
= 0x69d800;
1480 move_cmd
= 0x07d891;
1483 return ERROR_INVALID_ARGUMENTS
;
1486 /* we use r0 to store temporary data */
1487 if (!dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_R0
].valid
)
1488 dsp563xx
->read_core_reg(target
, DSP563XX_REG_IDX_R0
);
1489 /* we use r1 to store temporary data */
1490 if (!dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_R1
].valid
)
1491 dsp563xx
->read_core_reg(target
, DSP563XX_REG_IDX_R1
);
1493 /* r0 is no longer valid on target */
1494 dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_R0
].dirty
= 1;
1495 /* r1 is no longer valid on target */
1496 dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_R1
].dirty
= 1;
1501 if ((err
= dsp563xx_once_execute_dw_ir(target
->tap
, 1, 0x60F400, address
)) != ERROR_OK
)
1504 for (i
= 0; i
< x
; i
++)
1506 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, 0, move_cmd
)) != ERROR_OK
)
1508 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, 0, 0x08D13C)) != ERROR_OK
)
1510 if ((err
= dsp563xx_once_reg_read(target
->tap
, 0, DSP563XX_ONCE_OGDBR
, (uint32_t*)(void *)b
)) != ERROR_OK
)
1515 /* flush the jtag queue */
1516 if ((err
= jtag_execute_queue()) != ERROR_OK
)
1521 /* walk over the buffer and fix target endianness */
1524 for (i
= 0; i
< x
; i
++)
1526 data
= buf_get_u32(b
, 0, 32) & 0x00FFFFFF;
1527 // LOG_DEBUG("R: %08X", *((uint32_t*)b));
1528 target_buffer_set_u32(target
, b
, data
);
1535 static int dsp563xx_read_memory(struct target
*target
, int mem_type
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t * buffer
)
1539 uint8_t *buffer_y
,*buffer_x
;
1541 /* if size equals zero we are called from target read memory
1542 * and have to handle the parameter here */
1543 if ( (size
== 0) && (count
!= 0) )
1549 LOG_DEBUG("size is not aligned to 4 byte");
1552 count
= (count
- size
) / 4;
1556 /* we only support 4 byte aligned data */
1557 if ( (size
!= 4) || (!count
) )
1559 return ERROR_INVALID_ARGUMENTS
;
1562 if ( mem_type
!= MEM_L
)
1564 return dsp563xx_read_memory_core(target
,mem_type
,address
,size
,count
,buffer
);
1567 if ( !(buffer_y
= malloc(size
*count
)) )
1569 return ERROR_INVALID_ARGUMENTS
;
1572 if ( !(buffer_x
= malloc(size
*count
)) )
1575 return ERROR_INVALID_ARGUMENTS
;
1578 err
= dsp563xx_read_memory_core(target
,MEM_Y
,address
,size
,count
/2,buffer_y
);
1580 if ( err
!= ERROR_OK
)
1587 err
= dsp563xx_read_memory_core(target
,MEM_X
,address
,size
,count
/2,buffer_x
);
1589 if ( err
!= ERROR_OK
)
1596 for(i
=0,i1
=0;i
<count
;i
+=2,i1
++)
1598 buf_set_u32(buffer
+ i
*sizeof(uint32_t), 0, 32, buf_get_u32(buffer_y
+i1
*sizeof(uint32_t), 0, 32));
1599 buf_set_u32(buffer
+ (i
+ 1) *sizeof(uint32_t), 0, 32, buf_get_u32(buffer_x
+i1
*sizeof(uint32_t), 0, 32));
1608 static int dsp563xx_read_memory_default(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t * buffer
)
1611 return dsp563xx_read_memory(target
, dsp563xx_get_default_memory(), address
, size
, count
, buffer
);
1614 static int dsp563xx_read_buffer_default(struct target
*target
, uint32_t address
, uint32_t size
, uint8_t * buffer
)
1617 return dsp563xx_read_memory(target
, dsp563xx_get_default_memory(), address
, size
, 0, buffer
);
1620 static int dsp563xx_write_memory_core(struct target
*target
, int mem_type
, uint32_t address
, uint32_t size
, uint32_t count
, const uint8_t * buffer
)
1623 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
1625 uint32_t data
, move_cmd
= 0;
1628 LOG_DEBUG("memtype: %d address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", mem_type
,address
, size
, count
);
1630 if (target
->state
!= TARGET_HALTED
)
1632 LOG_WARNING("target not halted");
1633 return ERROR_TARGET_NOT_HALTED
;
1639 /* invalidate affected x registers */
1640 dsp563xx_invalidate_x_context(target
,address
,address
+count
-1);
1641 move_cmd
= 0x615800;
1644 move_cmd
= 0x695800;
1647 move_cmd
= 0x075891;
1650 return ERROR_INVALID_ARGUMENTS
;
1653 /* we use r0 to store temporary data */
1654 if (!dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_R0
].valid
)
1655 dsp563xx
->read_core_reg(target
, DSP563XX_REG_IDX_R0
);
1656 /* we use r1 to store temporary data */
1657 if (!dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_R1
].valid
)
1658 dsp563xx
->read_core_reg(target
, DSP563XX_REG_IDX_R1
);
1660 /* r0 is no longer valid on target */
1661 dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_R0
].dirty
= 1;
1662 /* r1 is no longer valid on target */
1663 dsp563xx
->core_cache
->reg_list
[DSP563XX_REG_IDX_R1
].dirty
= 1;
1668 if ((err
= dsp563xx_once_execute_dw_ir(target
->tap
, 1, 0x60F400, address
)) != ERROR_OK
)
1671 for (i
= 0; i
< x
; i
++)
1673 data
= target_buffer_get_u32(target
, b
);
1675 // LOG_DEBUG("W: %08X", data);
1679 if ((err
= dsp563xx_once_execute_dw_ir(target
->tap
, 0, 0x61F400, data
)) != ERROR_OK
)
1681 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, 0, move_cmd
)) != ERROR_OK
)
1686 /* flush the jtag queue */
1687 if ((err
= jtag_execute_queue()) != ERROR_OK
)
1695 static int dsp563xx_write_memory(struct target
*target
, int mem_type
, uint32_t address
, uint32_t size
, uint32_t count
, const uint8_t * buffer
)
1699 uint8_t *buffer_y
,*buffer_x
;
1701 /* if size equals zero we are called from target write memory
1702 * and have to handle the parameter here */
1703 if ( (size
== 0) && (count
!= 0) )
1709 LOG_DEBUG("size is not aligned to 4 byte");
1712 count
= (count
- size
) / 4;
1716 /* we only support 4 byte aligned data */
1717 if ( (size
!= 4) || (!count
) )
1719 return ERROR_INVALID_ARGUMENTS
;
1722 if ( mem_type
!= MEM_L
)
1724 return dsp563xx_write_memory_core(target
,mem_type
,address
,size
,count
,buffer
);
1727 if ( !(buffer_y
= malloc(size
*count
)) )
1729 return ERROR_INVALID_ARGUMENTS
;
1732 if ( !(buffer_x
= malloc(size
*count
)) )
1735 return ERROR_INVALID_ARGUMENTS
;
1738 for(i
=0,i1
=0;i
<count
;i
+=2,i1
++)
1740 buf_set_u32(buffer_y
+ i1
*sizeof(uint32_t), 0, 32, buf_get_u32(buffer
+i
*sizeof(uint32_t), 0, 32));
1741 buf_set_u32(buffer_x
+ i1
*sizeof(uint32_t), 0, 32, buf_get_u32(buffer
+(i
+1)*sizeof(uint32_t), 0, 32));
1744 err
= dsp563xx_write_memory_core(target
,MEM_Y
,address
,size
,count
/2,buffer_y
);
1746 if ( err
!= ERROR_OK
)
1753 err
= dsp563xx_write_memory_core(target
,MEM_X
,address
,size
,count
/2,buffer_x
);
1755 if ( err
!= ERROR_OK
)
1768 static int dsp563xx_write_memory_default(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, const uint8_t * buffer
)
1770 return dsp563xx_write_memory(target
, dsp563xx_get_default_memory(), address
, size
, count
, buffer
);
1773 static int dsp563xx_write_buffer_default(struct target
*target
, uint32_t address
, uint32_t size
, const uint8_t * buffer
)
1775 return dsp563xx_write_memory(target
, dsp563xx_get_default_memory(), address
, size
, 0, buffer
);
1778 static int dsp563xx_bulk_write_memory_default(struct target
*target
, uint32_t address
, uint32_t count
, const uint8_t *buffer
)
1780 return dsp563xx_write_memory(target
, dsp563xx_get_default_memory(), address
, 4, count
, buffer
);
1783 static int dsp563xx_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1788 static int dsp563xx_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1793 static int dsp563xx_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1798 static int dsp563xx_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1803 static void handle_md_output(struct command_context
*cmd_ctx
, struct target
*target
, uint32_t address
, unsigned size
, unsigned count
, const uint8_t * buffer
)
1805 const unsigned line_bytecnt
= 32;
1806 unsigned line_modulo
= line_bytecnt
/ size
;
1808 char output
[line_bytecnt
* 4 + 1];
1809 unsigned output_len
= 0;
1811 const char *value_fmt
;
1815 value_fmt
= "%8.8x ";
1818 value_fmt
= "%4.4x ";
1821 value_fmt
= "%2.2x ";
1824 /* "can't happen", caller checked */
1825 LOG_ERROR("invalid memory read size: %u", size
);
1829 for (unsigned i
= 0; i
< count
; i
++)
1831 if (i
% line_modulo
== 0)
1833 output_len
+= snprintf(output
+ output_len
, sizeof(output
) - output_len
, "0x%8.8x: ", (unsigned) (address
+ i
));
1837 const uint8_t *value_ptr
= buffer
+ i
* size
;
1841 value
= target_buffer_get_u32(target
, value_ptr
);
1844 value
= target_buffer_get_u16(target
, value_ptr
);
1849 output_len
+= snprintf(output
+ output_len
, sizeof(output
) - output_len
, value_fmt
, value
);
1851 if ((i
% line_modulo
== line_modulo
- 1) || (i
== count
- 1))
1853 command_print(cmd_ctx
, "%s", output
);
1859 COMMAND_HANDLER(dsp563xx_mem_command
)
1861 struct target
*target
= get_current_target(CMD_CTX
);
1864 uint32_t address
= 0;
1865 uint32_t count
= 1, i
;
1866 uint32_t pattern
= 0;
1868 uint8_t *buffer
, *b
;
1870 switch (CMD_NAME
[1])
1879 return ERROR_COMMAND_SYNTAX_ERROR
;
1882 switch (CMD_NAME
[3])
1894 return ERROR_COMMAND_SYNTAX_ERROR
;
1899 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
1906 return ERROR_COMMAND_SYNTAX_ERROR
;
1910 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], pattern
);
1914 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], count
);
1922 return ERROR_COMMAND_SYNTAX_ERROR
;
1926 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], count
);
1930 buffer
= calloc(count
, sizeof(uint32_t));
1934 if ((err
= dsp563xx_read_memory(target
, mem_type
, address
, sizeof(uint32_t), count
, buffer
)) == ERROR_OK
)
1935 handle_md_output(CMD_CTX
, target
, address
, sizeof(uint32_t), count
, buffer
);
1941 for (i
= 0; i
< count
; i
++)
1943 target_buffer_set_u32(target
, b
, pattern
);
1947 err
= dsp563xx_write_memory(target
, mem_type
, address
, sizeof(uint32_t), count
, buffer
);
1955 static const struct command_registration dsp563xx_command_handlers
[] = {
1958 .handler
= dsp563xx_mem_command
,
1959 .mode
= COMMAND_EXEC
,
1960 .help
= "write x memory words",
1961 .usage
= "mwwx address value [count]",
1965 .handler
= dsp563xx_mem_command
,
1966 .mode
= COMMAND_EXEC
,
1967 .help
= "write y memory words",
1968 .usage
= "mwwy address value [count]",
1972 .handler
= dsp563xx_mem_command
,
1973 .mode
= COMMAND_EXEC
,
1974 .help
= "write p memory words",
1975 .usage
= "mwwp address value [count]",
1979 .handler
= dsp563xx_mem_command
,
1980 .mode
= COMMAND_EXEC
,
1981 .help
= "display x memory words",
1982 .usage
= "mdwx address [count]",
1986 .handler
= dsp563xx_mem_command
,
1987 .mode
= COMMAND_EXEC
,
1988 .help
= "display y memory words",
1989 .usage
= "mdwy address [count]",
1993 .handler
= dsp563xx_mem_command
,
1994 .mode
= COMMAND_EXEC
,
1995 .help
= "display p memory words",
1996 .usage
= "mdwp address [count]",
1998 COMMAND_REGISTRATION_DONE
2001 /** Holds methods for DSP563XX targets. */
2002 struct target_type dsp563xx_target
= {
2005 .poll
= dsp563xx_poll
,
2006 .arch_state
= dsp563xx_arch_state
,
2008 .target_request_data
= NULL
,
2010 .get_gdb_reg_list
= dsp563xx_get_gdb_reg_list
,
2012 .halt
= dsp563xx_halt
,
2013 .resume
= dsp563xx_resume
,
2014 .step
= dsp563xx_step
,
2016 .assert_reset
= dsp563xx_assert_reset
,
2017 .deassert_reset
= dsp563xx_deassert_reset
,
2018 .soft_reset_halt
= dsp563xx_soft_reset_halt
,
2020 .read_memory
= dsp563xx_read_memory_default
,
2021 .write_memory
= dsp563xx_write_memory_default
,
2022 .bulk_write_memory
= dsp563xx_bulk_write_memory_default
,
2024 .read_buffer
= dsp563xx_read_buffer_default
,
2025 .write_buffer
= dsp563xx_write_buffer_default
,
2027 .run_algorithm
= dsp563xx_run_algorithm
,
2029 .add_breakpoint
= dsp563xx_add_breakpoint
,
2030 .remove_breakpoint
= dsp563xx_remove_breakpoint
,
2031 .add_watchpoint
= dsp563xx_add_watchpoint
,
2032 .remove_watchpoint
= dsp563xx_remove_watchpoint
,
2034 .commands
= dsp563xx_command_handlers
,
2035 .target_create
= dsp563xx_target_create
,
2036 .init_target
= dsp563xx_init_target
,
2037 .examine
= dsp563xx_examine
,
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