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arm_adi_v5: mem_ap_write error propagation
[openocd.git] / src / target / cortex_m3.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 * *
26 * *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
28 * *
29 ***************************************************************************/
30 #ifdef HAVE_CONFIG_H
31 #include "config.h"
32 #endif
33
34 #include "breakpoints.h"
35 #include "cortex_m3.h"
36 #include "target_request.h"
37 #include "target_type.h"
38 #include "arm_disassembler.h"
39 #include "register.h"
40 #include "arm_opcodes.h"
41 #include "arm_semihosting.h"
42
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FBP remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
48 *
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
51 * any longer.
52 */
53
54
55 /* forward declarations */
56 static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
57 static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
58 static void cortex_m3_enable_watchpoints(struct target *target);
59 static int cortex_m3_store_core_reg_u32(struct target *target,
60 enum armv7m_regtype type, uint32_t num, uint32_t value);
61
62 static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
63 uint32_t *value, int regnum)
64 {
65 int retval;
66 uint32_t dcrdr;
67
68 /* because the DCB_DCRDR is used for the emulated dcc channel
69 * we have to save/restore the DCB_DCRDR when used */
70
71 retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
72 if (retval != ERROR_OK)
73 return retval;
74
75 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
76 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
77 if (retval != ERROR_OK)
78 return retval;
79 retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
80 if (retval != ERROR_OK)
81 return retval;
82
83 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
84 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
85 if (retval != ERROR_OK)
86 return retval;
87 retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
88 if (retval != ERROR_OK)
89 return retval;
90
91 retval = dap_run(swjdp);
92 if (retval != ERROR_OK)
93 return retval;
94
95 /* restore DCB_DCRDR - this needs to be in a seperate
96 * transaction otherwise the emulated DCC channel breaks */
97 if (retval == ERROR_OK)
98 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
99
100 return retval;
101 }
102
103 static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
104 uint32_t value, int regnum)
105 {
106 int retval;
107 uint32_t dcrdr;
108
109 /* because the DCB_DCRDR is used for the emulated dcc channel
110 * we have to save/restore the DCB_DCRDR when used */
111
112 retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
113 if (retval != ERROR_OK)
114 return retval;
115
116 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
117 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
118 if (retval != ERROR_OK)
119 return retval;
120 retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
121 // XXX check retval
122
123 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
124 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
125 if (retval != ERROR_OK)
126 return retval;
127 retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
128 // XXX check retval
129
130 retval = dap_run(swjdp);
131
132 /* restore DCB_DCRDR - this needs to be in a seperate
133 * transaction otherwise the emulated DCC channel breaks */
134 if (retval == ERROR_OK)
135 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
136
137 return retval;
138 }
139
140 static int cortex_m3_write_debug_halt_mask(struct target *target,
141 uint32_t mask_on, uint32_t mask_off)
142 {
143 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
144 struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
145
146 /* mask off status bits */
147 cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
148 /* create new register mask */
149 cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
150
151 return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
152 }
153
154 static int cortex_m3_clear_halt(struct target *target)
155 {
156 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
157 struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
158 int retval;
159
160 /* clear step if any */
161 cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
162
163 /* Read Debug Fault Status Register */
164 retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
165 if (retval != ERROR_OK)
166 return retval;
167
168 /* Clear Debug Fault Status */
169 retval = mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
170 if (retval != ERROR_OK)
171 return retval;
172 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
173
174 return ERROR_OK;
175 }
176
177 static int cortex_m3_single_step_core(struct target *target)
178 {
179 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
180 struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
181 uint32_t dhcsr_save;
182 int retval;
183
184 /* backup dhcsr reg */
185 dhcsr_save = cortex_m3->dcb_dhcsr;
186
187 /* Mask interrupts before clearing halt, if done already. This avoids
188 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
189 * HALT can put the core into an unknown state.
190 */
191 if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
192 {
193 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
194 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
195 if (retval != ERROR_OK)
196 return retval;
197 }
198 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
199 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
200 if (retval != ERROR_OK)
201 return retval;
202 LOG_DEBUG(" ");
203
204 /* restore dhcsr reg */
205 cortex_m3->dcb_dhcsr = dhcsr_save;
206 cortex_m3_clear_halt(target);
207
208 return ERROR_OK;
209 }
210
211 static int cortex_m3_endreset_event(struct target *target)
212 {
213 int i;
214 int retval;
215 uint32_t dcb_demcr;
216 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
217 struct armv7m_common *armv7m = &cortex_m3->armv7m;
218 struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
219 struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
220 struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
221
222 /* REVISIT The four debug monitor bits are currently ignored... */
223 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
224 if (retval != ERROR_OK)
225 return retval;
226 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
227
228 /* this register is used for emulated dcc channel */
229 retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
230 if (retval != ERROR_OK)
231 return retval;
232
233 /* Enable debug requests */
234 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
235 if (retval != ERROR_OK)
236 return retval;
237 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
238 {
239 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
240 if (retval != ERROR_OK)
241 return retval;
242 }
243
244 /* clear any interrupt masking */
245 cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
246
247 /* Enable features controlled by ITM and DWT blocks, and catch only
248 * the vectors we were told to pay attention to.
249 *
250 * Target firmware is responsible for all fault handling policy
251 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
252 * or manual updates to the NVIC SHCSR and CCR registers.
253 */
254 retval = mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
255 if (retval != ERROR_OK)
256 return retval;
257
258 /* Paranoia: evidently some (early?) chips don't preserve all the
259 * debug state (including FBP, DWT, etc) across reset...
260 */
261
262 /* Enable FPB */
263 retval = target_write_u32(target, FP_CTRL, 3);
264 if (retval != ERROR_OK)
265 return retval;
266
267 cortex_m3->fpb_enabled = 1;
268
269 /* Restore FPB registers */
270 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
271 {
272 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
273 if (retval != ERROR_OK)
274 return retval;
275 }
276
277 /* Restore DWT registers */
278 for (i = 0; i < cortex_m3->dwt_num_comp; i++)
279 {
280 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
281 dwt_list[i].comp);
282 if (retval != ERROR_OK)
283 return retval;
284 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
285 dwt_list[i].mask);
286 if (retval != ERROR_OK)
287 return retval;
288 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
289 dwt_list[i].function);
290 if (retval != ERROR_OK)
291 return retval;
292 }
293 retval = dap_run(swjdp);
294 if (retval != ERROR_OK)
295 return retval;
296
297 register_cache_invalidate(cortex_m3->armv7m.core_cache);
298
299 /* make sure we have latest dhcsr flags */
300 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
301
302 return retval;
303 }
304
305 static int cortex_m3_examine_debug_reason(struct target *target)
306 {
307 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
308
309 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
310 /* only check the debug reason if we don't know it already */
311
312 if ((target->debug_reason != DBG_REASON_DBGRQ)
313 && (target->debug_reason != DBG_REASON_SINGLESTEP))
314 {
315 if (cortex_m3->nvic_dfsr & DFSR_BKPT)
316 {
317 target->debug_reason = DBG_REASON_BREAKPOINT;
318 if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
319 target->debug_reason = DBG_REASON_WPTANDBKPT;
320 }
321 else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
322 target->debug_reason = DBG_REASON_WATCHPOINT;
323 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
324 target->debug_reason = DBG_REASON_BREAKPOINT;
325 else /* EXTERNAL, HALTED */
326 target->debug_reason = DBG_REASON_UNDEFINED;
327 }
328
329 return ERROR_OK;
330 }
331
332 static int cortex_m3_examine_exception_reason(struct target *target)
333 {
334 uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
335 struct armv7m_common *armv7m = target_to_armv7m(target);
336 struct adiv5_dap *swjdp = &armv7m->dap;
337 int retval;
338
339 retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
340 if (retval != ERROR_OK)
341 return retval;
342 switch (armv7m->exception_number)
343 {
344 case 2: /* NMI */
345 break;
346 case 3: /* Hard Fault */
347 retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
348 if (retval != ERROR_OK)
349 return retval;
350 if (except_sr & 0x40000000)
351 {
352 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
353 if (retval != ERROR_OK)
354 return retval;
355 }
356 break;
357 case 4: /* Memory Management */
358 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
359 if (retval != ERROR_OK)
360 return retval;
361 retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
362 if (retval != ERROR_OK)
363 return retval;
364 break;
365 case 5: /* Bus Fault */
366 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
367 if (retval != ERROR_OK)
368 return retval;
369 retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
370 if (retval != ERROR_OK)
371 return retval;
372 break;
373 case 6: /* Usage Fault */
374 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
375 if (retval != ERROR_OK)
376 return retval;
377 break;
378 case 11: /* SVCall */
379 break;
380 case 12: /* Debug Monitor */
381 retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
382 if (retval != ERROR_OK)
383 return retval;
384 break;
385 case 14: /* PendSV */
386 break;
387 case 15: /* SysTick */
388 break;
389 default:
390 except_sr = 0;
391 break;
392 }
393 retval = dap_run(swjdp);
394 if (retval == ERROR_OK)
395 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
396 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
397 armv7m_exception_string(armv7m->exception_number),
398 shcsr, except_sr, cfsr, except_ar);
399 return retval;
400 }
401
402 /* PSP is used in some thread modes */
403 static const int armv7m_psp_reg_map[17] = {
404 ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
405 ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
406 ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
407 ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
408 ARMV7M_xPSR,
409 };
410
411 /* MSP is used in handler and some thread modes */
412 static const int armv7m_msp_reg_map[17] = {
413 ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
414 ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
415 ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
416 ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
417 ARMV7M_xPSR,
418 };
419
420 static int cortex_m3_debug_entry(struct target *target)
421 {
422 int i;
423 uint32_t xPSR;
424 int retval;
425 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
426 struct armv7m_common *armv7m = &cortex_m3->armv7m;
427 struct arm *arm = &armv7m->arm;
428 struct adiv5_dap *swjdp = &armv7m->dap;
429 struct reg *r;
430
431 LOG_DEBUG(" ");
432
433 cortex_m3_clear_halt(target);
434 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
435 if (retval != ERROR_OK)
436 return retval;
437
438 if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
439 return retval;
440
441 /* Examine target state and mode */
442 /* First load register acessible through core debug port*/
443 int num_regs = armv7m->core_cache->num_regs;
444
445 for (i = 0; i < num_regs; i++)
446 {
447 if (!armv7m->core_cache->reg_list[i].valid)
448 armv7m->read_core_reg(target, i);
449 }
450
451 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
452 xPSR = buf_get_u32(r->value, 0, 32);
453
454 #ifdef ARMV7_GDB_HACKS
455 /* FIXME this breaks on scan chains with more than one Cortex-M3.
456 * Instead, each CM3 should have its own dummy value...
457 */
458 /* copy real xpsr reg for gdb, setting thumb bit */
459 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
460 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
461 armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
462 armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
463 #endif
464
465 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
466 if (xPSR & 0xf00)
467 {
468 r->dirty = r->valid;
469 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
470 }
471
472 /* Are we in an exception handler */
473 if (xPSR & 0x1FF)
474 {
475 armv7m->core_mode = ARMV7M_MODE_HANDLER;
476 armv7m->exception_number = (xPSR & 0x1FF);
477
478 arm->core_mode = ARM_MODE_HANDLER;
479 arm->map = armv7m_msp_reg_map;
480 }
481 else
482 {
483 unsigned control = buf_get_u32(armv7m->core_cache
484 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
485
486 /* is this thread privileged? */
487 armv7m->core_mode = control & 1;
488 arm->core_mode = armv7m->core_mode
489 ? ARM_MODE_USER_THREAD
490 : ARM_MODE_THREAD;
491
492 /* which stack is it using? */
493 if (control & 2)
494 arm->map = armv7m_psp_reg_map;
495 else
496 arm->map = armv7m_msp_reg_map;
497
498 armv7m->exception_number = 0;
499 }
500
501 if (armv7m->exception_number)
502 {
503 cortex_m3_examine_exception_reason(target);
504 }
505
506 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
507 armv7m_mode_strings[armv7m->core_mode],
508 *(uint32_t*)(arm->pc->value),
509 target_state_name(target));
510
511 if (armv7m->post_debug_entry)
512 {
513 retval = armv7m->post_debug_entry(target);
514 if (retval != ERROR_OK)
515 return retval;
516 }
517
518 return ERROR_OK;
519 }
520
521 static int cortex_m3_poll(struct target *target)
522 {
523 int retval;
524 enum target_state prev_target_state = target->state;
525 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
526 struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
527
528 /* Read from Debug Halting Control and Status Register */
529 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
530 if (retval != ERROR_OK)
531 {
532 target->state = TARGET_UNKNOWN;
533 return retval;
534 }
535
536 /* Recover from lockup. See ARMv7-M architecture spec,
537 * section B1.5.15 "Unrecoverable exception cases".
538 *
539 * REVISIT Is there a better way to report and handle this?
540 */
541 if (cortex_m3->dcb_dhcsr & S_LOCKUP) {
542 LOG_WARNING("%s -- clearing lockup after double fault",
543 target_name(target));
544 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
545 target->debug_reason = DBG_REASON_DBGRQ;
546
547 /* refresh status bits */
548 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
549 if (retval != ERROR_OK)
550 return retval;
551 }
552
553 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
554 {
555 /* check if still in reset */
556 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
557 if (retval != ERROR_OK)
558 return retval;
559
560 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
561 {
562 target->state = TARGET_RESET;
563 return ERROR_OK;
564 }
565 }
566
567 if (target->state == TARGET_RESET)
568 {
569 /* Cannot switch context while running so endreset is
570 * called with target->state == TARGET_RESET
571 */
572 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
573 cortex_m3->dcb_dhcsr);
574 cortex_m3_endreset_event(target);
575 target->state = TARGET_RUNNING;
576 prev_target_state = TARGET_RUNNING;
577 }
578
579 if (cortex_m3->dcb_dhcsr & S_HALT)
580 {
581 target->state = TARGET_HALTED;
582
583 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
584 {
585 if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
586 return retval;
587
588 if (arm_semihosting(target, &retval) != 0)
589 return retval;
590
591 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
592 }
593 if (prev_target_state == TARGET_DEBUG_RUNNING)
594 {
595 LOG_DEBUG(" ");
596 if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
597 return retval;
598
599 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
600 }
601 }
602
603 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
604 * How best to model low power modes?
605 */
606
607 if (target->state == TARGET_UNKNOWN)
608 {
609 /* check if processor is retiring instructions */
610 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
611 {
612 target->state = TARGET_RUNNING;
613 return ERROR_OK;
614 }
615 }
616
617 return ERROR_OK;
618 }
619
620 static int cortex_m3_halt(struct target *target)
621 {
622 LOG_DEBUG("target->state: %s",
623 target_state_name(target));
624
625 if (target->state == TARGET_HALTED)
626 {
627 LOG_DEBUG("target was already halted");
628 return ERROR_OK;
629 }
630
631 if (target->state == TARGET_UNKNOWN)
632 {
633 LOG_WARNING("target was in unknown state when halt was requested");
634 }
635
636 if (target->state == TARGET_RESET)
637 {
638 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
639 {
640 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
641 return ERROR_TARGET_FAILURE;
642 }
643 else
644 {
645 /* we came here in a reset_halt or reset_init sequence
646 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
647 */
648 target->debug_reason = DBG_REASON_DBGRQ;
649
650 return ERROR_OK;
651 }
652 }
653
654 /* Write to Debug Halting Control and Status Register */
655 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
656
657 target->debug_reason = DBG_REASON_DBGRQ;
658
659 return ERROR_OK;
660 }
661
662 static int cortex_m3_soft_reset_halt(struct target *target)
663 {
664 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
665 struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
666 uint32_t dcb_dhcsr = 0;
667 int retval, timeout = 0;
668
669 /* Enter debug state on reset; restore DEMCR in endreset_event() */
670 retval = mem_ap_write_u32(swjdp, DCB_DEMCR,
671 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
672 if (retval != ERROR_OK)
673 return retval;
674
675 /* Request a core-only reset */
676 retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
677 AIRCR_VECTKEY | AIRCR_VECTRESET);
678 if (retval != ERROR_OK)
679 return retval;
680 target->state = TARGET_RESET;
681
682 /* registers are now invalid */
683 register_cache_invalidate(cortex_m3->armv7m.core_cache);
684
685 while (timeout < 100)
686 {
687 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
688 if (retval == ERROR_OK)
689 {
690 retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
691 &cortex_m3->nvic_dfsr);
692 if (retval != ERROR_OK)
693 return retval;
694 if ((dcb_dhcsr & S_HALT)
695 && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
696 {
697 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
698 "DFSR 0x%08x",
699 (unsigned) dcb_dhcsr,
700 (unsigned) cortex_m3->nvic_dfsr);
701 cortex_m3_poll(target);
702 /* FIXME restore user's vector catch config */
703 return ERROR_OK;
704 }
705 else
706 LOG_DEBUG("waiting for system reset-halt, "
707 "DHCSR 0x%08x, %d ms",
708 (unsigned) dcb_dhcsr, timeout);
709 }
710 timeout++;
711 alive_sleep(1);
712 }
713
714 return ERROR_OK;
715 }
716
717 static void cortex_m3_enable_breakpoints(struct target *target)
718 {
719 struct breakpoint *breakpoint = target->breakpoints;
720
721 /* set any pending breakpoints */
722 while (breakpoint)
723 {
724 if (!breakpoint->set)
725 cortex_m3_set_breakpoint(target, breakpoint);
726 breakpoint = breakpoint->next;
727 }
728 }
729
730 static int cortex_m3_resume(struct target *target, int current,
731 uint32_t address, int handle_breakpoints, int debug_execution)
732 {
733 struct armv7m_common *armv7m = target_to_armv7m(target);
734 struct breakpoint *breakpoint = NULL;
735 uint32_t resume_pc;
736 struct reg *r;
737
738 if (target->state != TARGET_HALTED)
739 {
740 LOG_WARNING("target not halted");
741 return ERROR_TARGET_NOT_HALTED;
742 }
743
744 if (!debug_execution)
745 {
746 target_free_all_working_areas(target);
747 cortex_m3_enable_breakpoints(target);
748 cortex_m3_enable_watchpoints(target);
749 }
750
751 if (debug_execution)
752 {
753 r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK;
754
755 /* Disable interrupts */
756 /* We disable interrupts in the PRIMASK register instead of
757 * masking with C_MASKINTS. This is probably the same issue
758 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
759 * in parallel with disabled interrupts can cause local faults
760 * to not be taken.
761 *
762 * REVISIT this clearly breaks non-debug execution, since the
763 * PRIMASK register state isn't saved/restored... workaround
764 * by never resuming app code after debug execution.
765 */
766 buf_set_u32(r->value, 0, 1, 1);
767 r->dirty = true;
768 r->valid = true;
769
770 /* Make sure we are in Thumb mode */
771 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
772 buf_set_u32(r->value, 24, 1, 1);
773 r->dirty = true;
774 r->valid = true;
775 }
776
777 /* current = 1: continue on current pc, otherwise continue at <address> */
778 r = armv7m->arm.pc;
779 if (!current)
780 {
781 buf_set_u32(r->value, 0, 32, address);
782 r->dirty = true;
783 r->valid = true;
784 }
785
786 /* if we halted last time due to a bkpt instruction
787 * then we have to manually step over it, otherwise
788 * the core will break again */
789
790 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
791 && !debug_execution)
792 {
793 armv7m_maybe_skip_bkpt_inst(target, NULL);
794 }
795
796 resume_pc = buf_get_u32(r->value, 0, 32);
797
798 armv7m_restore_context(target);
799
800 /* the front-end may request us not to handle breakpoints */
801 if (handle_breakpoints)
802 {
803 /* Single step past breakpoint at current address */
804 if ((breakpoint = breakpoint_find(target, resume_pc)))
805 {
806 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
807 breakpoint->address,
808 breakpoint->unique_id);
809 cortex_m3_unset_breakpoint(target, breakpoint);
810 cortex_m3_single_step_core(target);
811 cortex_m3_set_breakpoint(target, breakpoint);
812 }
813 }
814
815 /* Restart core */
816 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
817
818 target->debug_reason = DBG_REASON_NOTHALTED;
819
820 /* registers are now invalid */
821 register_cache_invalidate(armv7m->core_cache);
822
823 if (!debug_execution)
824 {
825 target->state = TARGET_RUNNING;
826 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
827 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
828 }
829 else
830 {
831 target->state = TARGET_DEBUG_RUNNING;
832 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
833 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
834 }
835
836 return ERROR_OK;
837 }
838
839 /* int irqstepcount = 0; */
840 static int cortex_m3_step(struct target *target, int current,
841 uint32_t address, int handle_breakpoints)
842 {
843 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
844 struct armv7m_common *armv7m = &cortex_m3->armv7m;
845 struct adiv5_dap *swjdp = &armv7m->dap;
846 struct breakpoint *breakpoint = NULL;
847 struct reg *pc = armv7m->arm.pc;
848 bool bkpt_inst_found = false;
849
850 if (target->state != TARGET_HALTED)
851 {
852 LOG_WARNING("target not halted");
853 return ERROR_TARGET_NOT_HALTED;
854 }
855
856 /* current = 1: continue on current pc, otherwise continue at <address> */
857 if (!current)
858 buf_set_u32(pc->value, 0, 32, address);
859
860 /* the front-end may request us not to handle breakpoints */
861 if (handle_breakpoints) {
862 breakpoint = breakpoint_find(target,
863 buf_get_u32(pc->value, 0, 32));
864 if (breakpoint)
865 cortex_m3_unset_breakpoint(target, breakpoint);
866 }
867
868 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
869
870 target->debug_reason = DBG_REASON_SINGLESTEP;
871
872 armv7m_restore_context(target);
873
874 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
875
876 /* if no bkpt instruction is found at pc then we can perform
877 * a normal step, otherwise we have to manually step over the bkpt
878 * instruction - as such simulate a step */
879 if (bkpt_inst_found == false)
880 {
881 /* set step and clear halt */
882 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
883 }
884
885 int retval;
886 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
887 if (retval != ERROR_OK)
888 return retval;
889
890 /* registers are now invalid */
891 register_cache_invalidate(cortex_m3->armv7m.core_cache);
892
893 if (breakpoint)
894 cortex_m3_set_breakpoint(target, breakpoint);
895
896 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
897 " nvic_icsr = 0x%" PRIx32,
898 cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
899
900 retval = cortex_m3_debug_entry(target);
901 if (retval != ERROR_OK)
902 return retval;
903 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
904
905 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
906 " nvic_icsr = 0x%" PRIx32,
907 cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
908
909 return ERROR_OK;
910 }
911
912 static int cortex_m3_assert_reset(struct target *target)
913 {
914 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
915 struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
916 int assert_srst = 1;
917
918 LOG_DEBUG("target->state: %s",
919 target_state_name(target));
920
921 enum reset_types jtag_reset_config = jtag_get_reset_config();
922
923 /*
924 * We can reset Cortex-M3 targets using just the NVIC without
925 * requiring SRST, getting a SoC reset (or a core-only reset)
926 * instead of a system reset.
927 */
928 if (!(jtag_reset_config & RESET_HAS_SRST))
929 assert_srst = 0;
930
931 /* Enable debug requests */
932 int retval;
933 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
934 if (retval != ERROR_OK)
935 return retval;
936 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
937 {
938 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
939 if (retval != ERROR_OK)
940 return retval;
941 }
942
943 retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
944 if (retval != ERROR_OK)
945 return retval;
946
947 if (!target->reset_halt)
948 {
949 /* Set/Clear C_MASKINTS in a separate operation */
950 if (cortex_m3->dcb_dhcsr & C_MASKINTS)
951 {
952 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
953 DBGKEY | C_DEBUGEN | C_HALT);
954 if (retval != ERROR_OK)
955 return retval;
956 }
957
958 /* clear any debug flags before resuming */
959 cortex_m3_clear_halt(target);
960
961 /* clear C_HALT in dhcsr reg */
962 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
963 }
964 else
965 {
966 /* Halt in debug on reset; endreset_event() restores DEMCR.
967 *
968 * REVISIT catching BUSERR presumably helps to defend against
969 * bad vector table entries. Should this include MMERR or
970 * other flags too?
971 */
972 retval = mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
973 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
974 if (retval != ERROR_OK)
975 return retval;
976 }
977
978 /*
979 * When nRST is asserted on most Stellaris devices, it clears some of
980 * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
981 * and OpenOCD depends on those TRMs. So we won't use SRST on those
982 * chips. (Only power-on reset should affect debug state, beyond a
983 * few specified bits; not the chip's nRST input, wired to SRST.)
984 *
985 * REVISIT current errata specs don't seem to cover this issue.
986 * Do we have more details than this email?
987 * https://lists.berlios.de/pipermail
988 * /openocd-development/2008-August/003065.html
989 */
990 if (strcmp(target->variant, "lm3s") == 0)
991 {
992 /* Check for silicon revisions with the issue. */
993 uint32_t did0;
994
995 if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
996 {
997 switch ((did0 >> 16) & 0xff)
998 {
999 case 0:
1000 /* all Sandstorm suffer issue */
1001 assert_srst = 0;
1002 break;
1003
1004 case 1:
1005 case 3:
1006 /* Fury and DustDevil rev A have
1007 * this nRST problem. It should
1008 * be fixed in rev B silicon.
1009 */
1010 if (((did0 >> 8) & 0xff) == 0)
1011 assert_srst = 0;
1012 break;
1013 case 4:
1014 /* Tempest should be fine. */
1015 break;
1016 }
1017 }
1018 }
1019
1020 if (assert_srst)
1021 {
1022 /* default to asserting srst */
1023 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1024 {
1025 jtag_add_reset(1, 1);
1026 }
1027 else
1028 {
1029 jtag_add_reset(0, 1);
1030 }
1031 }
1032 else
1033 {
1034 /* Use a standard Cortex-M3 software reset mechanism.
1035 * SYSRESETREQ will reset SoC peripherals outside the
1036 * core, like watchdog timers, if the SoC wires it up
1037 * correctly. Else VECRESET can reset just the core.
1038 */
1039 retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
1040 AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
1041 if (retval != ERROR_OK)
1042 return retval;
1043 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
1044
1045 {
1046 /* I do not know why this is necessary, but it
1047 * fixes strange effects (step/resume cause NMI
1048 * after reset) on LM3S6918 -- Michael Schwingen
1049 */
1050 uint32_t tmp;
1051 retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
1052 if (retval != ERROR_OK)
1053 return retval;
1054 }
1055 }
1056
1057 target->state = TARGET_RESET;
1058 jtag_add_sleep(50000);
1059
1060 register_cache_invalidate(cortex_m3->armv7m.core_cache);
1061
1062 if (target->reset_halt)
1063 {
1064 if ((retval = target_halt(target)) != ERROR_OK)
1065 return retval;
1066 }
1067
1068 return ERROR_OK;
1069 }
1070
1071 static int cortex_m3_deassert_reset(struct target *target)
1072 {
1073 LOG_DEBUG("target->state: %s",
1074 target_state_name(target));
1075
1076 /* deassert reset lines */
1077 jtag_add_reset(0, 0);
1078
1079 return ERROR_OK;
1080 }
1081
1082 static int
1083 cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1084 {
1085 int retval;
1086 int fp_num = 0;
1087 uint32_t hilo;
1088 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1089 struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
1090
1091 if (breakpoint->set)
1092 {
1093 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
1094 return ERROR_OK;
1095 }
1096
1097 if (cortex_m3->auto_bp_type)
1098 {
1099 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1100 }
1101
1102 if (breakpoint->type == BKPT_HARD)
1103 {
1104 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
1105 fp_num++;
1106 if (fp_num >= cortex_m3->fp_num_code)
1107 {
1108 LOG_ERROR("Can not find free FPB Comparator!");
1109 return ERROR_FAIL;
1110 }
1111 breakpoint->set = fp_num + 1;
1112 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1113 comparator_list[fp_num].used = 1;
1114 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
1115 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
1116 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
1117 if (!cortex_m3->fpb_enabled)
1118 {
1119 LOG_DEBUG("FPB wasn't enabled, do it now");
1120 target_write_u32(target, FP_CTRL, 3);
1121 }
1122 }
1123 else if (breakpoint->type == BKPT_SOFT)
1124 {
1125 uint8_t code[4];
1126
1127 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1128 * semihosting; don't use that. Otherwise the BKPT
1129 * parameter is arbitrary.
1130 */
1131 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1132 retval = target_read_memory(target,
1133 breakpoint->address & 0xFFFFFFFE,
1134 breakpoint->length, 1,
1135 breakpoint->orig_instr);
1136 if (retval != ERROR_OK)
1137 return retval;
1138 retval = target_write_memory(target,
1139 breakpoint->address & 0xFFFFFFFE,
1140 breakpoint->length, 1,
1141 code);
1142 if (retval != ERROR_OK)
1143 return retval;
1144 breakpoint->set = true;
1145 }
1146
1147 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1148 breakpoint->unique_id,
1149 (int)(breakpoint->type),
1150 breakpoint->address,
1151 breakpoint->length,
1152 breakpoint->set);
1153
1154 return ERROR_OK;
1155 }
1156
1157 static int
1158 cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1159 {
1160 int retval;
1161 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1162 struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
1163
1164 if (!breakpoint->set)
1165 {
1166 LOG_WARNING("breakpoint not set");
1167 return ERROR_OK;
1168 }
1169
1170 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1171 breakpoint->unique_id,
1172 (int)(breakpoint->type),
1173 breakpoint->address,
1174 breakpoint->length,
1175 breakpoint->set);
1176
1177 if (breakpoint->type == BKPT_HARD)
1178 {
1179 int fp_num = breakpoint->set - 1;
1180 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
1181 {
1182 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1183 return ERROR_OK;
1184 }
1185 comparator_list[fp_num].used = 0;
1186 comparator_list[fp_num].fpcr_value = 0;
1187 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
1188 }
1189 else
1190 {
1191 /* restore original instruction (kept in target endianness) */
1192 if (breakpoint->length == 4)
1193 {
1194 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
1195 {
1196 return retval;
1197 }
1198 }
1199 else
1200 {
1201 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
1202 {
1203 return retval;
1204 }
1205 }
1206 }
1207 breakpoint->set = false;
1208
1209 return ERROR_OK;
1210 }
1211
1212 static int
1213 cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1214 {
1215 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1216
1217 if (cortex_m3->auto_bp_type)
1218 {
1219 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1220 #ifdef ARMV7_GDB_HACKS
1221 if (breakpoint->length != 2) {
1222 /* XXX Hack: Replace all breakpoints with length != 2 with
1223 * a hardware breakpoint. */
1224 breakpoint->type = BKPT_HARD;
1225 breakpoint->length = 2;
1226 }
1227 #endif
1228 }
1229
1230 if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
1231 {
1232 LOG_INFO("flash patch comparator requested outside code memory region");
1233 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1234 }
1235
1236 if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
1237 {
1238 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1239 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1240 }
1241
1242 if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
1243 {
1244 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1245 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1246 }
1247
1248 if ((breakpoint->length != 2))
1249 {
1250 LOG_INFO("only breakpoints of two bytes length supported");
1251 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1252 }
1253
1254 if (breakpoint->type == BKPT_HARD)
1255 cortex_m3->fp_code_available--;
1256 cortex_m3_set_breakpoint(target, breakpoint);
1257
1258 return ERROR_OK;
1259 }
1260
1261 static int
1262 cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1263 {
1264 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1265
1266 /* REVISIT why check? FBP can be updated with core running ... */
1267 if (target->state != TARGET_HALTED)
1268 {
1269 LOG_WARNING("target not halted");
1270 return ERROR_TARGET_NOT_HALTED;
1271 }
1272
1273 if (cortex_m3->auto_bp_type)
1274 {
1275 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1276 }
1277
1278 if (breakpoint->set)
1279 {
1280 cortex_m3_unset_breakpoint(target, breakpoint);
1281 }
1282
1283 if (breakpoint->type == BKPT_HARD)
1284 cortex_m3->fp_code_available++;
1285
1286 return ERROR_OK;
1287 }
1288
1289 static int
1290 cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1291 {
1292 int dwt_num = 0;
1293 uint32_t mask, temp;
1294 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1295
1296 /* watchpoint params were validated earlier */
1297 mask = 0;
1298 temp = watchpoint->length;
1299 while (temp) {
1300 temp >>= 1;
1301 mask++;
1302 }
1303 mask--;
1304
1305 /* REVISIT Don't fully trust these "not used" records ... users
1306 * may set up breakpoints by hand, e.g. dual-address data value
1307 * watchpoint using comparator #1; comparator #0 matching cycle
1308 * count; send data trace info through ITM and TPIU; etc
1309 */
1310 struct cortex_m3_dwt_comparator *comparator;
1311
1312 for (comparator = cortex_m3->dwt_comparator_list;
1313 comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1314 comparator++, dwt_num++)
1315 continue;
1316 if (dwt_num >= cortex_m3->dwt_num_comp)
1317 {
1318 LOG_ERROR("Can not find free DWT Comparator");
1319 return ERROR_FAIL;
1320 }
1321 comparator->used = 1;
1322 watchpoint->set = dwt_num + 1;
1323
1324 comparator->comp = watchpoint->address;
1325 target_write_u32(target, comparator->dwt_comparator_address + 0,
1326 comparator->comp);
1327
1328 comparator->mask = mask;
1329 target_write_u32(target, comparator->dwt_comparator_address + 4,
1330 comparator->mask);
1331
1332 switch (watchpoint->rw) {
1333 case WPT_READ:
1334 comparator->function = 5;
1335 break;
1336 case WPT_WRITE:
1337 comparator->function = 6;
1338 break;
1339 case WPT_ACCESS:
1340 comparator->function = 7;
1341 break;
1342 }
1343 target_write_u32(target, comparator->dwt_comparator_address + 8,
1344 comparator->function);
1345
1346 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1347 watchpoint->unique_id, dwt_num,
1348 (unsigned) comparator->comp,
1349 (unsigned) comparator->mask,
1350 (unsigned) comparator->function);
1351 return ERROR_OK;
1352 }
1353
1354 static int
1355 cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1356 {
1357 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1358 struct cortex_m3_dwt_comparator *comparator;
1359 int dwt_num;
1360
1361 if (!watchpoint->set)
1362 {
1363 LOG_WARNING("watchpoint (wpid: %d) not set",
1364 watchpoint->unique_id);
1365 return ERROR_OK;
1366 }
1367
1368 dwt_num = watchpoint->set - 1;
1369
1370 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1371 watchpoint->unique_id, dwt_num,
1372 (unsigned) watchpoint->address);
1373
1374 if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
1375 {
1376 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1377 return ERROR_OK;
1378 }
1379
1380 comparator = cortex_m3->dwt_comparator_list + dwt_num;
1381 comparator->used = 0;
1382 comparator->function = 0;
1383 target_write_u32(target, comparator->dwt_comparator_address + 8,
1384 comparator->function);
1385
1386 watchpoint->set = false;
1387
1388 return ERROR_OK;
1389 }
1390
1391 static int
1392 cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1393 {
1394 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1395
1396 if (cortex_m3->dwt_comp_available < 1)
1397 {
1398 LOG_DEBUG("no comparators?");
1399 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1400 }
1401
1402 /* hardware doesn't support data value masking */
1403 if (watchpoint->mask != ~(uint32_t)0) {
1404 LOG_DEBUG("watchpoint value masks not supported");
1405 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1406 }
1407
1408 /* hardware allows address masks of up to 32K */
1409 unsigned mask;
1410
1411 for (mask = 0; mask < 16; mask++) {
1412 if ((1u << mask) == watchpoint->length)
1413 break;
1414 }
1415 if (mask == 16) {
1416 LOG_DEBUG("unsupported watchpoint length");
1417 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1418 }
1419 if (watchpoint->address & ((1 << mask) - 1)) {
1420 LOG_DEBUG("watchpoint address is unaligned");
1421 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1422 }
1423
1424 /* Caller doesn't seem to be able to describe watching for data
1425 * values of zero; that flags "no value".
1426 *
1427 * REVISIT This DWT may well be able to watch for specific data
1428 * values. Requires comparator #1 to set DATAVMATCH and match
1429 * the data, and another comparator (DATAVADDR0) matching addr.
1430 */
1431 if (watchpoint->value) {
1432 LOG_DEBUG("data value watchpoint not YET supported");
1433 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1434 }
1435
1436 cortex_m3->dwt_comp_available--;
1437 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1438
1439 return ERROR_OK;
1440 }
1441
1442 static int
1443 cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1444 {
1445 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1446
1447 /* REVISIT why check? DWT can be updated with core running ... */
1448 if (target->state != TARGET_HALTED)
1449 {
1450 LOG_WARNING("target not halted");
1451 return ERROR_TARGET_NOT_HALTED;
1452 }
1453
1454 if (watchpoint->set)
1455 {
1456 cortex_m3_unset_watchpoint(target, watchpoint);
1457 }
1458
1459 cortex_m3->dwt_comp_available++;
1460 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1461
1462 return ERROR_OK;
1463 }
1464
1465 static void cortex_m3_enable_watchpoints(struct target *target)
1466 {
1467 struct watchpoint *watchpoint = target->watchpoints;
1468
1469 /* set any pending watchpoints */
1470 while (watchpoint)
1471 {
1472 if (!watchpoint->set)
1473 cortex_m3_set_watchpoint(target, watchpoint);
1474 watchpoint = watchpoint->next;
1475 }
1476 }
1477
1478 static int cortex_m3_load_core_reg_u32(struct target *target,
1479 enum armv7m_regtype type, uint32_t num, uint32_t * value)
1480 {
1481 int retval;
1482 struct armv7m_common *armv7m = target_to_armv7m(target);
1483 struct adiv5_dap *swjdp = &armv7m->dap;
1484
1485 /* NOTE: we "know" here that the register identifiers used
1486 * in the v7m header match the Cortex-M3 Debug Core Register
1487 * Selector values for R0..R15, xPSR, MSP, and PSP.
1488 */
1489 switch (num) {
1490 case 0 ... 18:
1491 /* read a normal core register */
1492 retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1493
1494 if (retval != ERROR_OK)
1495 {
1496 LOG_ERROR("JTAG failure %i",retval);
1497 return ERROR_JTAG_DEVICE_ERROR;
1498 }
1499 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value);
1500 break;
1501
1502 case ARMV7M_PRIMASK:
1503 case ARMV7M_BASEPRI:
1504 case ARMV7M_FAULTMASK:
1505 case ARMV7M_CONTROL:
1506 /* Cortex-M3 packages these four registers as bitfields
1507 * in one Debug Core register. So say r0 and r2 docs;
1508 * it was removed from r1 docs, but still works.
1509 */
1510 cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1511
1512 switch (num)
1513 {
1514 case ARMV7M_PRIMASK:
1515 *value = buf_get_u32((uint8_t*)value, 0, 1);
1516 break;
1517
1518 case ARMV7M_BASEPRI:
1519 *value = buf_get_u32((uint8_t*)value, 8, 8);
1520 break;
1521
1522 case ARMV7M_FAULTMASK:
1523 *value = buf_get_u32((uint8_t*)value, 16, 1);
1524 break;
1525
1526 case ARMV7M_CONTROL:
1527 *value = buf_get_u32((uint8_t*)value, 24, 2);
1528 break;
1529 }
1530
1531 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1532 break;
1533
1534 default:
1535 return ERROR_INVALID_ARGUMENTS;
1536 }
1537
1538 return ERROR_OK;
1539 }
1540
1541 static int cortex_m3_store_core_reg_u32(struct target *target,
1542 enum armv7m_regtype type, uint32_t num, uint32_t value)
1543 {
1544 int retval;
1545 uint32_t reg;
1546 struct armv7m_common *armv7m = target_to_armv7m(target);
1547 struct adiv5_dap *swjdp = &armv7m->dap;
1548
1549 #ifdef ARMV7_GDB_HACKS
1550 /* If the LR register is being modified, make sure it will put us
1551 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1552 * hack to deal with the fact that gdb will sometimes "forge"
1553 * return addresses, and doesn't set the LSB correctly (i.e., when
1554 * printing expressions containing function calls, it sets LR = 0.)
1555 * Valid exception return codes have bit 0 set too.
1556 */
1557 if (num == ARMV7M_R14)
1558 value |= 0x01;
1559 #endif
1560
1561 /* NOTE: we "know" here that the register identifiers used
1562 * in the v7m header match the Cortex-M3 Debug Core Register
1563 * Selector values for R0..R15, xPSR, MSP, and PSP.
1564 */
1565 switch (num) {
1566 case 0 ... 18:
1567 retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1568 if (retval != ERROR_OK)
1569 {
1570 struct reg *r;
1571
1572 LOG_ERROR("JTAG failure %i", retval);
1573 r = armv7m->core_cache->reg_list + num;
1574 r->dirty = r->valid;
1575 return ERROR_JTAG_DEVICE_ERROR;
1576 }
1577 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1578 break;
1579
1580 case ARMV7M_PRIMASK:
1581 case ARMV7M_BASEPRI:
1582 case ARMV7M_FAULTMASK:
1583 case ARMV7M_CONTROL:
1584 /* Cortex-M3 packages these four registers as bitfields
1585 * in one Debug Core register. So say r0 and r2 docs;
1586 * it was removed from r1 docs, but still works.
1587 */
1588 cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
1589
1590 switch (num)
1591 {
1592 case ARMV7M_PRIMASK:
1593 buf_set_u32((uint8_t*)&reg, 0, 1, value);
1594 break;
1595
1596 case ARMV7M_BASEPRI:
1597 buf_set_u32((uint8_t*)&reg, 8, 8, value);
1598 break;
1599
1600 case ARMV7M_FAULTMASK:
1601 buf_set_u32((uint8_t*)&reg, 16, 1, value);
1602 break;
1603
1604 case ARMV7M_CONTROL:
1605 buf_set_u32((uint8_t*)&reg, 24, 2, value);
1606 break;
1607 }
1608
1609 cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1610
1611 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1612 break;
1613
1614 default:
1615 return ERROR_INVALID_ARGUMENTS;
1616 }
1617
1618 return ERROR_OK;
1619 }
1620
1621 static int cortex_m3_read_memory(struct target *target, uint32_t address,
1622 uint32_t size, uint32_t count, uint8_t *buffer)
1623 {
1624 struct armv7m_common *armv7m = target_to_armv7m(target);
1625 struct adiv5_dap *swjdp = &armv7m->dap;
1626 int retval = ERROR_INVALID_ARGUMENTS;
1627
1628 /* cortex_m3 handles unaligned memory access */
1629 if (count && buffer) {
1630 switch (size) {
1631 case 4:
1632 retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1633 break;
1634 case 2:
1635 retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1636 break;
1637 case 1:
1638 retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1639 break;
1640 }
1641 }
1642
1643 return retval;
1644 }
1645
1646 static int cortex_m3_write_memory(struct target *target, uint32_t address,
1647 uint32_t size, uint32_t count, uint8_t *buffer)
1648 {
1649 struct armv7m_common *armv7m = target_to_armv7m(target);
1650 struct adiv5_dap *swjdp = &armv7m->dap;
1651 int retval = ERROR_INVALID_ARGUMENTS;
1652
1653 if (count && buffer) {
1654 switch (size) {
1655 case 4:
1656 retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1657 break;
1658 case 2:
1659 retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1660 break;
1661 case 1:
1662 retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1663 break;
1664 }
1665 }
1666
1667 return retval;
1668 }
1669
1670 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
1671 uint32_t count, uint8_t *buffer)
1672 {
1673 return cortex_m3_write_memory(target, address, 4, count, buffer);
1674 }
1675
1676 static int cortex_m3_init_target(struct command_context *cmd_ctx,
1677 struct target *target)
1678 {
1679 armv7m_build_reg_cache(target);
1680 return ERROR_OK;
1681 }
1682
1683 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1684 * on r/w if the core is not running, and clear on resume or reset ... or
1685 * at least, in a post_restore_context() method.
1686 */
1687
1688 struct dwt_reg_state {
1689 struct target *target;
1690 uint32_t addr;
1691 uint32_t value; /* scratch/cache */
1692 };
1693
1694 static int cortex_m3_dwt_get_reg(struct reg *reg)
1695 {
1696 struct dwt_reg_state *state = reg->arch_info;
1697
1698 return target_read_u32(state->target, state->addr, &state->value);
1699 }
1700
1701 static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
1702 {
1703 struct dwt_reg_state *state = reg->arch_info;
1704
1705 return target_write_u32(state->target, state->addr,
1706 buf_get_u32(buf, 0, reg->size));
1707 }
1708
1709 struct dwt_reg {
1710 uint32_t addr;
1711 char *name;
1712 unsigned size;
1713 };
1714
1715 static struct dwt_reg dwt_base_regs[] = {
1716 { DWT_CTRL, "dwt_ctrl", 32, },
1717 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1718 * increments while the core is asleep.
1719 */
1720 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1721 /* plus some 8 bit counters, useful for profiling with TPIU */
1722 };
1723
1724 static struct dwt_reg dwt_comp[] = {
1725 #define DWT_COMPARATOR(i) \
1726 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1727 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1728 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1729 DWT_COMPARATOR(0),
1730 DWT_COMPARATOR(1),
1731 DWT_COMPARATOR(2),
1732 DWT_COMPARATOR(3),
1733 #undef DWT_COMPARATOR
1734 };
1735
1736 static const struct reg_arch_type dwt_reg_type = {
1737 .get = cortex_m3_dwt_get_reg,
1738 .set = cortex_m3_dwt_set_reg,
1739 };
1740
1741 static void
1742 cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1743 {
1744 struct dwt_reg_state *state;
1745
1746 state = calloc(1, sizeof *state);
1747 if (!state)
1748 return;
1749 state->addr = d->addr;
1750 state->target = t;
1751
1752 r->name = d->name;
1753 r->size = d->size;
1754 r->value = &state->value;
1755 r->arch_info = state;
1756 r->type = &dwt_reg_type;
1757 }
1758
1759 static void
1760 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
1761 {
1762 uint32_t dwtcr;
1763 struct reg_cache *cache;
1764 struct cortex_m3_dwt_comparator *comparator;
1765 int reg, i;
1766
1767 target_read_u32(target, DWT_CTRL, &dwtcr);
1768 if (!dwtcr) {
1769 LOG_DEBUG("no DWT");
1770 return;
1771 }
1772
1773 cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1774 cm3->dwt_comp_available = cm3->dwt_num_comp;
1775 cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1776 sizeof(struct cortex_m3_dwt_comparator));
1777 if (!cm3->dwt_comparator_list) {
1778 fail0:
1779 cm3->dwt_num_comp = 0;
1780 LOG_ERROR("out of mem");
1781 return;
1782 }
1783
1784 cache = calloc(1, sizeof *cache);
1785 if (!cache) {
1786 fail1:
1787 free(cm3->dwt_comparator_list);
1788 goto fail0;
1789 }
1790 cache->name = "cortex-m3 dwt registers";
1791 cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1792 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1793 if (!cache->reg_list) {
1794 free(cache);
1795 goto fail1;
1796 }
1797
1798 for (reg = 0; reg < 2; reg++)
1799 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1800 dwt_base_regs + reg);
1801
1802 comparator = cm3->dwt_comparator_list;
1803 for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1804 int j;
1805
1806 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1807 for (j = 0; j < 3; j++, reg++)
1808 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1809 dwt_comp + 3 * i + j);
1810 }
1811
1812 *register_get_last_cache_p(&target->reg_cache) = cache;
1813 cm3->dwt_cache = cache;
1814
1815 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1816 dwtcr, cm3->dwt_num_comp,
1817 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1818
1819 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1820 * implement single-address data value watchpoints ... so we
1821 * won't need to check it later, when asked to set one up.
1822 */
1823 }
1824
1825 static int cortex_m3_examine(struct target *target)
1826 {
1827 int retval;
1828 uint32_t cpuid, fpcr;
1829 int i;
1830 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1831 struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
1832
1833 if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
1834 return retval;
1835
1836 if (!target_was_examined(target))
1837 {
1838 target_set_examined(target);
1839
1840 /* Read from Device Identification Registers */
1841 retval = target_read_u32(target, CPUID, &cpuid);
1842 if (retval != ERROR_OK)
1843 return retval;
1844
1845 if (((cpuid >> 4) & 0xc3f) == 0xc23)
1846 LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected",
1847 (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
1848 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1849
1850 /* NOTE: FPB and DWT are both optional. */
1851
1852 /* Setup FPB */
1853 target_read_u32(target, FP_CTRL, &fpcr);
1854 cortex_m3->auto_bp_type = 1;
1855 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
1856 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1857 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1858 cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
1859 cortex_m3->fpb_enabled = fpcr & 1;
1860 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
1861 {
1862 cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1863 cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1864 }
1865 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
1866
1867 /* Setup DWT */
1868 cortex_m3_dwt_setup(cortex_m3, target);
1869
1870 /* These hardware breakpoints only work for code in flash! */
1871 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1872 target_name(target),
1873 cortex_m3->fp_num_code,
1874 cortex_m3->dwt_num_comp);
1875 }
1876
1877 return ERROR_OK;
1878 }
1879
1880 static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl)
1881 {
1882 uint16_t dcrdr;
1883 int retval;
1884
1885 mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1886 *ctrl = (uint8_t)dcrdr;
1887 *value = (uint8_t)(dcrdr >> 8);
1888
1889 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1890
1891 /* write ack back to software dcc register
1892 * signify we have read data */
1893 if (dcrdr & (1 << 0))
1894 {
1895 dcrdr = 0;
1896 retval = mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1897 if (retval != ERROR_OK)
1898 return retval;
1899 }
1900
1901 return ERROR_OK;
1902 }
1903
1904 static int cortex_m3_target_request_data(struct target *target,
1905 uint32_t size, uint8_t *buffer)
1906 {
1907 struct armv7m_common *armv7m = target_to_armv7m(target);
1908 struct adiv5_dap *swjdp = &armv7m->dap;
1909 uint8_t data;
1910 uint8_t ctrl;
1911 uint32_t i;
1912
1913 for (i = 0; i < (size * 4); i++)
1914 {
1915 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1916 buffer[i] = data;
1917 }
1918
1919 return ERROR_OK;
1920 }
1921
1922 static int cortex_m3_handle_target_request(void *priv)
1923 {
1924 struct target *target = priv;
1925 if (!target_was_examined(target))
1926 return ERROR_OK;
1927 struct armv7m_common *armv7m = target_to_armv7m(target);
1928 struct adiv5_dap *swjdp = &armv7m->dap;
1929
1930 if (!target->dbg_msg_enabled)
1931 return ERROR_OK;
1932
1933 if (target->state == TARGET_RUNNING)
1934 {
1935 uint8_t data;
1936 uint8_t ctrl;
1937
1938 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1939
1940 /* check if we have data */
1941 if (ctrl & (1 << 0))
1942 {
1943 uint32_t request;
1944
1945 /* we assume target is quick enough */
1946 request = data;
1947 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1948 request |= (data << 8);
1949 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1950 request |= (data << 16);
1951 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1952 request |= (data << 24);
1953 target_request(target, request);
1954 }
1955 }
1956
1957 return ERROR_OK;
1958 }
1959
1960 static int cortex_m3_init_arch_info(struct target *target,
1961 struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
1962 {
1963 int retval;
1964 struct armv7m_common *armv7m = &cortex_m3->armv7m;
1965
1966 armv7m_init_arch_info(target, armv7m);
1967
1968 /* prepare JTAG information for the new target */
1969 cortex_m3->jtag_info.tap = tap;
1970 cortex_m3->jtag_info.scann_size = 4;
1971
1972 armv7m->arm.dap = &armv7m->dap;
1973
1974 /* Leave (only) generic DAP stuff for debugport_init(); */
1975 armv7m->dap.jtag_info = &cortex_m3->jtag_info;
1976 armv7m->dap.memaccess_tck = 8;
1977 /* Cortex-M3 has 4096 bytes autoincrement range */
1978 armv7m->dap.tar_autoincr_block = (1 << 12);
1979
1980 /* register arch-specific functions */
1981 armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
1982
1983 armv7m->post_debug_entry = NULL;
1984
1985 armv7m->pre_restore_context = NULL;
1986
1987 armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
1988 armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
1989
1990 target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
1991
1992 if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
1993 {
1994 return retval;
1995 }
1996
1997 return ERROR_OK;
1998 }
1999
2000 static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
2001 {
2002 struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
2003
2004 cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
2005 cortex_m3_init_arch_info(target, cortex_m3, target->tap);
2006
2007 return ERROR_OK;
2008 }
2009
2010 /*--------------------------------------------------------------------------*/
2011
2012 static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
2013 struct cortex_m3_common *cm3)
2014 {
2015 if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
2016 command_print(cmd_ctx, "target is not a Cortex-M3");
2017 return ERROR_TARGET_INVALID;
2018 }
2019 return ERROR_OK;
2020 }
2021
2022 /*
2023 * Only stuff below this line should need to verify that its target
2024 * is a Cortex-M3. Everything else should have indirected through the
2025 * cortexm3_target structure, which is only used with CM3 targets.
2026 */
2027
2028 static const struct {
2029 char name[10];
2030 unsigned mask;
2031 } vec_ids[] = {
2032 { "hard_err", VC_HARDERR, },
2033 { "int_err", VC_INTERR, },
2034 { "bus_err", VC_BUSERR, },
2035 { "state_err", VC_STATERR, },
2036 { "chk_err", VC_CHKERR, },
2037 { "nocp_err", VC_NOCPERR, },
2038 { "mm_err", VC_MMERR, },
2039 { "reset", VC_CORERESET, },
2040 };
2041
2042 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
2043 {
2044 struct target *target = get_current_target(CMD_CTX);
2045 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2046 struct armv7m_common *armv7m = &cortex_m3->armv7m;
2047 struct adiv5_dap *swjdp = &armv7m->dap;
2048 uint32_t demcr = 0;
2049 int retval;
2050
2051 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2052 if (retval != ERROR_OK)
2053 return retval;
2054
2055 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2056 if (retval != ERROR_OK)
2057 return retval;
2058
2059 if (CMD_ARGC > 0) {
2060 unsigned catch = 0;
2061
2062 if (CMD_ARGC == 1) {
2063 if (strcmp(CMD_ARGV[0], "all") == 0) {
2064 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2065 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2066 | VC_MMERR | VC_CORERESET;
2067 goto write;
2068 } else if (strcmp(CMD_ARGV[0], "none") == 0) {
2069 goto write;
2070 }
2071 }
2072 while (CMD_ARGC-- > 0) {
2073 unsigned i;
2074 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2075 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2076 continue;
2077 catch |= vec_ids[i].mask;
2078 break;
2079 }
2080 if (i == ARRAY_SIZE(vec_ids)) {
2081 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2082 return ERROR_INVALID_ARGUMENTS;
2083 }
2084 }
2085 write:
2086 /* For now, armv7m->demcr only stores vector catch flags. */
2087 armv7m->demcr = catch;
2088
2089 demcr &= ~0xffff;
2090 demcr |= catch;
2091
2092 /* write, but don't assume it stuck (why not??) */
2093 retval = mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
2094 if (retval != ERROR_OK)
2095 return retval;
2096 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2097 if (retval != ERROR_OK)
2098 return retval;
2099
2100 /* FIXME be sure to clear DEMCR on clean server shutdown.
2101 * Otherwise the vector catch hardware could fire when there's
2102 * no debugger hooked up, causing much confusion...
2103 */
2104 }
2105
2106 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
2107 {
2108 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2109 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2110 }
2111
2112 return ERROR_OK;
2113 }
2114
2115 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
2116 {
2117 struct target *target = get_current_target(CMD_CTX);
2118 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2119 int retval;
2120
2121 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2122 if (retval != ERROR_OK)
2123 return retval;
2124
2125 if (target->state != TARGET_HALTED)
2126 {
2127 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2128 return ERROR_OK;
2129 }
2130
2131 if (CMD_ARGC > 0)
2132 {
2133 bool enable;
2134 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
2135 uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0);
2136 uint32_t mask_off = enable ? 0 : C_MASKINTS;
2137 cortex_m3_write_debug_halt_mask(target, mask_on, mask_off);
2138 }
2139
2140 command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
2141 (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
2142
2143 return ERROR_OK;
2144 }
2145
2146 static const struct command_registration cortex_m3_exec_command_handlers[] = {
2147 {
2148 .name = "maskisr",
2149 .handler = handle_cortex_m3_mask_interrupts_command,
2150 .mode = COMMAND_EXEC,
2151 .help = "mask cortex_m3 interrupts",
2152 .usage = "['on'|'off']",
2153 },
2154 {
2155 .name = "vector_catch",
2156 .handler = handle_cortex_m3_vector_catch_command,
2157 .mode = COMMAND_EXEC,
2158 .help = "configure hardware vectors to trigger debug entry",
2159 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2160 },
2161 COMMAND_REGISTRATION_DONE
2162 };
2163 static const struct command_registration cortex_m3_command_handlers[] = {
2164 {
2165 .chain = armv7m_command_handlers,
2166 },
2167 {
2168 .name = "cortex_m3",
2169 .mode = COMMAND_EXEC,
2170 .help = "Cortex-M3 command group",
2171 .chain = cortex_m3_exec_command_handlers,
2172 },
2173 COMMAND_REGISTRATION_DONE
2174 };
2175
2176 struct target_type cortexm3_target =
2177 {
2178 .name = "cortex_m3",
2179
2180 .poll = cortex_m3_poll,
2181 .arch_state = armv7m_arch_state,
2182
2183 .target_request_data = cortex_m3_target_request_data,
2184
2185 .halt = cortex_m3_halt,
2186 .resume = cortex_m3_resume,
2187 .step = cortex_m3_step,
2188
2189 .assert_reset = cortex_m3_assert_reset,
2190 .deassert_reset = cortex_m3_deassert_reset,
2191 .soft_reset_halt = cortex_m3_soft_reset_halt,
2192
2193 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2194
2195 .read_memory = cortex_m3_read_memory,
2196 .write_memory = cortex_m3_write_memory,
2197 .bulk_write_memory = cortex_m3_bulk_write_memory,
2198 .checksum_memory = armv7m_checksum_memory,
2199 .blank_check_memory = armv7m_blank_check_memory,
2200
2201 .run_algorithm = armv7m_run_algorithm,
2202
2203 .add_breakpoint = cortex_m3_add_breakpoint,
2204 .remove_breakpoint = cortex_m3_remove_breakpoint,
2205 .add_watchpoint = cortex_m3_add_watchpoint,
2206 .remove_watchpoint = cortex_m3_remove_watchpoint,
2207
2208 .commands = cortex_m3_command_handlers,
2209 .target_create = cortex_m3_target_create,
2210 .init_target = cortex_m3_init_target,
2211 .examine = cortex_m3_examine,
2212 };
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