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ADIv5: use new DAP ops for DP read/write
[openocd.git] / src / target / cortex_m3.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 * *
26 * *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
28 * *
29 ***************************************************************************/
30 #ifdef HAVE_CONFIG_H
31 #include "config.h"
32 #endif
33
34 #include "breakpoints.h"
35 #include "cortex_m3.h"
36 #include "target_request.h"
37 #include "target_type.h"
38 #include "arm_disassembler.h"
39 #include "register.h"
40 #include "arm_opcodes.h"
41 #include "arm_semihosting.h"
42
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FBP remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
48 *
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
51 * any longer.
52 */
53
54
55 /* forward declarations */
56 static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
57 static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
58 static void cortex_m3_enable_watchpoints(struct target *target);
59 static int cortex_m3_store_core_reg_u32(struct target *target,
60 enum armv7m_regtype type, uint32_t num, uint32_t value);
61
62 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
63 uint32_t *value, int regnum)
64 {
65 int retval;
66 uint32_t dcrdr;
67
68 /* because the DCB_DCRDR is used for the emulated dcc channel
69 * we have to save/restore the DCB_DCRDR when used */
70
71 mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
72
73 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
74 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
75 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
76
77 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
78 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
79 dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
80
81 retval = dap_run(swjdp);
82
83 /* restore DCB_DCRDR - this needs to be in a seperate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval == ERROR_OK)
86 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
87
88 return retval;
89 }
90
91 static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
92 uint32_t value, int regnum)
93 {
94 int retval;
95 uint32_t dcrdr;
96
97 /* because the DCB_DCRDR is used for the emulated dcc channel
98 * we have to save/restore the DCB_DCRDR when used */
99
100 mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
101
102 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
103 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
104 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
105
106 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
107 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
108 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
109
110 retval = dap_run(swjdp);
111
112 /* restore DCB_DCRDR - this needs to be in a seperate
113 * transaction otherwise the emulated DCC channel breaks */
114 if (retval == ERROR_OK)
115 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
116
117 return retval;
118 }
119
120 static int cortex_m3_write_debug_halt_mask(struct target *target,
121 uint32_t mask_on, uint32_t mask_off)
122 {
123 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
124 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
125
126 /* mask off status bits */
127 cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
128 /* create new register mask */
129 cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
130
131 return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
132 }
133
134 static int cortex_m3_clear_halt(struct target *target)
135 {
136 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
137 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
138
139 /* clear step if any */
140 cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
141
142 /* Read Debug Fault Status Register */
143 mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
144
145 /* Clear Debug Fault Status */
146 mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
147 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
148
149 return ERROR_OK;
150 }
151
152 static int cortex_m3_single_step_core(struct target *target)
153 {
154 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
155 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
156 uint32_t dhcsr_save;
157
158 /* backup dhcsr reg */
159 dhcsr_save = cortex_m3->dcb_dhcsr;
160
161 /* Mask interrupts before clearing halt, if done already. This avoids
162 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
163 * HALT can put the core into an unknown state.
164 */
165 if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
166 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
167 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
168 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
169 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
170 LOG_DEBUG(" ");
171
172 /* restore dhcsr reg */
173 cortex_m3->dcb_dhcsr = dhcsr_save;
174 cortex_m3_clear_halt(target);
175
176 return ERROR_OK;
177 }
178
179 static int cortex_m3_endreset_event(struct target *target)
180 {
181 int i;
182 int retval;
183 uint32_t dcb_demcr;
184 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
185 struct armv7m_common *armv7m = &cortex_m3->armv7m;
186 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
187 struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
188 struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
189
190 /* REVISIT The four debug monitor bits are currently ignored... */
191 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
192 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
193
194 /* this register is used for emulated dcc channel */
195 mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
196
197 /* Enable debug requests */
198 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
199 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
200 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
201
202 /* clear any interrupt masking */
203 cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
204
205 /* Enable features controlled by ITM and DWT blocks, and catch only
206 * the vectors we were told to pay attention to.
207 *
208 * Target firmware is responsible for all fault handling policy
209 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
210 * or manual updates to the NVIC SHCSR and CCR registers.
211 */
212 mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
213
214 /* Paranoia: evidently some (early?) chips don't preserve all the
215 * debug state (including FBP, DWT, etc) across reset...
216 */
217
218 /* Enable FPB */
219 target_write_u32(target, FP_CTRL, 3);
220 cortex_m3->fpb_enabled = 1;
221
222 /* Restore FPB registers */
223 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
224 {
225 target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
226 }
227
228 /* Restore DWT registers */
229 for (i = 0; i < cortex_m3->dwt_num_comp; i++)
230 {
231 target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
232 dwt_list[i].comp);
233 target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
234 dwt_list[i].mask);
235 target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
236 dwt_list[i].function);
237 }
238 retval = dap_run(swjdp);
239 if (retval != ERROR_OK)
240 return retval;
241
242 register_cache_invalidate(cortex_m3->armv7m.core_cache);
243
244 /* make sure we have latest dhcsr flags */
245 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
246
247 return retval;
248 }
249
250 static int cortex_m3_examine_debug_reason(struct target *target)
251 {
252 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
253
254 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
255 /* only check the debug reason if we don't know it already */
256
257 if ((target->debug_reason != DBG_REASON_DBGRQ)
258 && (target->debug_reason != DBG_REASON_SINGLESTEP))
259 {
260 if (cortex_m3->nvic_dfsr & DFSR_BKPT)
261 {
262 target->debug_reason = DBG_REASON_BREAKPOINT;
263 if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
264 target->debug_reason = DBG_REASON_WPTANDBKPT;
265 }
266 else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
267 target->debug_reason = DBG_REASON_WATCHPOINT;
268 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
269 target->debug_reason = DBG_REASON_BREAKPOINT;
270 else /* EXTERNAL, HALTED */
271 target->debug_reason = DBG_REASON_UNDEFINED;
272 }
273
274 return ERROR_OK;
275 }
276
277 static int cortex_m3_examine_exception_reason(struct target *target)
278 {
279 uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
280 struct armv7m_common *armv7m = target_to_armv7m(target);
281 struct swjdp_common *swjdp = &armv7m->swjdp_info;
282 int retval;
283
284 mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
285 switch (armv7m->exception_number)
286 {
287 case 2: /* NMI */
288 break;
289 case 3: /* Hard Fault */
290 mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
291 if (except_sr & 0x40000000)
292 {
293 mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
294 }
295 break;
296 case 4: /* Memory Management */
297 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
298 mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
299 break;
300 case 5: /* Bus Fault */
301 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
302 mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
303 break;
304 case 6: /* Usage Fault */
305 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
306 break;
307 case 11: /* SVCall */
308 break;
309 case 12: /* Debug Monitor */
310 mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
311 break;
312 case 14: /* PendSV */
313 break;
314 case 15: /* SysTick */
315 break;
316 default:
317 except_sr = 0;
318 break;
319 }
320 retval = dap_run(swjdp);
321 if (retval == ERROR_OK)
322 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
323 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
324 armv7m_exception_string(armv7m->exception_number),
325 shcsr, except_sr, cfsr, except_ar);
326 return retval;
327 }
328
329 /* PSP is used in some thread modes */
330 static const int armv7m_psp_reg_map[17] = {
331 ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
332 ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
333 ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
334 ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
335 ARMV7M_xPSR,
336 };
337
338 /* MSP is used in handler and some thread modes */
339 static const int armv7m_msp_reg_map[17] = {
340 ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
341 ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
342 ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
343 ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
344 ARMV7M_xPSR,
345 };
346
347 static int cortex_m3_debug_entry(struct target *target)
348 {
349 int i;
350 uint32_t xPSR;
351 int retval;
352 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
353 struct armv7m_common *armv7m = &cortex_m3->armv7m;
354 struct arm *arm = &armv7m->arm;
355 struct swjdp_common *swjdp = &armv7m->swjdp_info;
356 struct reg *r;
357
358 LOG_DEBUG(" ");
359
360 cortex_m3_clear_halt(target);
361 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
362
363 if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
364 return retval;
365
366 /* Examine target state and mode */
367 /* First load register acessible through core debug port*/
368 int num_regs = armv7m->core_cache->num_regs;
369
370 for (i = 0; i < num_regs; i++)
371 {
372 if (!armv7m->core_cache->reg_list[i].valid)
373 armv7m->read_core_reg(target, i);
374 }
375
376 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
377 xPSR = buf_get_u32(r->value, 0, 32);
378
379 #ifdef ARMV7_GDB_HACKS
380 /* FIXME this breaks on scan chains with more than one Cortex-M3.
381 * Instead, each CM3 should have its own dummy value...
382 */
383 /* copy real xpsr reg for gdb, setting thumb bit */
384 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
385 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
386 armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
387 armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
388 #endif
389
390 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
391 if (xPSR & 0xf00)
392 {
393 r->dirty = r->valid;
394 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
395 }
396
397 /* Are we in an exception handler */
398 if (xPSR & 0x1FF)
399 {
400 armv7m->core_mode = ARMV7M_MODE_HANDLER;
401 armv7m->exception_number = (xPSR & 0x1FF);
402
403 arm->core_mode = ARM_MODE_HANDLER;
404 arm->map = armv7m_msp_reg_map;
405 }
406 else
407 {
408 unsigned control = buf_get_u32(armv7m->core_cache
409 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
410
411 /* is this thread privileged? */
412 armv7m->core_mode = control & 1;
413 arm->core_mode = armv7m->core_mode
414 ? ARM_MODE_USER_THREAD
415 : ARM_MODE_THREAD;
416
417 /* which stack is it using? */
418 if (control & 2)
419 arm->map = armv7m_psp_reg_map;
420 else
421 arm->map = armv7m_msp_reg_map;
422
423 armv7m->exception_number = 0;
424 }
425
426 if (armv7m->exception_number)
427 {
428 cortex_m3_examine_exception_reason(target);
429 }
430
431 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
432 armv7m_mode_strings[armv7m->core_mode],
433 *(uint32_t*)(arm->pc->value),
434 target_state_name(target));
435
436 if (armv7m->post_debug_entry)
437 armv7m->post_debug_entry(target);
438
439 return ERROR_OK;
440 }
441
442 static int cortex_m3_poll(struct target *target)
443 {
444 int retval;
445 enum target_state prev_target_state = target->state;
446 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
447 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
448
449 /* Read from Debug Halting Control and Status Register */
450 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
451 if (retval != ERROR_OK)
452 {
453 target->state = TARGET_UNKNOWN;
454 return retval;
455 }
456
457 /* Recover from lockup. See ARMv7-M architecture spec,
458 * section B1.5.15 "Unrecoverable exception cases".
459 *
460 * REVISIT Is there a better way to report and handle this?
461 */
462 if (cortex_m3->dcb_dhcsr & S_LOCKUP) {
463 LOG_WARNING("%s -- clearing lockup after double fault",
464 target_name(target));
465 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
466 target->debug_reason = DBG_REASON_DBGRQ;
467
468 /* refresh status bits */
469 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
470 }
471
472 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
473 {
474 /* check if still in reset */
475 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
476
477 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
478 {
479 target->state = TARGET_RESET;
480 return ERROR_OK;
481 }
482 }
483
484 if (target->state == TARGET_RESET)
485 {
486 /* Cannot switch context while running so endreset is
487 * called with target->state == TARGET_RESET
488 */
489 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
490 cortex_m3->dcb_dhcsr);
491 cortex_m3_endreset_event(target);
492 target->state = TARGET_RUNNING;
493 prev_target_state = TARGET_RUNNING;
494 }
495
496 if (cortex_m3->dcb_dhcsr & S_HALT)
497 {
498 target->state = TARGET_HALTED;
499
500 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
501 {
502 if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
503 return retval;
504
505 if (arm_semihosting(target, &retval) != 0)
506 return retval;
507
508 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
509 }
510 if (prev_target_state == TARGET_DEBUG_RUNNING)
511 {
512 LOG_DEBUG(" ");
513 if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
514 return retval;
515
516 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
517 }
518 }
519
520 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
521 * How best to model low power modes?
522 */
523
524 if (target->state == TARGET_UNKNOWN)
525 {
526 /* check if processor is retiring instructions */
527 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
528 {
529 target->state = TARGET_RUNNING;
530 return ERROR_OK;
531 }
532 }
533
534 return ERROR_OK;
535 }
536
537 static int cortex_m3_halt(struct target *target)
538 {
539 LOG_DEBUG("target->state: %s",
540 target_state_name(target));
541
542 if (target->state == TARGET_HALTED)
543 {
544 LOG_DEBUG("target was already halted");
545 return ERROR_OK;
546 }
547
548 if (target->state == TARGET_UNKNOWN)
549 {
550 LOG_WARNING("target was in unknown state when halt was requested");
551 }
552
553 if (target->state == TARGET_RESET)
554 {
555 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
556 {
557 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
558 return ERROR_TARGET_FAILURE;
559 }
560 else
561 {
562 /* we came here in a reset_halt or reset_init sequence
563 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
564 */
565 target->debug_reason = DBG_REASON_DBGRQ;
566
567 return ERROR_OK;
568 }
569 }
570
571 /* Write to Debug Halting Control and Status Register */
572 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
573
574 target->debug_reason = DBG_REASON_DBGRQ;
575
576 return ERROR_OK;
577 }
578
579 static int cortex_m3_soft_reset_halt(struct target *target)
580 {
581 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
582 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
583 uint32_t dcb_dhcsr = 0;
584 int retval, timeout = 0;
585
586 /* Enter debug state on reset; restore DEMCR in endreset_event() */
587 mem_ap_write_u32(swjdp, DCB_DEMCR,
588 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
589
590 /* Request a core-only reset */
591 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
592 AIRCR_VECTKEY | AIRCR_VECTRESET);
593 target->state = TARGET_RESET;
594
595 /* registers are now invalid */
596 register_cache_invalidate(cortex_m3->armv7m.core_cache);
597
598 while (timeout < 100)
599 {
600 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
601 if (retval == ERROR_OK)
602 {
603 mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
604 &cortex_m3->nvic_dfsr);
605 if ((dcb_dhcsr & S_HALT)
606 && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
607 {
608 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
609 "DFSR 0x%08x",
610 (unsigned) dcb_dhcsr,
611 (unsigned) cortex_m3->nvic_dfsr);
612 cortex_m3_poll(target);
613 /* FIXME restore user's vector catch config */
614 return ERROR_OK;
615 }
616 else
617 LOG_DEBUG("waiting for system reset-halt, "
618 "DHCSR 0x%08x, %d ms",
619 (unsigned) dcb_dhcsr, timeout);
620 }
621 timeout++;
622 alive_sleep(1);
623 }
624
625 return ERROR_OK;
626 }
627
628 static void cortex_m3_enable_breakpoints(struct target *target)
629 {
630 struct breakpoint *breakpoint = target->breakpoints;
631
632 /* set any pending breakpoints */
633 while (breakpoint)
634 {
635 if (!breakpoint->set)
636 cortex_m3_set_breakpoint(target, breakpoint);
637 breakpoint = breakpoint->next;
638 }
639 }
640
641 static int cortex_m3_resume(struct target *target, int current,
642 uint32_t address, int handle_breakpoints, int debug_execution)
643 {
644 struct armv7m_common *armv7m = target_to_armv7m(target);
645 struct breakpoint *breakpoint = NULL;
646 uint32_t resume_pc;
647 struct reg *r;
648
649 if (target->state != TARGET_HALTED)
650 {
651 LOG_WARNING("target not halted");
652 return ERROR_TARGET_NOT_HALTED;
653 }
654
655 if (!debug_execution)
656 {
657 target_free_all_working_areas(target);
658 cortex_m3_enable_breakpoints(target);
659 cortex_m3_enable_watchpoints(target);
660 }
661
662 if (debug_execution)
663 {
664 r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK;
665
666 /* Disable interrupts */
667 /* We disable interrupts in the PRIMASK register instead of
668 * masking with C_MASKINTS. This is probably the same issue
669 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
670 * in parallel with disabled interrupts can cause local faults
671 * to not be taken.
672 *
673 * REVISIT this clearly breaks non-debug execution, since the
674 * PRIMASK register state isn't saved/restored... workaround
675 * by never resuming app code after debug execution.
676 */
677 buf_set_u32(r->value, 0, 1, 1);
678 r->dirty = true;
679 r->valid = true;
680
681 /* Make sure we are in Thumb mode */
682 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
683 buf_set_u32(r->value, 24, 1, 1);
684 r->dirty = true;
685 r->valid = true;
686 }
687
688 /* current = 1: continue on current pc, otherwise continue at <address> */
689 r = armv7m->arm.pc;
690 if (!current)
691 {
692 buf_set_u32(r->value, 0, 32, address);
693 r->dirty = true;
694 r->valid = true;
695 }
696
697 /* if we halted last time due to a bkpt instruction
698 * then we have to manually step over it, otherwise
699 * the core will break again */
700
701 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
702 && !debug_execution)
703 {
704 armv7m_maybe_skip_bkpt_inst(target, NULL);
705 }
706
707 resume_pc = buf_get_u32(r->value, 0, 32);
708
709 armv7m_restore_context(target);
710
711 /* the front-end may request us not to handle breakpoints */
712 if (handle_breakpoints)
713 {
714 /* Single step past breakpoint at current address */
715 if ((breakpoint = breakpoint_find(target, resume_pc)))
716 {
717 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
718 breakpoint->address,
719 breakpoint->unique_id);
720 cortex_m3_unset_breakpoint(target, breakpoint);
721 cortex_m3_single_step_core(target);
722 cortex_m3_set_breakpoint(target, breakpoint);
723 }
724 }
725
726 /* Restart core */
727 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
728
729 target->debug_reason = DBG_REASON_NOTHALTED;
730
731 /* registers are now invalid */
732 register_cache_invalidate(armv7m->core_cache);
733
734 if (!debug_execution)
735 {
736 target->state = TARGET_RUNNING;
737 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
738 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
739 }
740 else
741 {
742 target->state = TARGET_DEBUG_RUNNING;
743 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
744 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
745 }
746
747 return ERROR_OK;
748 }
749
750 /* int irqstepcount = 0; */
751 static int cortex_m3_step(struct target *target, int current,
752 uint32_t address, int handle_breakpoints)
753 {
754 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
755 struct armv7m_common *armv7m = &cortex_m3->armv7m;
756 struct swjdp_common *swjdp = &armv7m->swjdp_info;
757 struct breakpoint *breakpoint = NULL;
758 struct reg *pc = armv7m->arm.pc;
759 bool bkpt_inst_found = false;
760
761 if (target->state != TARGET_HALTED)
762 {
763 LOG_WARNING("target not halted");
764 return ERROR_TARGET_NOT_HALTED;
765 }
766
767 /* current = 1: continue on current pc, otherwise continue at <address> */
768 if (!current)
769 buf_set_u32(pc->value, 0, 32, address);
770
771 /* the front-end may request us not to handle breakpoints */
772 if (handle_breakpoints) {
773 breakpoint = breakpoint_find(target,
774 buf_get_u32(pc->value, 0, 32));
775 if (breakpoint)
776 cortex_m3_unset_breakpoint(target, breakpoint);
777 }
778
779 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
780
781 target->debug_reason = DBG_REASON_SINGLESTEP;
782
783 armv7m_restore_context(target);
784
785 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
786
787 /* if no bkpt instruction is found at pc then we can perform
788 * a normal step, otherwise we have to manually step over the bkpt
789 * instruction - as such simulate a step */
790 if (bkpt_inst_found == false)
791 {
792 /* set step and clear halt */
793 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
794 }
795
796 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
797
798 /* registers are now invalid */
799 register_cache_invalidate(cortex_m3->armv7m.core_cache);
800
801 if (breakpoint)
802 cortex_m3_set_breakpoint(target, breakpoint);
803
804 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
805 " nvic_icsr = 0x%" PRIx32,
806 cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
807
808 cortex_m3_debug_entry(target);
809 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
810
811 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
812 " nvic_icsr = 0x%" PRIx32,
813 cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
814
815 return ERROR_OK;
816 }
817
818 static int cortex_m3_assert_reset(struct target *target)
819 {
820 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
821 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
822 int assert_srst = 1;
823
824 LOG_DEBUG("target->state: %s",
825 target_state_name(target));
826
827 enum reset_types jtag_reset_config = jtag_get_reset_config();
828
829 /*
830 * We can reset Cortex-M3 targets using just the NVIC without
831 * requiring SRST, getting a SoC reset (or a core-only reset)
832 * instead of a system reset.
833 */
834 if (!(jtag_reset_config & RESET_HAS_SRST))
835 assert_srst = 0;
836
837 /* Enable debug requests */
838 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
839 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
840 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
841
842 mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
843
844 if (!target->reset_halt)
845 {
846 /* Set/Clear C_MASKINTS in a separate operation */
847 if (cortex_m3->dcb_dhcsr & C_MASKINTS)
848 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
849 DBGKEY | C_DEBUGEN | C_HALT);
850
851 /* clear any debug flags before resuming */
852 cortex_m3_clear_halt(target);
853
854 /* clear C_HALT in dhcsr reg */
855 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
856 }
857 else
858 {
859 /* Halt in debug on reset; endreset_event() restores DEMCR.
860 *
861 * REVISIT catching BUSERR presumably helps to defend against
862 * bad vector table entries. Should this include MMERR or
863 * other flags too?
864 */
865 mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
866 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
867 }
868
869 /*
870 * When nRST is asserted on most Stellaris devices, it clears some of
871 * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
872 * and OpenOCD depends on those TRMs. So we won't use SRST on those
873 * chips. (Only power-on reset should affect debug state, beyond a
874 * few specified bits; not the chip's nRST input, wired to SRST.)
875 *
876 * REVISIT current errata specs don't seem to cover this issue.
877 * Do we have more details than this email?
878 * https://lists.berlios.de/pipermail
879 * /openocd-development/2008-August/003065.html
880 */
881 if (strcmp(target->variant, "lm3s") == 0)
882 {
883 /* Check for silicon revisions with the issue. */
884 uint32_t did0;
885
886 if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
887 {
888 switch ((did0 >> 16) & 0xff)
889 {
890 case 0:
891 /* all Sandstorm suffer issue */
892 assert_srst = 0;
893 break;
894
895 case 1:
896 case 3:
897 /* Fury and DustDevil rev A have
898 * this nRST problem. It should
899 * be fixed in rev B silicon.
900 */
901 if (((did0 >> 8) & 0xff) == 0)
902 assert_srst = 0;
903 break;
904 case 4:
905 /* Tempest should be fine. */
906 break;
907 }
908 }
909 }
910
911 if (assert_srst)
912 {
913 /* default to asserting srst */
914 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
915 {
916 jtag_add_reset(1, 1);
917 }
918 else
919 {
920 jtag_add_reset(0, 1);
921 }
922 }
923 else
924 {
925 /* Use a standard Cortex-M3 software reset mechanism.
926 * SYSRESETREQ will reset SoC peripherals outside the
927 * core, like watchdog timers, if the SoC wires it up
928 * correctly. Else VECRESET can reset just the core.
929 */
930 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
931 AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
932 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
933
934 {
935 /* I do not know why this is necessary, but it
936 * fixes strange effects (step/resume cause NMI
937 * after reset) on LM3S6918 -- Michael Schwingen
938 */
939 uint32_t tmp;
940 mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
941 }
942 }
943
944 target->state = TARGET_RESET;
945 jtag_add_sleep(50000);
946
947 register_cache_invalidate(cortex_m3->armv7m.core_cache);
948
949 if (target->reset_halt)
950 {
951 int retval;
952 if ((retval = target_halt(target)) != ERROR_OK)
953 return retval;
954 }
955
956 return ERROR_OK;
957 }
958
959 static int cortex_m3_deassert_reset(struct target *target)
960 {
961 LOG_DEBUG("target->state: %s",
962 target_state_name(target));
963
964 /* deassert reset lines */
965 jtag_add_reset(0, 0);
966
967 return ERROR_OK;
968 }
969
970 static int
971 cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
972 {
973 int retval;
974 int fp_num = 0;
975 uint32_t hilo;
976 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
977 struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
978
979 if (breakpoint->set)
980 {
981 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
982 return ERROR_OK;
983 }
984
985 if (cortex_m3->auto_bp_type)
986 {
987 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
988 }
989
990 if (breakpoint->type == BKPT_HARD)
991 {
992 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
993 fp_num++;
994 if (fp_num >= cortex_m3->fp_num_code)
995 {
996 LOG_ERROR("Can not find free FPB Comparator!");
997 return ERROR_FAIL;
998 }
999 breakpoint->set = fp_num + 1;
1000 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1001 comparator_list[fp_num].used = 1;
1002 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
1003 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
1004 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
1005 if (!cortex_m3->fpb_enabled)
1006 {
1007 LOG_DEBUG("FPB wasn't enabled, do it now");
1008 target_write_u32(target, FP_CTRL, 3);
1009 }
1010 }
1011 else if (breakpoint->type == BKPT_SOFT)
1012 {
1013 uint8_t code[4];
1014
1015 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1016 * semihosting; don't use that. Otherwise the BKPT
1017 * parameter is arbitrary.
1018 */
1019 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1020 retval = target_read_memory(target,
1021 breakpoint->address & 0xFFFFFFFE,
1022 breakpoint->length, 1,
1023 breakpoint->orig_instr);
1024 if (retval != ERROR_OK)
1025 return retval;
1026 retval = target_write_memory(target,
1027 breakpoint->address & 0xFFFFFFFE,
1028 breakpoint->length, 1,
1029 code);
1030 if (retval != ERROR_OK)
1031 return retval;
1032 breakpoint->set = true;
1033 }
1034
1035 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1036 breakpoint->unique_id,
1037 (int)(breakpoint->type),
1038 breakpoint->address,
1039 breakpoint->length,
1040 breakpoint->set);
1041
1042 return ERROR_OK;
1043 }
1044
1045 static int
1046 cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1047 {
1048 int retval;
1049 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1050 struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
1051
1052 if (!breakpoint->set)
1053 {
1054 LOG_WARNING("breakpoint not set");
1055 return ERROR_OK;
1056 }
1057
1058 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1059 breakpoint->unique_id,
1060 (int)(breakpoint->type),
1061 breakpoint->address,
1062 breakpoint->length,
1063 breakpoint->set);
1064
1065 if (breakpoint->type == BKPT_HARD)
1066 {
1067 int fp_num = breakpoint->set - 1;
1068 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
1069 {
1070 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1071 return ERROR_OK;
1072 }
1073 comparator_list[fp_num].used = 0;
1074 comparator_list[fp_num].fpcr_value = 0;
1075 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
1076 }
1077 else
1078 {
1079 /* restore original instruction (kept in target endianness) */
1080 if (breakpoint->length == 4)
1081 {
1082 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
1083 {
1084 return retval;
1085 }
1086 }
1087 else
1088 {
1089 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
1090 {
1091 return retval;
1092 }
1093 }
1094 }
1095 breakpoint->set = false;
1096
1097 return ERROR_OK;
1098 }
1099
1100 static int
1101 cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1102 {
1103 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1104
1105 if (cortex_m3->auto_bp_type)
1106 {
1107 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1108 #ifdef ARMV7_GDB_HACKS
1109 if (breakpoint->length != 2) {
1110 /* XXX Hack: Replace all breakpoints with length != 2 with
1111 * a hardware breakpoint. */
1112 breakpoint->type = BKPT_HARD;
1113 breakpoint->length = 2;
1114 }
1115 #endif
1116 }
1117
1118 if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
1119 {
1120 LOG_INFO("flash patch comparator requested outside code memory region");
1121 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1122 }
1123
1124 if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
1125 {
1126 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1127 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1128 }
1129
1130 if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
1131 {
1132 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1133 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1134 }
1135
1136 if ((breakpoint->length != 2))
1137 {
1138 LOG_INFO("only breakpoints of two bytes length supported");
1139 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1140 }
1141
1142 if (breakpoint->type == BKPT_HARD)
1143 cortex_m3->fp_code_available--;
1144 cortex_m3_set_breakpoint(target, breakpoint);
1145
1146 return ERROR_OK;
1147 }
1148
1149 static int
1150 cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1151 {
1152 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1153
1154 /* REVISIT why check? FBP can be updated with core running ... */
1155 if (target->state != TARGET_HALTED)
1156 {
1157 LOG_WARNING("target not halted");
1158 return ERROR_TARGET_NOT_HALTED;
1159 }
1160
1161 if (cortex_m3->auto_bp_type)
1162 {
1163 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1164 }
1165
1166 if (breakpoint->set)
1167 {
1168 cortex_m3_unset_breakpoint(target, breakpoint);
1169 }
1170
1171 if (breakpoint->type == BKPT_HARD)
1172 cortex_m3->fp_code_available++;
1173
1174 return ERROR_OK;
1175 }
1176
1177 static int
1178 cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1179 {
1180 int dwt_num = 0;
1181 uint32_t mask, temp;
1182 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1183
1184 /* watchpoint params were validated earlier */
1185 mask = 0;
1186 temp = watchpoint->length;
1187 while (temp) {
1188 temp >>= 1;
1189 mask++;
1190 }
1191 mask--;
1192
1193 /* REVISIT Don't fully trust these "not used" records ... users
1194 * may set up breakpoints by hand, e.g. dual-address data value
1195 * watchpoint using comparator #1; comparator #0 matching cycle
1196 * count; send data trace info through ITM and TPIU; etc
1197 */
1198 struct cortex_m3_dwt_comparator *comparator;
1199
1200 for (comparator = cortex_m3->dwt_comparator_list;
1201 comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1202 comparator++, dwt_num++)
1203 continue;
1204 if (dwt_num >= cortex_m3->dwt_num_comp)
1205 {
1206 LOG_ERROR("Can not find free DWT Comparator");
1207 return ERROR_FAIL;
1208 }
1209 comparator->used = 1;
1210 watchpoint->set = dwt_num + 1;
1211
1212 comparator->comp = watchpoint->address;
1213 target_write_u32(target, comparator->dwt_comparator_address + 0,
1214 comparator->comp);
1215
1216 comparator->mask = mask;
1217 target_write_u32(target, comparator->dwt_comparator_address + 4,
1218 comparator->mask);
1219
1220 switch (watchpoint->rw) {
1221 case WPT_READ:
1222 comparator->function = 5;
1223 break;
1224 case WPT_WRITE:
1225 comparator->function = 6;
1226 break;
1227 case WPT_ACCESS:
1228 comparator->function = 7;
1229 break;
1230 }
1231 target_write_u32(target, comparator->dwt_comparator_address + 8,
1232 comparator->function);
1233
1234 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1235 watchpoint->unique_id, dwt_num,
1236 (unsigned) comparator->comp,
1237 (unsigned) comparator->mask,
1238 (unsigned) comparator->function);
1239 return ERROR_OK;
1240 }
1241
1242 static int
1243 cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1244 {
1245 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1246 struct cortex_m3_dwt_comparator *comparator;
1247 int dwt_num;
1248
1249 if (!watchpoint->set)
1250 {
1251 LOG_WARNING("watchpoint (wpid: %d) not set",
1252 watchpoint->unique_id);
1253 return ERROR_OK;
1254 }
1255
1256 dwt_num = watchpoint->set - 1;
1257
1258 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1259 watchpoint->unique_id, dwt_num,
1260 (unsigned) watchpoint->address);
1261
1262 if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
1263 {
1264 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1265 return ERROR_OK;
1266 }
1267
1268 comparator = cortex_m3->dwt_comparator_list + dwt_num;
1269 comparator->used = 0;
1270 comparator->function = 0;
1271 target_write_u32(target, comparator->dwt_comparator_address + 8,
1272 comparator->function);
1273
1274 watchpoint->set = false;
1275
1276 return ERROR_OK;
1277 }
1278
1279 static int
1280 cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1281 {
1282 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1283
1284 if (cortex_m3->dwt_comp_available < 1)
1285 {
1286 LOG_DEBUG("no comparators?");
1287 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1288 }
1289
1290 /* hardware doesn't support data value masking */
1291 if (watchpoint->mask != ~(uint32_t)0) {
1292 LOG_DEBUG("watchpoint value masks not supported");
1293 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1294 }
1295
1296 /* hardware allows address masks of up to 32K */
1297 unsigned mask;
1298
1299 for (mask = 0; mask < 16; mask++) {
1300 if ((1u << mask) == watchpoint->length)
1301 break;
1302 }
1303 if (mask == 16) {
1304 LOG_DEBUG("unsupported watchpoint length");
1305 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1306 }
1307 if (watchpoint->address & ((1 << mask) - 1)) {
1308 LOG_DEBUG("watchpoint address is unaligned");
1309 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1310 }
1311
1312 /* Caller doesn't seem to be able to describe watching for data
1313 * values of zero; that flags "no value".
1314 *
1315 * REVISIT This DWT may well be able to watch for specific data
1316 * values. Requires comparator #1 to set DATAVMATCH and match
1317 * the data, and another comparator (DATAVADDR0) matching addr.
1318 */
1319 if (watchpoint->value) {
1320 LOG_DEBUG("data value watchpoint not YET supported");
1321 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1322 }
1323
1324 cortex_m3->dwt_comp_available--;
1325 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1326
1327 return ERROR_OK;
1328 }
1329
1330 static int
1331 cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1332 {
1333 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1334
1335 /* REVISIT why check? DWT can be updated with core running ... */
1336 if (target->state != TARGET_HALTED)
1337 {
1338 LOG_WARNING("target not halted");
1339 return ERROR_TARGET_NOT_HALTED;
1340 }
1341
1342 if (watchpoint->set)
1343 {
1344 cortex_m3_unset_watchpoint(target, watchpoint);
1345 }
1346
1347 cortex_m3->dwt_comp_available++;
1348 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1349
1350 return ERROR_OK;
1351 }
1352
1353 static void cortex_m3_enable_watchpoints(struct target *target)
1354 {
1355 struct watchpoint *watchpoint = target->watchpoints;
1356
1357 /* set any pending watchpoints */
1358 while (watchpoint)
1359 {
1360 if (!watchpoint->set)
1361 cortex_m3_set_watchpoint(target, watchpoint);
1362 watchpoint = watchpoint->next;
1363 }
1364 }
1365
1366 static int cortex_m3_load_core_reg_u32(struct target *target,
1367 enum armv7m_regtype type, uint32_t num, uint32_t * value)
1368 {
1369 int retval;
1370 struct armv7m_common *armv7m = target_to_armv7m(target);
1371 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1372
1373 /* NOTE: we "know" here that the register identifiers used
1374 * in the v7m header match the Cortex-M3 Debug Core Register
1375 * Selector values for R0..R15, xPSR, MSP, and PSP.
1376 */
1377 switch (num) {
1378 case 0 ... 18:
1379 /* read a normal core register */
1380 retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1381
1382 if (retval != ERROR_OK)
1383 {
1384 LOG_ERROR("JTAG failure %i",retval);
1385 return ERROR_JTAG_DEVICE_ERROR;
1386 }
1387 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value);
1388 break;
1389
1390 case ARMV7M_PRIMASK:
1391 case ARMV7M_BASEPRI:
1392 case ARMV7M_FAULTMASK:
1393 case ARMV7M_CONTROL:
1394 /* Cortex-M3 packages these four registers as bitfields
1395 * in one Debug Core register. So say r0 and r2 docs;
1396 * it was removed from r1 docs, but still works.
1397 */
1398 cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1399
1400 switch (num)
1401 {
1402 case ARMV7M_PRIMASK:
1403 *value = buf_get_u32((uint8_t*)value, 0, 1);
1404 break;
1405
1406 case ARMV7M_BASEPRI:
1407 *value = buf_get_u32((uint8_t*)value, 8, 8);
1408 break;
1409
1410 case ARMV7M_FAULTMASK:
1411 *value = buf_get_u32((uint8_t*)value, 16, 1);
1412 break;
1413
1414 case ARMV7M_CONTROL:
1415 *value = buf_get_u32((uint8_t*)value, 24, 2);
1416 break;
1417 }
1418
1419 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1420 break;
1421
1422 default:
1423 return ERROR_INVALID_ARGUMENTS;
1424 }
1425
1426 return ERROR_OK;
1427 }
1428
1429 static int cortex_m3_store_core_reg_u32(struct target *target,
1430 enum armv7m_regtype type, uint32_t num, uint32_t value)
1431 {
1432 int retval;
1433 uint32_t reg;
1434 struct armv7m_common *armv7m = target_to_armv7m(target);
1435 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1436
1437 #ifdef ARMV7_GDB_HACKS
1438 /* If the LR register is being modified, make sure it will put us
1439 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1440 * hack to deal with the fact that gdb will sometimes "forge"
1441 * return addresses, and doesn't set the LSB correctly (i.e., when
1442 * printing expressions containing function calls, it sets LR = 0.)
1443 * Valid exception return codes have bit 0 set too.
1444 */
1445 if (num == ARMV7M_R14)
1446 value |= 0x01;
1447 #endif
1448
1449 /* NOTE: we "know" here that the register identifiers used
1450 * in the v7m header match the Cortex-M3 Debug Core Register
1451 * Selector values for R0..R15, xPSR, MSP, and PSP.
1452 */
1453 switch (num) {
1454 case 0 ... 18:
1455 retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1456 if (retval != ERROR_OK)
1457 {
1458 struct reg *r;
1459
1460 LOG_ERROR("JTAG failure %i", retval);
1461 r = armv7m->core_cache->reg_list + num;
1462 r->dirty = r->valid;
1463 return ERROR_JTAG_DEVICE_ERROR;
1464 }
1465 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1466 break;
1467
1468 case ARMV7M_PRIMASK:
1469 case ARMV7M_BASEPRI:
1470 case ARMV7M_FAULTMASK:
1471 case ARMV7M_CONTROL:
1472 /* Cortex-M3 packages these four registers as bitfields
1473 * in one Debug Core register. So say r0 and r2 docs;
1474 * it was removed from r1 docs, but still works.
1475 */
1476 cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
1477
1478 switch (num)
1479 {
1480 case ARMV7M_PRIMASK:
1481 buf_set_u32((uint8_t*)&reg, 0, 1, value);
1482 break;
1483
1484 case ARMV7M_BASEPRI:
1485 buf_set_u32((uint8_t*)&reg, 8, 8, value);
1486 break;
1487
1488 case ARMV7M_FAULTMASK:
1489 buf_set_u32((uint8_t*)&reg, 16, 1, value);
1490 break;
1491
1492 case ARMV7M_CONTROL:
1493 buf_set_u32((uint8_t*)&reg, 24, 2, value);
1494 break;
1495 }
1496
1497 cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1498
1499 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1500 break;
1501
1502 default:
1503 return ERROR_INVALID_ARGUMENTS;
1504 }
1505
1506 return ERROR_OK;
1507 }
1508
1509 static int cortex_m3_read_memory(struct target *target, uint32_t address,
1510 uint32_t size, uint32_t count, uint8_t *buffer)
1511 {
1512 struct armv7m_common *armv7m = target_to_armv7m(target);
1513 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1514 int retval = ERROR_INVALID_ARGUMENTS;
1515
1516 /* cortex_m3 handles unaligned memory access */
1517 if (count && buffer) {
1518 switch (size) {
1519 case 4:
1520 retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1521 break;
1522 case 2:
1523 retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1524 break;
1525 case 1:
1526 retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1527 break;
1528 }
1529 }
1530
1531 return retval;
1532 }
1533
1534 static int cortex_m3_write_memory(struct target *target, uint32_t address,
1535 uint32_t size, uint32_t count, uint8_t *buffer)
1536 {
1537 struct armv7m_common *armv7m = target_to_armv7m(target);
1538 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1539 int retval = ERROR_INVALID_ARGUMENTS;
1540
1541 if (count && buffer) {
1542 switch (size) {
1543 case 4:
1544 retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1545 break;
1546 case 2:
1547 retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1548 break;
1549 case 1:
1550 retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1551 break;
1552 }
1553 }
1554
1555 return retval;
1556 }
1557
1558 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
1559 uint32_t count, uint8_t *buffer)
1560 {
1561 return cortex_m3_write_memory(target, address, 4, count, buffer);
1562 }
1563
1564 static int cortex_m3_init_target(struct command_context *cmd_ctx,
1565 struct target *target)
1566 {
1567 armv7m_build_reg_cache(target);
1568 return ERROR_OK;
1569 }
1570
1571 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1572 * on r/w if the core is not running, and clear on resume or reset ... or
1573 * at least, in a post_restore_context() method.
1574 */
1575
1576 struct dwt_reg_state {
1577 struct target *target;
1578 uint32_t addr;
1579 uint32_t value; /* scratch/cache */
1580 };
1581
1582 static int cortex_m3_dwt_get_reg(struct reg *reg)
1583 {
1584 struct dwt_reg_state *state = reg->arch_info;
1585
1586 return target_read_u32(state->target, state->addr, &state->value);
1587 }
1588
1589 static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
1590 {
1591 struct dwt_reg_state *state = reg->arch_info;
1592
1593 return target_write_u32(state->target, state->addr,
1594 buf_get_u32(buf, 0, reg->size));
1595 }
1596
1597 struct dwt_reg {
1598 uint32_t addr;
1599 char *name;
1600 unsigned size;
1601 };
1602
1603 static struct dwt_reg dwt_base_regs[] = {
1604 { DWT_CTRL, "dwt_ctrl", 32, },
1605 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1606 * increments while the core is asleep.
1607 */
1608 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1609 /* plus some 8 bit counters, useful for profiling with TPIU */
1610 };
1611
1612 static struct dwt_reg dwt_comp[] = {
1613 #define DWT_COMPARATOR(i) \
1614 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1615 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1616 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1617 DWT_COMPARATOR(0),
1618 DWT_COMPARATOR(1),
1619 DWT_COMPARATOR(2),
1620 DWT_COMPARATOR(3),
1621 #undef DWT_COMPARATOR
1622 };
1623
1624 static const struct reg_arch_type dwt_reg_type = {
1625 .get = cortex_m3_dwt_get_reg,
1626 .set = cortex_m3_dwt_set_reg,
1627 };
1628
1629 static void
1630 cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1631 {
1632 struct dwt_reg_state *state;
1633
1634 state = calloc(1, sizeof *state);
1635 if (!state)
1636 return;
1637 state->addr = d->addr;
1638 state->target = t;
1639
1640 r->name = d->name;
1641 r->size = d->size;
1642 r->value = &state->value;
1643 r->arch_info = state;
1644 r->type = &dwt_reg_type;
1645 }
1646
1647 static void
1648 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
1649 {
1650 uint32_t dwtcr;
1651 struct reg_cache *cache;
1652 struct cortex_m3_dwt_comparator *comparator;
1653 int reg, i;
1654
1655 target_read_u32(target, DWT_CTRL, &dwtcr);
1656 if (!dwtcr) {
1657 LOG_DEBUG("no DWT");
1658 return;
1659 }
1660
1661 cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1662 cm3->dwt_comp_available = cm3->dwt_num_comp;
1663 cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1664 sizeof(struct cortex_m3_dwt_comparator));
1665 if (!cm3->dwt_comparator_list) {
1666 fail0:
1667 cm3->dwt_num_comp = 0;
1668 LOG_ERROR("out of mem");
1669 return;
1670 }
1671
1672 cache = calloc(1, sizeof *cache);
1673 if (!cache) {
1674 fail1:
1675 free(cm3->dwt_comparator_list);
1676 goto fail0;
1677 }
1678 cache->name = "cortex-m3 dwt registers";
1679 cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1680 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1681 if (!cache->reg_list) {
1682 free(cache);
1683 goto fail1;
1684 }
1685
1686 for (reg = 0; reg < 2; reg++)
1687 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1688 dwt_base_regs + reg);
1689
1690 comparator = cm3->dwt_comparator_list;
1691 for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1692 int j;
1693
1694 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1695 for (j = 0; j < 3; j++, reg++)
1696 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1697 dwt_comp + 3 * i + j);
1698 }
1699
1700 *register_get_last_cache_p(&target->reg_cache) = cache;
1701 cm3->dwt_cache = cache;
1702
1703 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1704 dwtcr, cm3->dwt_num_comp,
1705 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1706
1707 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1708 * implement single-address data value watchpoints ... so we
1709 * won't need to check it later, when asked to set one up.
1710 */
1711 }
1712
1713 static int cortex_m3_examine(struct target *target)
1714 {
1715 int retval;
1716 uint32_t cpuid, fpcr;
1717 int i;
1718 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1719 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
1720
1721 if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
1722 return retval;
1723
1724 if (!target_was_examined(target))
1725 {
1726 target_set_examined(target);
1727
1728 /* Read from Device Identification Registers */
1729 retval = target_read_u32(target, CPUID, &cpuid);
1730 if (retval != ERROR_OK)
1731 return retval;
1732
1733 if (((cpuid >> 4) & 0xc3f) == 0xc23)
1734 LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected",
1735 (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
1736 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1737
1738 /* NOTE: FPB and DWT are both optional. */
1739
1740 /* Setup FPB */
1741 target_read_u32(target, FP_CTRL, &fpcr);
1742 cortex_m3->auto_bp_type = 1;
1743 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
1744 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1745 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1746 cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
1747 cortex_m3->fpb_enabled = fpcr & 1;
1748 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
1749 {
1750 cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1751 cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1752 }
1753 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
1754
1755 /* Setup DWT */
1756 cortex_m3_dwt_setup(cortex_m3, target);
1757
1758 /* These hardware breakpoints only work for code in flash! */
1759 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1760 target_name(target),
1761 cortex_m3->fp_num_code,
1762 cortex_m3->dwt_num_comp);
1763 }
1764
1765 return ERROR_OK;
1766 }
1767
1768 static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
1769 {
1770 uint16_t dcrdr;
1771
1772 mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1773 *ctrl = (uint8_t)dcrdr;
1774 *value = (uint8_t)(dcrdr >> 8);
1775
1776 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1777
1778 /* write ack back to software dcc register
1779 * signify we have read data */
1780 if (dcrdr & (1 << 0))
1781 {
1782 dcrdr = 0;
1783 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1784 }
1785
1786 return ERROR_OK;
1787 }
1788
1789 static int cortex_m3_target_request_data(struct target *target,
1790 uint32_t size, uint8_t *buffer)
1791 {
1792 struct armv7m_common *armv7m = target_to_armv7m(target);
1793 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1794 uint8_t data;
1795 uint8_t ctrl;
1796 uint32_t i;
1797
1798 for (i = 0; i < (size * 4); i++)
1799 {
1800 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1801 buffer[i] = data;
1802 }
1803
1804 return ERROR_OK;
1805 }
1806
1807 static int cortex_m3_handle_target_request(void *priv)
1808 {
1809 struct target *target = priv;
1810 if (!target_was_examined(target))
1811 return ERROR_OK;
1812 struct armv7m_common *armv7m = target_to_armv7m(target);
1813 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1814
1815 if (!target->dbg_msg_enabled)
1816 return ERROR_OK;
1817
1818 if (target->state == TARGET_RUNNING)
1819 {
1820 uint8_t data;
1821 uint8_t ctrl;
1822
1823 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1824
1825 /* check if we have data */
1826 if (ctrl & (1 << 0))
1827 {
1828 uint32_t request;
1829
1830 /* we assume target is quick enough */
1831 request = data;
1832 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1833 request |= (data << 8);
1834 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1835 request |= (data << 16);
1836 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1837 request |= (data << 24);
1838 target_request(target, request);
1839 }
1840 }
1841
1842 return ERROR_OK;
1843 }
1844
1845 static int cortex_m3_init_arch_info(struct target *target,
1846 struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
1847 {
1848 int retval;
1849 struct armv7m_common *armv7m = &cortex_m3->armv7m;
1850
1851 armv7m_init_arch_info(target, armv7m);
1852
1853 /* prepare JTAG information for the new target */
1854 cortex_m3->jtag_info.tap = tap;
1855 cortex_m3->jtag_info.scann_size = 4;
1856
1857 /* Leave (only) generic DAP stuff for debugport_init(); */
1858 armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
1859 armv7m->swjdp_info.memaccess_tck = 8;
1860 /* Cortex-M3 has 4096 bytes autoincrement range */
1861 armv7m->swjdp_info.tar_autoincr_block = (1 << 12);
1862
1863 /* register arch-specific functions */
1864 armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
1865
1866 armv7m->post_debug_entry = NULL;
1867
1868 armv7m->pre_restore_context = NULL;
1869 armv7m->post_restore_context = NULL;
1870
1871 armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
1872 armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
1873
1874 target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
1875
1876 if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
1877 {
1878 return retval;
1879 }
1880
1881 return ERROR_OK;
1882 }
1883
1884 static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
1885 {
1886 struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
1887
1888 cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
1889 cortex_m3_init_arch_info(target, cortex_m3, target->tap);
1890
1891 return ERROR_OK;
1892 }
1893
1894 /*--------------------------------------------------------------------------*/
1895
1896 static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
1897 struct cortex_m3_common *cm3)
1898 {
1899 if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
1900 command_print(cmd_ctx, "target is not a Cortex-M3");
1901 return ERROR_TARGET_INVALID;
1902 }
1903 return ERROR_OK;
1904 }
1905
1906 /*
1907 * Only stuff below this line should need to verify that its target
1908 * is a Cortex-M3. Everything else should have indirected through the
1909 * cortexm3_target structure, which is only used with CM3 targets.
1910 */
1911
1912 static const struct {
1913 char name[10];
1914 unsigned mask;
1915 } vec_ids[] = {
1916 { "hard_err", VC_HARDERR, },
1917 { "int_err", VC_INTERR, },
1918 { "bus_err", VC_BUSERR, },
1919 { "state_err", VC_STATERR, },
1920 { "chk_err", VC_CHKERR, },
1921 { "nocp_err", VC_NOCPERR, },
1922 { "mm_err", VC_MMERR, },
1923 { "reset", VC_CORERESET, },
1924 };
1925
1926 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
1927 {
1928 struct target *target = get_current_target(CMD_CTX);
1929 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1930 struct armv7m_common *armv7m = &cortex_m3->armv7m;
1931 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1932 uint32_t demcr = 0;
1933 int retval;
1934
1935 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1936 if (retval != ERROR_OK)
1937 return retval;
1938
1939 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1940
1941 if (CMD_ARGC > 0) {
1942 unsigned catch = 0;
1943
1944 if (CMD_ARGC == 1) {
1945 if (strcmp(CMD_ARGV[0], "all") == 0) {
1946 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
1947 | VC_STATERR | VC_CHKERR | VC_NOCPERR
1948 | VC_MMERR | VC_CORERESET;
1949 goto write;
1950 } else if (strcmp(CMD_ARGV[0], "none") == 0) {
1951 goto write;
1952 }
1953 }
1954 while (CMD_ARGC-- > 0) {
1955 unsigned i;
1956 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
1957 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
1958 continue;
1959 catch |= vec_ids[i].mask;
1960 break;
1961 }
1962 if (i == ARRAY_SIZE(vec_ids)) {
1963 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
1964 return ERROR_INVALID_ARGUMENTS;
1965 }
1966 }
1967 write:
1968 /* For now, armv7m->demcr only stores vector catch flags. */
1969 armv7m->demcr = catch;
1970
1971 demcr &= ~0xffff;
1972 demcr |= catch;
1973
1974 /* write, but don't assume it stuck (why not??) */
1975 mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
1976 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1977
1978 /* FIXME be sure to clear DEMCR on clean server shutdown.
1979 * Otherwise the vector catch hardware could fire when there's
1980 * no debugger hooked up, causing much confusion...
1981 */
1982 }
1983
1984 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
1985 {
1986 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
1987 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
1988 }
1989
1990 return ERROR_OK;
1991 }
1992
1993 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
1994 {
1995 struct target *target = get_current_target(CMD_CTX);
1996 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1997 int retval;
1998
1999 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2000 if (retval != ERROR_OK)
2001 return retval;
2002
2003 if (target->state != TARGET_HALTED)
2004 {
2005 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2006 return ERROR_OK;
2007 }
2008
2009 if (CMD_ARGC > 0)
2010 {
2011 bool enable;
2012 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
2013 uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0);
2014 uint32_t mask_off = enable ? 0 : C_MASKINTS;
2015 cortex_m3_write_debug_halt_mask(target, mask_on, mask_off);
2016 }
2017
2018 command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
2019 (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
2020
2021 return ERROR_OK;
2022 }
2023
2024 static const struct command_registration cortex_m3_exec_command_handlers[] = {
2025 {
2026 .name = "maskisr",
2027 .handler = handle_cortex_m3_mask_interrupts_command,
2028 .mode = COMMAND_EXEC,
2029 .help = "mask cortex_m3 interrupts",
2030 .usage = "['on'|'off']",
2031 },
2032 {
2033 .name = "vector_catch",
2034 .handler = handle_cortex_m3_vector_catch_command,
2035 .mode = COMMAND_EXEC,
2036 .help = "configure hardware vectors to trigger debug entry",
2037 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2038 },
2039 COMMAND_REGISTRATION_DONE
2040 };
2041 static const struct command_registration cortex_m3_command_handlers[] = {
2042 {
2043 .chain = armv7m_command_handlers,
2044 },
2045 {
2046 .name = "cortex_m3",
2047 .mode = COMMAND_EXEC,
2048 .help = "Cortex-M3 command group",
2049 .chain = cortex_m3_exec_command_handlers,
2050 },
2051 COMMAND_REGISTRATION_DONE
2052 };
2053
2054 struct target_type cortexm3_target =
2055 {
2056 .name = "cortex_m3",
2057
2058 .poll = cortex_m3_poll,
2059 .arch_state = armv7m_arch_state,
2060
2061 .target_request_data = cortex_m3_target_request_data,
2062
2063 .halt = cortex_m3_halt,
2064 .resume = cortex_m3_resume,
2065 .step = cortex_m3_step,
2066
2067 .assert_reset = cortex_m3_assert_reset,
2068 .deassert_reset = cortex_m3_deassert_reset,
2069 .soft_reset_halt = cortex_m3_soft_reset_halt,
2070
2071 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2072
2073 .read_memory = cortex_m3_read_memory,
2074 .write_memory = cortex_m3_write_memory,
2075 .bulk_write_memory = cortex_m3_bulk_write_memory,
2076 .checksum_memory = armv7m_checksum_memory,
2077 .blank_check_memory = armv7m_blank_check_memory,
2078
2079 .run_algorithm = armv7m_run_algorithm,
2080
2081 .add_breakpoint = cortex_m3_add_breakpoint,
2082 .remove_breakpoint = cortex_m3_remove_breakpoint,
2083 .add_watchpoint = cortex_m3_add_watchpoint,
2084 .remove_watchpoint = cortex_m3_remove_watchpoint,
2085
2086 .commands = cortex_m3_command_handlers,
2087 .target_create = cortex_m3_target_create,
2088 .init_target = cortex_m3_init_target,
2089 .examine = cortex_m3_examine,
2090 };
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