src/target/cortex_m.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2005 by Dominic Rath                                    *
   5  *   Dominic.Rath@gmx.de                                                   *
   6  *                                                                         *
   7  *   Copyright (C) 2006 by Magnus Lundin                                   *
   8  *   lundin@mlu.mine.nu                                                    *
   9  *                                                                         *
  10  *   Copyright (C) 2008 by Spencer Oliver                                  *
  11  *   spen@spen-soft.co.uk                                                  *
  12  ***************************************************************************/
  13
  14 #ifndef OPENOCD_TARGET_CORTEX_M_H
  15 #define OPENOCD_TARGET_CORTEX_M_H
  16
  17 #include "armv7m.h"
  18 #include "helper/bits.h"
  19
  20 #define CORTEX_M_COMMON_MAGIC 0x1A451A45U
  21
  22 #define SYSTEM_CONTROL_BASE 0x400FE000
  23
  24 #define ITM_TER0        0xE0000E00
  25 #define ITM_TPR         0xE0000E40
  26 #define ITM_TCR         0xE0000E80
  27 #define ITM_TCR_ITMENA_BIT      BIT(0)
  28 #define ITM_TCR_BUSY_BIT        BIT(23)
  29 #define ITM_LAR         0xE0000FB0
  30 #define ITM_LAR_KEY     0xC5ACCE55
  31
  32 #define CPUID           0xE000ED00
  33
  34 #define ARM_CPUID_IMPLEMENTOR_POS       24
  35 #define ARM_CPUID_IMPLEMENTOR_MASK      (0xFF << ARM_CPUID_IMPLEMENTOR_POS)
  36 #define ARM_CPUID_PARTNO_POS            4
  37 #define ARM_CPUID_PARTNO_MASK           (0xFFF << ARM_CPUID_PARTNO_POS)
  38
  39 #define ARM_MAKE_CPUID(impl, partno)    ((((impl) << ARM_CPUID_IMPLEMENTOR_POS) & ARM_CPUID_IMPLEMENTOR_MASK) | \
  40         (((partno) << ARM_CPUID_PARTNO_POS)  & ARM_CPUID_PARTNO_MASK))
  41
  42 /** Known Arm Cortex masked CPU Ids
  43  * This includes the implementor and part number, but _not_ the revision or
  44  * patch fields.
  45  */
  46 enum cortex_m_impl_part {
  47         CORTEX_M_PARTNO_INVALID,
  48         STAR_MC1_PARTNO    = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0x132), /* FIXME - confirm implementor! */
  49         CORTEX_M0_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC20),
  50         CORTEX_M1_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC21),
  51         CORTEX_M3_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC23),
  52         CORTEX_M4_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC24),
  53         CORTEX_M7_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC27),
  54         CORTEX_M0P_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC60),
  55         CORTEX_M23_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD20),
  56         CORTEX_M33_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD21),
  57         CORTEX_M35P_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD31),
  58         CORTEX_M55_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD22),
  59 };
  60
  61 /* Relevant Cortex-M flags, used in struct cortex_m_part_info.flags */
  62 #define CORTEX_M_F_HAS_FPV4               BIT(0)
  63 #define CORTEX_M_F_HAS_FPV5               BIT(1)
  64 #define CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K  BIT(2)
  65
  66 struct cortex_m_part_info {
  67         enum cortex_m_impl_part impl_part;
  68         const char *name;
  69         enum arm_arch arch;
  70         uint32_t flags;
  71 };
  72
  73 /* Debug Control Block */
  74 #define DCB_DHCSR       0xE000EDF0
  75 #define DCB_DCRSR       0xE000EDF4
  76 #define DCB_DCRDR       0xE000EDF8
  77 #define DCB_DEMCR       0xE000EDFC
  78 #define DCB_DSCSR       0xE000EE08
  79
  80 #define DAUTHSTATUS     0xE000EFB8
  81 #define DAUTHSTATUS_SID_MASK    0x00000030
  82
  83 #define DCRSR_WNR       BIT(16)
  84
  85 #define DWT_CTRL        0xE0001000
  86 #define DWT_CYCCNT      0xE0001004
  87 #define DWT_PCSR        0xE000101C
  88 #define DWT_COMP0       0xE0001020
  89 #define DWT_MASK0       0xE0001024
  90 #define DWT_FUNCTION0   0xE0001028
  91 #define DWT_DEVARCH             0xE0001FBC
  92
  93 #define DWT_DEVARCH_ARMV8M      0x101A02
  94
  95 #define FP_CTRL         0xE0002000
  96 #define FP_REMAP        0xE0002004
  97 #define FP_COMP0        0xE0002008
  98 #define FP_COMP1        0xE000200C
  99 #define FP_COMP2        0xE0002010
 100 #define FP_COMP3        0xE0002014
 101 #define FP_COMP4        0xE0002018
 102 #define FP_COMP5        0xE000201C
 103 #define FP_COMP6        0xE0002020
 104 #define FP_COMP7        0xE0002024
 105
 106 #define FPU_CPACR       0xE000ED88
 107 #define FPU_FPCCR       0xE000EF34
 108 #define FPU_FPCAR       0xE000EF38
 109 #define FPU_FPDSCR      0xE000EF3C
 110
 111 #define TPIU_SSPSR      0xE0040000
 112 #define TPIU_CSPSR      0xE0040004
 113 #define TPIU_ACPR       0xE0040010
 114 #define TPIU_SPPR       0xE00400F0
 115 #define TPIU_FFSR       0xE0040300
 116 #define TPIU_FFCR       0xE0040304
 117 #define TPIU_FSCR       0xE0040308
 118
 119 /* Maximum SWO prescaler value. */
 120 #define TPIU_ACPR_MAX_SWOSCALER 0x1fff
 121
 122 /* DCB_DHCSR bit and field definitions */
 123 #define DBGKEY          (0xA05Ful << 16)
 124 #define C_DEBUGEN       BIT(0)
 125 #define C_HALT          BIT(1)
 126 #define C_STEP          BIT(2)
 127 #define C_MASKINTS      BIT(3)
 128 #define S_REGRDY        BIT(16)
 129 #define S_HALT          BIT(17)
 130 #define S_SLEEP         BIT(18)
 131 #define S_LOCKUP        BIT(19)
 132 #define S_RETIRE_ST     BIT(24)
 133 #define S_RESET_ST      BIT(25)
 134
 135 /* DCB_DEMCR bit and field definitions */
 136 #define TRCENA                  BIT(24)
 137 #define VC_HARDERR              BIT(10)
 138 #define VC_INTERR               BIT(9)
 139 #define VC_BUSERR               BIT(8)
 140 #define VC_STATERR              BIT(7)
 141 #define VC_CHKERR               BIT(6)
 142 #define VC_NOCPERR              BIT(5)
 143 #define VC_MMERR                BIT(4)
 144 #define VC_CORERESET    BIT(0)
 145
 146 /* DCB_DSCSR bit and field definitions */
 147 #define DSCSR_CDS               BIT(16)
 148
 149 /* NVIC registers */
 150 #define NVIC_ICTR               0xE000E004
 151 #define NVIC_ISE0               0xE000E100
 152 #define NVIC_ICSR               0xE000ED04
 153 #define NVIC_AIRCR              0xE000ED0C
 154 #define NVIC_SHCSR              0xE000ED24
 155 #define NVIC_CFSR               0xE000ED28
 156 #define NVIC_MMFSRB             0xE000ED28
 157 #define NVIC_BFSRB              0xE000ED29
 158 #define NVIC_USFSRH             0xE000ED2A
 159 #define NVIC_HFSR               0xE000ED2C
 160 #define NVIC_DFSR               0xE000ED30
 161 #define NVIC_MMFAR              0xE000ED34
 162 #define NVIC_BFAR               0xE000ED38
 163 #define NVIC_SFSR               0xE000EDE4
 164 #define NVIC_SFAR               0xE000EDE8
 165
 166 /* NVIC_AIRCR bits */
 167 #define AIRCR_VECTKEY           (0x5FAul << 16)
 168 #define AIRCR_SYSRESETREQ       BIT(2)
 169 #define AIRCR_VECTCLRACTIVE     BIT(1)
 170 #define AIRCR_VECTRESET         BIT(0)
 171 /* NVIC_SHCSR bits */
 172 #define SHCSR_BUSFAULTENA       BIT(17)
 173 /* NVIC_DFSR bits */
 174 #define DFSR_HALTED                     1
 175 #define DFSR_BKPT                       2
 176 #define DFSR_DWTTRAP            4
 177 #define DFSR_VCATCH                     8
 178 #define DFSR_EXTERNAL           16
 179
 180 #define FPCR_CODE 0
 181 #define FPCR_LITERAL 1
 182 #define FPCR_REPLACE_REMAP  (0ul << 30)
 183 #define FPCR_REPLACE_BKPT_LOW  (1ul << 30)
 184 #define FPCR_REPLACE_BKPT_HIGH  (2ul << 30)
 185 #define FPCR_REPLACE_BKPT_BOTH  (3ul << 30)
 186
 187 struct cortex_m_fp_comparator {
 188         bool used;
 189         int type;
 190         uint32_t fpcr_value;
 191         uint32_t fpcr_address;
 192 };
 193
 194 struct cortex_m_dwt_comparator {
 195         bool used;
 196         uint32_t comp;
 197         uint32_t mask;
 198         uint32_t function;
 199         uint32_t dwt_comparator_address;
 200 };
 201
 202 enum cortex_m_soft_reset_config {
 203         CORTEX_M_RESET_SYSRESETREQ,
 204         CORTEX_M_RESET_VECTRESET,
 205 };
 206
 207 enum cortex_m_isrmasking_mode {
 208         CORTEX_M_ISRMASK_AUTO,
 209         CORTEX_M_ISRMASK_OFF,
 210         CORTEX_M_ISRMASK_ON,
 211         CORTEX_M_ISRMASK_STEPONLY,
 212 };
 213
 214 struct cortex_m_common {
 215         unsigned int common_magic;
 216
 217         struct armv7m_common armv7m;
 218
 219         /* Context information */
 220         uint32_t dcb_dhcsr;
 221         uint32_t dcb_dhcsr_cumulated_sticky;
 222         /* DCB DHCSR has been at least once read, so the sticky bits have been reset */
 223         bool dcb_dhcsr_sticky_is_recent;
 224         uint32_t nvic_dfsr;  /* Debug Fault Status Register - shows reason for debug halt */
 225         uint32_t nvic_icsr;  /* Interrupt Control State Register - shows active and pending IRQ */
 226
 227         /* Flash Patch and Breakpoint (FPB) */
 228         unsigned int fp_num_lit;
 229         unsigned int fp_num_code;
 230         int fp_rev;
 231         bool fpb_enabled;
 232         struct cortex_m_fp_comparator *fp_comparator_list;
 233
 234         /* Data Watchpoint and Trace (DWT) */
 235         unsigned int dwt_num_comp;
 236         unsigned int dwt_comp_available;
 237         uint32_t dwt_devarch;
 238         struct cortex_m_dwt_comparator *dwt_comparator_list;
 239         struct reg_cache *dwt_cache;
 240
 241         enum cortex_m_soft_reset_config soft_reset_config;
 242         bool vectreset_supported;
 243         enum cortex_m_isrmasking_mode isrmasking_mode;
 244
 245         const struct cortex_m_part_info *core_info;
 246
 247         bool slow_register_read;        /* A register has not been ready, poll S_REGRDY */
 248
 249         uint64_t apsel;
 250
 251         /* Whether this target has the erratum that makes C_MASKINTS not apply to
 252          * already pending interrupts */
 253         bool maskints_erratum;
 254 };
 255
 256 static inline bool is_cortex_m_or_hla(const struct cortex_m_common *cortex_m)
 257 {
 258         return cortex_m->common_magic == CORTEX_M_COMMON_MAGIC;
 259 }
 260
 261 static inline bool is_cortex_m_with_dap_access(const struct cortex_m_common *cortex_m)
 262 {
 263         if (!is_cortex_m_or_hla(cortex_m))
 264                 return false;
 265
 266         return !cortex_m->armv7m.is_hla_target;
 267 }
 268
 269 /**
 270  * @returns the pointer to the target specific struct
 271  * without matching a magic number.
 272  * Use in target specific service routines, where the correct
 273  * type of arch_info is certain.
 274  */
 275 static inline struct cortex_m_common *
 276 target_to_cm(struct target *target)
 277 {
 278         return container_of(target->arch_info,
 279                         struct cortex_m_common, armv7m.arm);
 280 }
 281
 282 /**
 283  * @returns the pointer to the target specific struct
 284  * or NULL if the magic number does not match.
 285  * Use in a flash driver or any place where mismatch of the arch_info
 286  * type can happen.
 287  */
 288 static inline struct cortex_m_common *
 289 target_to_cortex_m_safe(struct target *target)
 290 {
 291         /* Check the parent types first to prevent peeking memory too far
 292          * from arch_info pointer */
 293         if (!target_to_armv7m_safe(target))
 294                 return NULL;
 295
 296         struct cortex_m_common *cortex_m = target_to_cm(target);
 297         if (!is_cortex_m_or_hla(cortex_m))
 298                 return NULL;
 299
 300         return cortex_m;
 301 }
 302
 303 /**
 304  * @returns cached value of the cpuid, masked for implementation and part.
 305  * or CORTEX_M_PARTNO_INVALID if the magic number does not match
 306  * or core_info is not initialised.
 307  */
 308 static inline enum cortex_m_impl_part cortex_m_get_impl_part(struct target *target)
 309 {
 310         struct cortex_m_common *cortex_m = target_to_cortex_m_safe(target);
 311         if (!cortex_m)
 312                 return CORTEX_M_PARTNO_INVALID;
 313
 314         if (!cortex_m->core_info)
 315                 return CORTEX_M_PARTNO_INVALID;
 316
 317         return cortex_m->core_info->impl_part;
 318 }
 319
 320 int cortex_m_examine(struct target *target);
 321 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
 322 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
 323 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
 324 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
 325 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
 326 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
 327 void cortex_m_enable_breakpoints(struct target *target);
 328 void cortex_m_enable_watchpoints(struct target *target);
 329 void cortex_m_deinit_target(struct target *target);
 330 int cortex_m_profiling(struct target *target, uint32_t *samples,
 331         uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
 332
 333 #endif /* OPENOCD_TARGET_CORTEX_M_H */