target/cortex_m: allow setting the type of a breakpoint
[openocd.git] / src / target / cortex_m.h
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifndef OPENOCD_TARGET_CORTEX_M_H
26 #define OPENOCD_TARGET_CORTEX_M_H
27
28 #include "armv7m.h"
29
30 #define CORTEX_M_COMMON_MAGIC 0x1A451A45
31
32 #define SYSTEM_CONTROL_BASE 0x400FE000
33
34 #define ITM_TER0 0xE0000E00
35 #define ITM_TPR 0xE0000E40
36 #define ITM_TCR 0xE0000E80
37 #define ITM_LAR 0xE0000FB0
38 #define ITM_LAR_KEY 0xC5ACCE55
39
40 #define CPUID 0xE000ED00
41 /* Debug Control Block */
42 #define DCB_DHCSR 0xE000EDF0
43 #define DCB_DCRSR 0xE000EDF4
44 #define DCB_DCRDR 0xE000EDF8
45 #define DCB_DEMCR 0xE000EDFC
46
47 #define DCRSR_WnR (1 << 16)
48
49 #define DWT_CTRL 0xE0001000
50 #define DWT_CYCCNT 0xE0001004
51 #define DWT_PCSR 0xE000101C
52 #define DWT_COMP0 0xE0001020
53 #define DWT_MASK0 0xE0001024
54 #define DWT_FUNCTION0 0xE0001028
55
56 #define FP_CTRL 0xE0002000
57 #define FP_REMAP 0xE0002004
58 #define FP_COMP0 0xE0002008
59 #define FP_COMP1 0xE000200C
60 #define FP_COMP2 0xE0002010
61 #define FP_COMP3 0xE0002014
62 #define FP_COMP4 0xE0002018
63 #define FP_COMP5 0xE000201C
64 #define FP_COMP6 0xE0002020
65 #define FP_COMP7 0xE0002024
66
67 #define FPU_CPACR 0xE000ED88
68 #define FPU_FPCCR 0xE000EF34
69 #define FPU_FPCAR 0xE000EF38
70 #define FPU_FPDSCR 0xE000EF3C
71
72 #define TPIU_SSPSR 0xE0040000
73 #define TPIU_CSPSR 0xE0040004
74 #define TPIU_ACPR 0xE0040010
75 #define TPIU_SPPR 0xE00400F0
76 #define TPIU_FFSR 0xE0040300
77 #define TPIU_FFCR 0xE0040304
78 #define TPIU_FSCR 0xE0040308
79
80 /* DCB_DHCSR bit and field definitions */
81 #define DBGKEY (0xA05F << 16)
82 #define C_DEBUGEN (1 << 0)
83 #define C_HALT (1 << 1)
84 #define C_STEP (1 << 2)
85 #define C_MASKINTS (1 << 3)
86 #define S_REGRDY (1 << 16)
87 #define S_HALT (1 << 17)
88 #define S_SLEEP (1 << 18)
89 #define S_LOCKUP (1 << 19)
90 #define S_RETIRE_ST (1 << 24)
91 #define S_RESET_ST (1 << 25)
92
93 /* DCB_DEMCR bit and field definitions */
94 #define TRCENA (1 << 24)
95 #define VC_HARDERR (1 << 10)
96 #define VC_INTERR (1 << 9)
97 #define VC_BUSERR (1 << 8)
98 #define VC_STATERR (1 << 7)
99 #define VC_CHKERR (1 << 6)
100 #define VC_NOCPERR (1 << 5)
101 #define VC_MMERR (1 << 4)
102 #define VC_CORERESET (1 << 0)
103
104 #define NVIC_ICTR 0xE000E004
105 #define NVIC_ISE0 0xE000E100
106 #define NVIC_ICSR 0xE000ED04
107 #define NVIC_AIRCR 0xE000ED0C
108 #define NVIC_SHCSR 0xE000ED24
109 #define NVIC_CFSR 0xE000ED28
110 #define NVIC_MMFSRb 0xE000ED28
111 #define NVIC_BFSRb 0xE000ED29
112 #define NVIC_USFSRh 0xE000ED2A
113 #define NVIC_HFSR 0xE000ED2C
114 #define NVIC_DFSR 0xE000ED30
115 #define NVIC_MMFAR 0xE000ED34
116 #define NVIC_BFAR 0xE000ED38
117
118 /* NVIC_AIRCR bits */
119 #define AIRCR_VECTKEY (0x5FA << 16)
120 #define AIRCR_SYSRESETREQ (1 << 2)
121 #define AIRCR_VECTCLRACTIVE (1 << 1)
122 #define AIRCR_VECTRESET (1 << 0)
123 /* NVIC_SHCSR bits */
124 #define SHCSR_BUSFAULTENA (1 << 17)
125 /* NVIC_DFSR bits */
126 #define DFSR_HALTED 1
127 #define DFSR_BKPT 2
128 #define DFSR_DWTTRAP 4
129 #define DFSR_VCATCH 8
130
131 #define FPCR_CODE 0
132 #define FPCR_LITERAL 1
133 #define FPCR_REPLACE_REMAP (0 << 30)
134 #define FPCR_REPLACE_BKPT_LOW (1 << 30)
135 #define FPCR_REPLACE_BKPT_HIGH (2 << 30)
136 #define FPCR_REPLACE_BKPT_BOTH (3 << 30)
137
138 struct cortex_m_fp_comparator {
139 int used;
140 int type;
141 uint32_t fpcr_value;
142 uint32_t fpcr_address;
143 };
144
145 struct cortex_m_dwt_comparator {
146 int used;
147 uint32_t comp;
148 uint32_t mask;
149 uint32_t function;
150 uint32_t dwt_comparator_address;
151 };
152
153 enum cortex_m_soft_reset_config {
154 CORTEX_M_RESET_SYSRESETREQ,
155 CORTEX_M_RESET_VECTRESET,
156 };
157
158 enum cortex_m_isrmasking_mode {
159 CORTEX_M_ISRMASK_AUTO,
160 CORTEX_M_ISRMASK_OFF,
161 CORTEX_M_ISRMASK_ON,
162 };
163
164 struct cortex_m_common {
165 int common_magic;
166
167 /* Context information */
168 uint32_t dcb_dhcsr;
169 uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
170 uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
171
172 /* Flash Patch and Breakpoint (FPB) */
173 int fp_num_lit;
174 int fp_num_code;
175 int fp_code_available;
176 int fp_rev;
177 int fpb_enabled;
178 struct cortex_m_fp_comparator *fp_comparator_list;
179
180 /* Data Watchpoint and Trace (DWT) */
181 int dwt_num_comp;
182 int dwt_comp_available;
183 struct cortex_m_dwt_comparator *dwt_comparator_list;
184 struct reg_cache *dwt_cache;
185
186 enum cortex_m_soft_reset_config soft_reset_config;
187
188 enum cortex_m_isrmasking_mode isrmasking_mode;
189
190 struct armv7m_common armv7m;
191
192 int apsel;
193 };
194
195 static inline struct cortex_m_common *
196 target_to_cm(struct target *target)
197 {
198 return container_of(target->arch_info,
199 struct cortex_m_common, armv7m);
200 }
201
202 int cortex_m_examine(struct target *target);
203 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
204 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
205 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
206 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
207 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint);
208 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint);
209 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
210 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
211 void cortex_m_enable_breakpoints(struct target *target);
212 void cortex_m_enable_watchpoints(struct target *target);
213 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target);
214 void cortex_m_deinit_target(struct target *target);
215 int cortex_m_profiling(struct target *target, uint32_t *samples,
216 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
217
218 #endif /* OPENOCD_TARGET_CORTEX_M_H */