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target/cortex_m: Change sleep to running state
[openocd.git] / src / target / cortex_m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 * *
24 * *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
26 * *
27 ***************************************************************************/
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
34 #include "cortex_m.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
38 #include "register.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
42
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FPB remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
48 *
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
51 * any longer.
52 */
53
54 /* forward declarations */
55 static int cortex_m_store_core_reg_u32(struct target *target,
56 uint32_t num, uint32_t value);
57 static void cortex_m_dwt_free(struct target *target);
58
59 static int cortexm_dap_read_coreregister_u32(struct target *target,
60 uint32_t *value, int regnum)
61 {
62 struct armv7m_common *armv7m = target_to_armv7m(target);
63 int retval;
64 uint32_t dcrdr;
65
66 /* because the DCB_DCRDR is used for the emulated dcc channel
67 * we have to save/restore the DCB_DCRDR when used */
68 if (target->dbg_msg_enabled) {
69 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
70 if (retval != ERROR_OK)
71 return retval;
72 }
73
74 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
75 if (retval != ERROR_OK)
76 return retval;
77
78 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
79 if (retval != ERROR_OK)
80 return retval;
81
82 if (target->dbg_msg_enabled) {
83 /* restore DCB_DCRDR - this needs to be in a separate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval == ERROR_OK)
86 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
87 }
88
89 return retval;
90 }
91
92 static int cortexm_dap_write_coreregister_u32(struct target *target,
93 uint32_t value, int regnum)
94 {
95 struct armv7m_common *armv7m = target_to_armv7m(target);
96 int retval;
97 uint32_t dcrdr;
98
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
101 if (target->dbg_msg_enabled) {
102 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
103 if (retval != ERROR_OK)
104 return retval;
105 }
106
107 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
108 if (retval != ERROR_OK)
109 return retval;
110
111 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
112 if (retval != ERROR_OK)
113 return retval;
114
115 if (target->dbg_msg_enabled) {
116 /* restore DCB_DCRDR - this needs to be in a separate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval == ERROR_OK)
119 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
120 }
121
122 return retval;
123 }
124
125 static int cortex_m_write_debug_halt_mask(struct target *target,
126 uint32_t mask_on, uint32_t mask_off)
127 {
128 struct cortex_m_common *cortex_m = target_to_cm(target);
129 struct armv7m_common *armv7m = &cortex_m->armv7m;
130
131 /* mask off status bits */
132 cortex_m->dcb_dhcsr &= ~((0xFFFFul << 16) | mask_off);
133 /* create new register mask */
134 cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
135
136 return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
137 }
138
139 static int cortex_m_set_maskints(struct target *target, bool mask)
140 {
141 struct cortex_m_common *cortex_m = target_to_cm(target);
142 if (!!(cortex_m->dcb_dhcsr & C_MASKINTS) != mask)
143 return cortex_m_write_debug_halt_mask(target, mask ? C_MASKINTS : 0, mask ? 0 : C_MASKINTS);
144 else
145 return ERROR_OK;
146 }
147
148 static int cortex_m_set_maskints_for_halt(struct target *target)
149 {
150 struct cortex_m_common *cortex_m = target_to_cm(target);
151 switch (cortex_m->isrmasking_mode) {
152 case CORTEX_M_ISRMASK_AUTO:
153 /* interrupts taken at resume, whether for step or run -> no mask */
154 return cortex_m_set_maskints(target, false);
155
156 case CORTEX_M_ISRMASK_OFF:
157 /* interrupts never masked */
158 return cortex_m_set_maskints(target, false);
159
160 case CORTEX_M_ISRMASK_ON:
161 /* interrupts always masked */
162 return cortex_m_set_maskints(target, true);
163
164 case CORTEX_M_ISRMASK_STEPONLY:
165 /* interrupts masked for single step only -> mask now if MASKINTS
166 * erratum, otherwise only mask before stepping */
167 return cortex_m_set_maskints(target, cortex_m->maskints_erratum);
168 }
169 return ERROR_OK;
170 }
171
172 static int cortex_m_set_maskints_for_run(struct target *target)
173 {
174 switch (target_to_cm(target)->isrmasking_mode) {
175 case CORTEX_M_ISRMASK_AUTO:
176 /* interrupts taken at resume, whether for step or run -> no mask */
177 return cortex_m_set_maskints(target, false);
178
179 case CORTEX_M_ISRMASK_OFF:
180 /* interrupts never masked */
181 return cortex_m_set_maskints(target, false);
182
183 case CORTEX_M_ISRMASK_ON:
184 /* interrupts always masked */
185 return cortex_m_set_maskints(target, true);
186
187 case CORTEX_M_ISRMASK_STEPONLY:
188 /* interrupts masked for single step only -> no mask */
189 return cortex_m_set_maskints(target, false);
190 }
191 return ERROR_OK;
192 }
193
194 static int cortex_m_set_maskints_for_step(struct target *target)
195 {
196 switch (target_to_cm(target)->isrmasking_mode) {
197 case CORTEX_M_ISRMASK_AUTO:
198 /* the auto-interrupt should already be done -> mask */
199 return cortex_m_set_maskints(target, true);
200
201 case CORTEX_M_ISRMASK_OFF:
202 /* interrupts never masked */
203 return cortex_m_set_maskints(target, false);
204
205 case CORTEX_M_ISRMASK_ON:
206 /* interrupts always masked */
207 return cortex_m_set_maskints(target, true);
208
209 case CORTEX_M_ISRMASK_STEPONLY:
210 /* interrupts masked for single step only -> mask */
211 return cortex_m_set_maskints(target, true);
212 }
213 return ERROR_OK;
214 }
215
216 static int cortex_m_clear_halt(struct target *target)
217 {
218 struct cortex_m_common *cortex_m = target_to_cm(target);
219 struct armv7m_common *armv7m = &cortex_m->armv7m;
220 int retval;
221
222 /* clear step if any */
223 cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
224
225 /* Read Debug Fault Status Register */
226 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
227 if (retval != ERROR_OK)
228 return retval;
229
230 /* Clear Debug Fault Status */
231 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
232 if (retval != ERROR_OK)
233 return retval;
234 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
235
236 return ERROR_OK;
237 }
238
239 static int cortex_m_single_step_core(struct target *target)
240 {
241 struct cortex_m_common *cortex_m = target_to_cm(target);
242 struct armv7m_common *armv7m = &cortex_m->armv7m;
243 int retval;
244
245 /* Mask interrupts before clearing halt, if not done already. This avoids
246 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
247 * HALT can put the core into an unknown state.
248 */
249 if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
250 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
251 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
252 if (retval != ERROR_OK)
253 return retval;
254 }
255 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
256 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
257 if (retval != ERROR_OK)
258 return retval;
259 LOG_DEBUG(" ");
260
261 /* restore dhcsr reg */
262 cortex_m_clear_halt(target);
263
264 return ERROR_OK;
265 }
266
267 static int cortex_m_enable_fpb(struct target *target)
268 {
269 int retval = target_write_u32(target, FP_CTRL, 3);
270 if (retval != ERROR_OK)
271 return retval;
272
273 /* check the fpb is actually enabled */
274 uint32_t fpctrl;
275 retval = target_read_u32(target, FP_CTRL, &fpctrl);
276 if (retval != ERROR_OK)
277 return retval;
278
279 if (fpctrl & 1)
280 return ERROR_OK;
281
282 return ERROR_FAIL;
283 }
284
285 static int cortex_m_endreset_event(struct target *target)
286 {
287 int i;
288 int retval;
289 uint32_t dcb_demcr;
290 struct cortex_m_common *cortex_m = target_to_cm(target);
291 struct armv7m_common *armv7m = &cortex_m->armv7m;
292 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
293 struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
294 struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
295
296 /* REVISIT The four debug monitor bits are currently ignored... */
297 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
298 if (retval != ERROR_OK)
299 return retval;
300 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
301
302 /* this register is used for emulated dcc channel */
303 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
304 if (retval != ERROR_OK)
305 return retval;
306
307 /* Enable debug requests */
308 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
309 if (retval != ERROR_OK)
310 return retval;
311 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
312 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
313 if (retval != ERROR_OK)
314 return retval;
315 }
316
317 /* Restore proper interrupt masking setting for running CPU. */
318 cortex_m_set_maskints_for_run(target);
319
320 /* Enable features controlled by ITM and DWT blocks, and catch only
321 * the vectors we were told to pay attention to.
322 *
323 * Target firmware is responsible for all fault handling policy
324 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
325 * or manual updates to the NVIC SHCSR and CCR registers.
326 */
327 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
328 if (retval != ERROR_OK)
329 return retval;
330
331 /* Paranoia: evidently some (early?) chips don't preserve all the
332 * debug state (including FPB, DWT, etc) across reset...
333 */
334
335 /* Enable FPB */
336 retval = cortex_m_enable_fpb(target);
337 if (retval != ERROR_OK) {
338 LOG_ERROR("Failed to enable the FPB");
339 return retval;
340 }
341
342 cortex_m->fpb_enabled = true;
343
344 /* Restore FPB registers */
345 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
346 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
347 if (retval != ERROR_OK)
348 return retval;
349 }
350
351 /* Restore DWT registers */
352 for (i = 0; i < cortex_m->dwt_num_comp; i++) {
353 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
354 dwt_list[i].comp);
355 if (retval != ERROR_OK)
356 return retval;
357 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
358 dwt_list[i].mask);
359 if (retval != ERROR_OK)
360 return retval;
361 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
362 dwt_list[i].function);
363 if (retval != ERROR_OK)
364 return retval;
365 }
366 retval = dap_run(swjdp);
367 if (retval != ERROR_OK)
368 return retval;
369
370 register_cache_invalidate(armv7m->arm.core_cache);
371
372 /* make sure we have latest dhcsr flags */
373 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
374
375 return retval;
376 }
377
378 static int cortex_m_examine_debug_reason(struct target *target)
379 {
380 struct cortex_m_common *cortex_m = target_to_cm(target);
381
382 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
383 * only check the debug reason if we don't know it already */
384
385 if ((target->debug_reason != DBG_REASON_DBGRQ)
386 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
387 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
388 target->debug_reason = DBG_REASON_BREAKPOINT;
389 if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
390 target->debug_reason = DBG_REASON_WPTANDBKPT;
391 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
392 target->debug_reason = DBG_REASON_WATCHPOINT;
393 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
394 target->debug_reason = DBG_REASON_BREAKPOINT;
395 else if (cortex_m->nvic_dfsr & DFSR_EXTERNAL)
396 target->debug_reason = DBG_REASON_DBGRQ;
397 else /* HALTED */
398 target->debug_reason = DBG_REASON_UNDEFINED;
399 }
400
401 return ERROR_OK;
402 }
403
404 static int cortex_m_examine_exception_reason(struct target *target)
405 {
406 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
407 struct armv7m_common *armv7m = target_to_armv7m(target);
408 struct adiv5_dap *swjdp = armv7m->arm.dap;
409 int retval;
410
411 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
412 if (retval != ERROR_OK)
413 return retval;
414 switch (armv7m->exception_number) {
415 case 2: /* NMI */
416 break;
417 case 3: /* Hard Fault */
418 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
419 if (retval != ERROR_OK)
420 return retval;
421 if (except_sr & 0x40000000) {
422 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
423 if (retval != ERROR_OK)
424 return retval;
425 }
426 break;
427 case 4: /* Memory Management */
428 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
429 if (retval != ERROR_OK)
430 return retval;
431 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
432 if (retval != ERROR_OK)
433 return retval;
434 break;
435 case 5: /* Bus Fault */
436 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
437 if (retval != ERROR_OK)
438 return retval;
439 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
440 if (retval != ERROR_OK)
441 return retval;
442 break;
443 case 6: /* Usage Fault */
444 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
445 if (retval != ERROR_OK)
446 return retval;
447 break;
448 case 7: /* Secure Fault */
449 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr);
450 if (retval != ERROR_OK)
451 return retval;
452 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar);
453 if (retval != ERROR_OK)
454 return retval;
455 break;
456 case 11: /* SVCall */
457 break;
458 case 12: /* Debug Monitor */
459 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
460 if (retval != ERROR_OK)
461 return retval;
462 break;
463 case 14: /* PendSV */
464 break;
465 case 15: /* SysTick */
466 break;
467 default:
468 except_sr = 0;
469 break;
470 }
471 retval = dap_run(swjdp);
472 if (retval == ERROR_OK)
473 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
474 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
475 armv7m_exception_string(armv7m->exception_number),
476 shcsr, except_sr, cfsr, except_ar);
477 return retval;
478 }
479
480 static int cortex_m_debug_entry(struct target *target)
481 {
482 int i;
483 uint32_t xPSR;
484 int retval;
485 struct cortex_m_common *cortex_m = target_to_cm(target);
486 struct armv7m_common *armv7m = &cortex_m->armv7m;
487 struct arm *arm = &armv7m->arm;
488 struct reg *r;
489
490 LOG_DEBUG(" ");
491
492 /* Do this really early to minimize the window where the MASKINTS erratum
493 * can pile up pending interrupts. */
494 cortex_m_set_maskints_for_halt(target);
495
496 cortex_m_clear_halt(target);
497 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
498 if (retval != ERROR_OK)
499 return retval;
500
501 retval = armv7m->examine_debug_reason(target);
502 if (retval != ERROR_OK)
503 return retval;
504
505 /* examine PE security state */
506 bool secure_state = false;
507 if (armv7m->arm.is_armv8m) {
508 uint32_t dscsr;
509
510 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr);
511 if (retval != ERROR_OK)
512 return retval;
513
514 secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
515 }
516
517 /* Examine target state and mode
518 * First load register accessible through core debug port */
519 int num_regs = arm->core_cache->num_regs;
520
521 for (i = 0; i < num_regs; i++) {
522 r = &armv7m->arm.core_cache->reg_list[i];
523 if (!r->valid)
524 arm->read_core_reg(target, r, i, ARM_MODE_ANY);
525 }
526
527 r = arm->cpsr;
528 xPSR = buf_get_u32(r->value, 0, 32);
529
530 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
531 if (xPSR & 0xf00) {
532 r->dirty = r->valid;
533 cortex_m_store_core_reg_u32(target, 16, xPSR & ~0xff);
534 }
535
536 /* Are we in an exception handler */
537 if (xPSR & 0x1FF) {
538 armv7m->exception_number = (xPSR & 0x1FF);
539
540 arm->core_mode = ARM_MODE_HANDLER;
541 arm->map = armv7m_msp_reg_map;
542 } else {
543 unsigned control = buf_get_u32(arm->core_cache
544 ->reg_list[ARMV7M_CONTROL].value, 0, 3);
545
546 /* is this thread privileged? */
547 arm->core_mode = control & 1
548 ? ARM_MODE_USER_THREAD
549 : ARM_MODE_THREAD;
550
551 /* which stack is it using? */
552 if (control & 2)
553 arm->map = armv7m_psp_reg_map;
554 else
555 arm->map = armv7m_msp_reg_map;
556
557 armv7m->exception_number = 0;
558 }
559
560 if (armv7m->exception_number)
561 cortex_m_examine_exception_reason(target);
562
563 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", cpu in %s state, target->state: %s",
564 arm_mode_name(arm->core_mode),
565 buf_get_u32(arm->pc->value, 0, 32),
566 secure_state ? "Secure" : "Non-Secure",
567 target_state_name(target));
568
569 if (armv7m->post_debug_entry) {
570 retval = armv7m->post_debug_entry(target);
571 if (retval != ERROR_OK)
572 return retval;
573 }
574
575 return ERROR_OK;
576 }
577
578 static int cortex_m_poll(struct target *target)
579 {
580 int detected_failure = ERROR_OK;
581 int retval = ERROR_OK;
582 enum target_state prev_target_state = target->state;
583 struct cortex_m_common *cortex_m = target_to_cm(target);
584 struct armv7m_common *armv7m = &cortex_m->armv7m;
585
586 /* Read from Debug Halting Control and Status Register */
587 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
588 if (retval != ERROR_OK) {
589 target->state = TARGET_UNKNOWN;
590 return retval;
591 }
592
593 /* Recover from lockup. See ARMv7-M architecture spec,
594 * section B1.5.15 "Unrecoverable exception cases".
595 */
596 if (cortex_m->dcb_dhcsr & S_LOCKUP) {
597 LOG_ERROR("%s -- clearing lockup after double fault",
598 target_name(target));
599 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
600 target->debug_reason = DBG_REASON_DBGRQ;
601
602 /* We have to execute the rest (the "finally" equivalent, but
603 * still throw this exception again).
604 */
605 detected_failure = ERROR_FAIL;
606
607 /* refresh status bits */
608 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
609 if (retval != ERROR_OK)
610 return retval;
611 }
612
613 if (cortex_m->dcb_dhcsr & S_RESET_ST) {
614 if (target->state != TARGET_RESET) {
615 target->state = TARGET_RESET;
616 LOG_INFO("%s: external reset detected", target_name(target));
617 }
618 return ERROR_OK;
619 }
620
621 if (target->state == TARGET_RESET) {
622 /* Cannot switch context while running so endreset is
623 * called with target->state == TARGET_RESET
624 */
625 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
626 cortex_m->dcb_dhcsr);
627 retval = cortex_m_endreset_event(target);
628 if (retval != ERROR_OK) {
629 target->state = TARGET_UNKNOWN;
630 return retval;
631 }
632 target->state = TARGET_RUNNING;
633 prev_target_state = TARGET_RUNNING;
634 }
635
636 if (cortex_m->dcb_dhcsr & S_HALT) {
637 target->state = TARGET_HALTED;
638
639 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
640 retval = cortex_m_debug_entry(target);
641 if (retval != ERROR_OK)
642 return retval;
643
644 if (arm_semihosting(target, &retval) != 0)
645 return retval;
646
647 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
648 }
649 if (prev_target_state == TARGET_DEBUG_RUNNING) {
650 LOG_DEBUG(" ");
651 retval = cortex_m_debug_entry(target);
652 if (retval != ERROR_OK)
653 return retval;
654
655 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
656 }
657 }
658
659 if (target->state == TARGET_UNKNOWN) {
660 /* check if processor is retiring instructions or sleeping */
661 if (cortex_m->dcb_dhcsr & S_RETIRE_ST || cortex_m->dcb_dhcsr & S_SLEEP) {
662 target->state = TARGET_RUNNING;
663 retval = ERROR_OK;
664 }
665 }
666
667 /* Check that target is truly halted, since the target could be resumed externally */
668 if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
669 /* registers are now invalid */
670 register_cache_invalidate(armv7m->arm.core_cache);
671
672 target->state = TARGET_RUNNING;
673 LOG_WARNING("%s: external resume detected", target_name(target));
674 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
675 retval = ERROR_OK;
676 }
677
678 /* Did we detect a failure condition that we cleared? */
679 if (detected_failure != ERROR_OK)
680 retval = detected_failure;
681 return retval;
682 }
683
684 static int cortex_m_halt(struct target *target)
685 {
686 LOG_DEBUG("target->state: %s",
687 target_state_name(target));
688
689 if (target->state == TARGET_HALTED) {
690 LOG_DEBUG("target was already halted");
691 return ERROR_OK;
692 }
693
694 if (target->state == TARGET_UNKNOWN)
695 LOG_WARNING("target was in unknown state when halt was requested");
696
697 if (target->state == TARGET_RESET) {
698 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
699 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
700 return ERROR_TARGET_FAILURE;
701 } else {
702 /* we came here in a reset_halt or reset_init sequence
703 * debug entry was already prepared in cortex_m3_assert_reset()
704 */
705 target->debug_reason = DBG_REASON_DBGRQ;
706
707 return ERROR_OK;
708 }
709 }
710
711 /* Write to Debug Halting Control and Status Register */
712 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
713
714 /* Do this really early to minimize the window where the MASKINTS erratum
715 * can pile up pending interrupts. */
716 cortex_m_set_maskints_for_halt(target);
717
718 target->debug_reason = DBG_REASON_DBGRQ;
719
720 return ERROR_OK;
721 }
722
723 static int cortex_m_soft_reset_halt(struct target *target)
724 {
725 struct cortex_m_common *cortex_m = target_to_cm(target);
726 struct armv7m_common *armv7m = &cortex_m->armv7m;
727 uint32_t dcb_dhcsr = 0;
728 int retval, timeout = 0;
729
730 /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
731 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
732 * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
733 * core, not the peripherals */
734 LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
735
736 /* Set C_DEBUGEN */
737 retval = cortex_m_write_debug_halt_mask(target, 0, C_STEP | C_MASKINTS);
738 if (retval != ERROR_OK)
739 return retval;
740
741 /* Enter debug state on reset; restore DEMCR in endreset_event() */
742 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
743 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
744 if (retval != ERROR_OK)
745 return retval;
746
747 /* Request a core-only reset */
748 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
749 AIRCR_VECTKEY | AIRCR_VECTRESET);
750 if (retval != ERROR_OK)
751 return retval;
752 target->state = TARGET_RESET;
753
754 /* registers are now invalid */
755 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
756
757 while (timeout < 100) {
758 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
759 if (retval == ERROR_OK) {
760 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
761 &cortex_m->nvic_dfsr);
762 if (retval != ERROR_OK)
763 return retval;
764 if ((dcb_dhcsr & S_HALT)
765 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
766 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
767 "DFSR 0x%08x",
768 (unsigned) dcb_dhcsr,
769 (unsigned) cortex_m->nvic_dfsr);
770 cortex_m_poll(target);
771 /* FIXME restore user's vector catch config */
772 return ERROR_OK;
773 } else
774 LOG_DEBUG("waiting for system reset-halt, "
775 "DHCSR 0x%08x, %d ms",
776 (unsigned) dcb_dhcsr, timeout);
777 }
778 timeout++;
779 alive_sleep(1);
780 }
781
782 return ERROR_OK;
783 }
784
785 void cortex_m_enable_breakpoints(struct target *target)
786 {
787 struct breakpoint *breakpoint = target->breakpoints;
788
789 /* set any pending breakpoints */
790 while (breakpoint) {
791 if (!breakpoint->set)
792 cortex_m_set_breakpoint(target, breakpoint);
793 breakpoint = breakpoint->next;
794 }
795 }
796
797 static int cortex_m_resume(struct target *target, int current,
798 target_addr_t address, int handle_breakpoints, int debug_execution)
799 {
800 struct armv7m_common *armv7m = target_to_armv7m(target);
801 struct breakpoint *breakpoint = NULL;
802 uint32_t resume_pc;
803 struct reg *r;
804
805 if (target->state != TARGET_HALTED) {
806 LOG_WARNING("target not halted");
807 return ERROR_TARGET_NOT_HALTED;
808 }
809
810 if (!debug_execution) {
811 target_free_all_working_areas(target);
812 cortex_m_enable_breakpoints(target);
813 cortex_m_enable_watchpoints(target);
814 }
815
816 if (debug_execution) {
817 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
818
819 /* Disable interrupts */
820 /* We disable interrupts in the PRIMASK register instead of
821 * masking with C_MASKINTS. This is probably the same issue
822 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
823 * in parallel with disabled interrupts can cause local faults
824 * to not be taken.
825 *
826 * REVISIT this clearly breaks non-debug execution, since the
827 * PRIMASK register state isn't saved/restored... workaround
828 * by never resuming app code after debug execution.
829 */
830 buf_set_u32(r->value, 0, 1, 1);
831 r->dirty = true;
832 r->valid = true;
833
834 /* Make sure we are in Thumb mode */
835 r = armv7m->arm.cpsr;
836 buf_set_u32(r->value, 24, 1, 1);
837 r->dirty = true;
838 r->valid = true;
839 }
840
841 /* current = 1: continue on current pc, otherwise continue at <address> */
842 r = armv7m->arm.pc;
843 if (!current) {
844 buf_set_u32(r->value, 0, 32, address);
845 r->dirty = true;
846 r->valid = true;
847 }
848
849 /* if we halted last time due to a bkpt instruction
850 * then we have to manually step over it, otherwise
851 * the core will break again */
852
853 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
854 && !debug_execution)
855 armv7m_maybe_skip_bkpt_inst(target, NULL);
856
857 resume_pc = buf_get_u32(r->value, 0, 32);
858
859 armv7m_restore_context(target);
860
861 /* the front-end may request us not to handle breakpoints */
862 if (handle_breakpoints) {
863 /* Single step past breakpoint at current address */
864 breakpoint = breakpoint_find(target, resume_pc);
865 if (breakpoint) {
866 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
867 breakpoint->address,
868 breakpoint->unique_id);
869 cortex_m_unset_breakpoint(target, breakpoint);
870 cortex_m_single_step_core(target);
871 cortex_m_set_breakpoint(target, breakpoint);
872 }
873 }
874
875 /* Restart core */
876 cortex_m_set_maskints_for_run(target);
877 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
878
879 target->debug_reason = DBG_REASON_NOTHALTED;
880
881 /* registers are now invalid */
882 register_cache_invalidate(armv7m->arm.core_cache);
883
884 if (!debug_execution) {
885 target->state = TARGET_RUNNING;
886 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
887 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
888 } else {
889 target->state = TARGET_DEBUG_RUNNING;
890 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
891 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
892 }
893
894 return ERROR_OK;
895 }
896
897 /* int irqstepcount = 0; */
898 static int cortex_m_step(struct target *target, int current,
899 target_addr_t address, int handle_breakpoints)
900 {
901 struct cortex_m_common *cortex_m = target_to_cm(target);
902 struct armv7m_common *armv7m = &cortex_m->armv7m;
903 struct breakpoint *breakpoint = NULL;
904 struct reg *pc = armv7m->arm.pc;
905 bool bkpt_inst_found = false;
906 int retval;
907 bool isr_timed_out = false;
908
909 if (target->state != TARGET_HALTED) {
910 LOG_WARNING("target not halted");
911 return ERROR_TARGET_NOT_HALTED;
912 }
913
914 /* current = 1: continue on current pc, otherwise continue at <address> */
915 if (!current)
916 buf_set_u32(pc->value, 0, 32, address);
917
918 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
919
920 /* the front-end may request us not to handle breakpoints */
921 if (handle_breakpoints) {
922 breakpoint = breakpoint_find(target, pc_value);
923 if (breakpoint)
924 cortex_m_unset_breakpoint(target, breakpoint);
925 }
926
927 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
928
929 target->debug_reason = DBG_REASON_SINGLESTEP;
930
931 armv7m_restore_context(target);
932
933 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
934
935 /* if no bkpt instruction is found at pc then we can perform
936 * a normal step, otherwise we have to manually step over the bkpt
937 * instruction - as such simulate a step */
938 if (bkpt_inst_found == false) {
939 if (cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO) {
940 /* Automatic ISR masking mode off: Just step over the next
941 * instruction, with interrupts on or off as appropriate. */
942 cortex_m_set_maskints_for_step(target);
943 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
944 } else {
945 /* Process interrupts during stepping in a way they don't interfere
946 * debugging.
947 *
948 * Principle:
949 *
950 * Set a temporary break point at the current pc and let the core run
951 * with interrupts enabled. Pending interrupts get served and we run
952 * into the breakpoint again afterwards. Then we step over the next
953 * instruction with interrupts disabled.
954 *
955 * If the pending interrupts don't complete within time, we leave the
956 * core running. This may happen if the interrupts trigger faster
957 * than the core can process them or the handler doesn't return.
958 *
959 * If no more breakpoints are available we simply do a step with
960 * interrupts enabled.
961 *
962 */
963
964 /* 2012-09-29 ph
965 *
966 * If a break point is already set on the lower half word then a break point on
967 * the upper half word will not break again when the core is restarted. So we
968 * just step over the instruction with interrupts disabled.
969 *
970 * The documentation has no information about this, it was found by observation
971 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
972 * suffer from this problem.
973 *
974 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
975 * address has it always cleared. The former is done to indicate thumb mode
976 * to gdb.
977 *
978 */
979 if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
980 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
981 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
982 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
983 /* Re-enable interrupts if appropriate */
984 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
985 cortex_m_set_maskints_for_halt(target);
986 } else {
987
988 /* Set a temporary break point */
989 if (breakpoint) {
990 retval = cortex_m_set_breakpoint(target, breakpoint);
991 } else {
992 enum breakpoint_type type = BKPT_HARD;
993 if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
994 /* FPB rev.1 cannot handle such addr, try BKPT instr */
995 type = BKPT_SOFT;
996 }
997 retval = breakpoint_add(target, pc_value, 2, type);
998 }
999
1000 bool tmp_bp_set = (retval == ERROR_OK);
1001
1002 /* No more breakpoints left, just do a step */
1003 if (!tmp_bp_set) {
1004 cortex_m_set_maskints_for_step(target);
1005 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1006 /* Re-enable interrupts if appropriate */
1007 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1008 cortex_m_set_maskints_for_halt(target);
1009 } else {
1010 /* Start the core */
1011 LOG_DEBUG("Starting core to serve pending interrupts");
1012 int64_t t_start = timeval_ms();
1013 cortex_m_set_maskints_for_run(target);
1014 cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
1015
1016 /* Wait for pending handlers to complete or timeout */
1017 do {
1018 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
1019 DCB_DHCSR,
1020 &cortex_m->dcb_dhcsr);
1021 if (retval != ERROR_OK) {
1022 target->state = TARGET_UNKNOWN;
1023 return retval;
1024 }
1025 isr_timed_out = ((timeval_ms() - t_start) > 500);
1026 } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
1027
1028 /* only remove breakpoint if we created it */
1029 if (breakpoint)
1030 cortex_m_unset_breakpoint(target, breakpoint);
1031 else {
1032 /* Remove the temporary breakpoint */
1033 breakpoint_remove(target, pc_value);
1034 }
1035
1036 if (isr_timed_out) {
1037 LOG_DEBUG("Interrupt handlers didn't complete within time, "
1038 "leaving target running");
1039 } else {
1040 /* Step over next instruction with interrupts disabled */
1041 cortex_m_set_maskints_for_step(target);
1042 cortex_m_write_debug_halt_mask(target,
1043 C_HALT | C_MASKINTS,
1044 0);
1045 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1046 /* Re-enable interrupts if appropriate */
1047 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1048 cortex_m_set_maskints_for_halt(target);
1049 }
1050 }
1051 }
1052 }
1053 }
1054
1055 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1056 if (retval != ERROR_OK)
1057 return retval;
1058
1059 /* registers are now invalid */
1060 register_cache_invalidate(armv7m->arm.core_cache);
1061
1062 if (breakpoint)
1063 cortex_m_set_breakpoint(target, breakpoint);
1064
1065 if (isr_timed_out) {
1066 /* Leave the core running. The user has to stop execution manually. */
1067 target->debug_reason = DBG_REASON_NOTHALTED;
1068 target->state = TARGET_RUNNING;
1069 return ERROR_OK;
1070 }
1071
1072 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1073 " nvic_icsr = 0x%" PRIx32,
1074 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1075
1076 retval = cortex_m_debug_entry(target);
1077 if (retval != ERROR_OK)
1078 return retval;
1079 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1080
1081 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1082 " nvic_icsr = 0x%" PRIx32,
1083 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1084
1085 return ERROR_OK;
1086 }
1087
1088 static int cortex_m_assert_reset(struct target *target)
1089 {
1090 struct cortex_m_common *cortex_m = target_to_cm(target);
1091 struct armv7m_common *armv7m = &cortex_m->armv7m;
1092 enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
1093
1094 LOG_DEBUG("target->state: %s",
1095 target_state_name(target));
1096
1097 enum reset_types jtag_reset_config = jtag_get_reset_config();
1098
1099 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1100 /* allow scripts to override the reset event */
1101
1102 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1103 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1104 target->state = TARGET_RESET;
1105
1106 return ERROR_OK;
1107 }
1108
1109 /* some cores support connecting while srst is asserted
1110 * use that mode is it has been configured */
1111
1112 bool srst_asserted = false;
1113
1114 if (!target_was_examined(target)) {
1115 if (jtag_reset_config & RESET_HAS_SRST) {
1116 adapter_assert_reset();
1117 if (target->reset_halt)
1118 LOG_ERROR("Target not examined, will not halt after reset!");
1119 return ERROR_OK;
1120 } else {
1121 LOG_ERROR("Target not examined, reset NOT asserted!");
1122 return ERROR_FAIL;
1123 }
1124 }
1125
1126 if ((jtag_reset_config & RESET_HAS_SRST) &&
1127 (jtag_reset_config & RESET_SRST_NO_GATING)) {
1128 adapter_assert_reset();
1129 srst_asserted = true;
1130 }
1131
1132 /* Enable debug requests */
1133 int retval;
1134 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1135 /* Store important errors instead of failing and proceed to reset assert */
1136
1137 if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1138 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1139
1140 /* If the processor is sleeping in a WFI or WFE instruction, the
1141 * C_HALT bit must be asserted to regain control */
1142 if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1143 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1144
1145 mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1146 /* Ignore less important errors */
1147
1148 if (!target->reset_halt) {
1149 /* Set/Clear C_MASKINTS in a separate operation */
1150 cortex_m_set_maskints_for_run(target);
1151
1152 /* clear any debug flags before resuming */
1153 cortex_m_clear_halt(target);
1154
1155 /* clear C_HALT in dhcsr reg */
1156 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1157 } else {
1158 /* Halt in debug on reset; endreset_event() restores DEMCR.
1159 *
1160 * REVISIT catching BUSERR presumably helps to defend against
1161 * bad vector table entries. Should this include MMERR or
1162 * other flags too?
1163 */
1164 int retval2;
1165 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1166 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1167 if (retval != ERROR_OK || retval2 != ERROR_OK)
1168 LOG_INFO("AP write error, reset will not halt");
1169 }
1170
1171 if (jtag_reset_config & RESET_HAS_SRST) {
1172 /* default to asserting srst */
1173 if (!srst_asserted)
1174 adapter_assert_reset();
1175
1176 /* srst is asserted, ignore AP access errors */
1177 retval = ERROR_OK;
1178 } else {
1179 /* Use a standard Cortex-M3 software reset mechanism.
1180 * We default to using VECRESET as it is supported on all current cores
1181 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1182 * This has the disadvantage of not resetting the peripherals, so a
1183 * reset-init event handler is needed to perform any peripheral resets.
1184 */
1185 if (!cortex_m->vectreset_supported
1186 && reset_config == CORTEX_M_RESET_VECTRESET) {
1187 reset_config = CORTEX_M_RESET_SYSRESETREQ;
1188 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1189 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1190 }
1191
1192 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1193 ? "SYSRESETREQ" : "VECTRESET");
1194
1195 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1196 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1197 "handler to reset any peripherals or configure hardware srst support.");
1198 }
1199
1200 int retval3;
1201 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1202 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1203 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1204 if (retval3 != ERROR_OK)
1205 LOG_DEBUG("Ignoring AP write error right after reset");
1206
1207 retval3 = dap_dp_init(armv7m->debug_ap->dap);
1208 if (retval3 != ERROR_OK)
1209 LOG_ERROR("DP initialisation failed");
1210
1211 else {
1212 /* I do not know why this is necessary, but it
1213 * fixes strange effects (step/resume cause NMI
1214 * after reset) on LM3S6918 -- Michael Schwingen
1215 */
1216 uint32_t tmp;
1217 mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1218 }
1219 }
1220
1221 target->state = TARGET_RESET;
1222 jtag_sleep(50000);
1223
1224 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1225
1226 /* now return stored error code if any */
1227 if (retval != ERROR_OK)
1228 return retval;
1229
1230 if (target->reset_halt) {
1231 retval = target_halt(target);
1232 if (retval != ERROR_OK)
1233 return retval;
1234 }
1235
1236 return ERROR_OK;
1237 }
1238
1239 static int cortex_m_deassert_reset(struct target *target)
1240 {
1241 struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1242
1243 LOG_DEBUG("target->state: %s",
1244 target_state_name(target));
1245
1246 /* deassert reset lines */
1247 adapter_deassert_reset();
1248
1249 enum reset_types jtag_reset_config = jtag_get_reset_config();
1250
1251 if ((jtag_reset_config & RESET_HAS_SRST) &&
1252 !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1253 target_was_examined(target)) {
1254 int retval = dap_dp_init(armv7m->debug_ap->dap);
1255 if (retval != ERROR_OK) {
1256 LOG_ERROR("DP initialisation failed");
1257 return retval;
1258 }
1259 }
1260
1261 return ERROR_OK;
1262 }
1263
1264 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1265 {
1266 int retval;
1267 int fp_num = 0;
1268 struct cortex_m_common *cortex_m = target_to_cm(target);
1269 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1270
1271 if (breakpoint->set) {
1272 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1273 return ERROR_OK;
1274 }
1275
1276 if (breakpoint->type == BKPT_HARD) {
1277 uint32_t fpcr_value;
1278 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1279 fp_num++;
1280 if (fp_num >= cortex_m->fp_num_code) {
1281 LOG_ERROR("Can not find free FPB Comparator!");
1282 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1283 }
1284 breakpoint->set = fp_num + 1;
1285 fpcr_value = breakpoint->address | 1;
1286 if (cortex_m->fp_rev == 0) {
1287 if (breakpoint->address > 0x1FFFFFFF) {
1288 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1289 return ERROR_FAIL;
1290 }
1291 uint32_t hilo;
1292 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1293 fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1294 } else if (cortex_m->fp_rev > 1) {
1295 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1296 return ERROR_FAIL;
1297 }
1298 comparator_list[fp_num].used = true;
1299 comparator_list[fp_num].fpcr_value = fpcr_value;
1300 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1301 comparator_list[fp_num].fpcr_value);
1302 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1303 fp_num,
1304 comparator_list[fp_num].fpcr_value);
1305 if (!cortex_m->fpb_enabled) {
1306 LOG_DEBUG("FPB wasn't enabled, do it now");
1307 retval = cortex_m_enable_fpb(target);
1308 if (retval != ERROR_OK) {
1309 LOG_ERROR("Failed to enable the FPB");
1310 return retval;
1311 }
1312
1313 cortex_m->fpb_enabled = true;
1314 }
1315 } else if (breakpoint->type == BKPT_SOFT) {
1316 uint8_t code[4];
1317
1318 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1319 * semihosting; don't use that. Otherwise the BKPT
1320 * parameter is arbitrary.
1321 */
1322 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1323 retval = target_read_memory(target,
1324 breakpoint->address & 0xFFFFFFFE,
1325 breakpoint->length, 1,
1326 breakpoint->orig_instr);
1327 if (retval != ERROR_OK)
1328 return retval;
1329 retval = target_write_memory(target,
1330 breakpoint->address & 0xFFFFFFFE,
1331 breakpoint->length, 1,
1332 code);
1333 if (retval != ERROR_OK)
1334 return retval;
1335 breakpoint->set = true;
1336 }
1337
1338 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1339 breakpoint->unique_id,
1340 (int)(breakpoint->type),
1341 breakpoint->address,
1342 breakpoint->length,
1343 breakpoint->set);
1344
1345 return ERROR_OK;
1346 }
1347
1348 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1349 {
1350 int retval;
1351 struct cortex_m_common *cortex_m = target_to_cm(target);
1352 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1353
1354 if (!breakpoint->set) {
1355 LOG_WARNING("breakpoint not set");
1356 return ERROR_OK;
1357 }
1358
1359 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1360 breakpoint->unique_id,
1361 (int)(breakpoint->type),
1362 breakpoint->address,
1363 breakpoint->length,
1364 breakpoint->set);
1365
1366 if (breakpoint->type == BKPT_HARD) {
1367 int fp_num = breakpoint->set - 1;
1368 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1369 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1370 return ERROR_OK;
1371 }
1372 comparator_list[fp_num].used = false;
1373 comparator_list[fp_num].fpcr_value = 0;
1374 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1375 comparator_list[fp_num].fpcr_value);
1376 } else {
1377 /* restore original instruction (kept in target endianness) */
1378 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE,
1379 breakpoint->length, 1,
1380 breakpoint->orig_instr);
1381 if (retval != ERROR_OK)
1382 return retval;
1383 }
1384 breakpoint->set = false;
1385
1386 return ERROR_OK;
1387 }
1388
1389 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1390 {
1391 if (breakpoint->length == 3) {
1392 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1393 breakpoint->length = 2;
1394 }
1395
1396 if ((breakpoint->length != 2)) {
1397 LOG_INFO("only breakpoints of two bytes length supported");
1398 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1399 }
1400
1401 return cortex_m_set_breakpoint(target, breakpoint);
1402 }
1403
1404 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1405 {
1406 if (!breakpoint->set)
1407 return ERROR_OK;
1408
1409 return cortex_m_unset_breakpoint(target, breakpoint);
1410 }
1411
1412 static int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1413 {
1414 int dwt_num = 0;
1415 struct cortex_m_common *cortex_m = target_to_cm(target);
1416
1417 /* REVISIT Don't fully trust these "not used" records ... users
1418 * may set up breakpoints by hand, e.g. dual-address data value
1419 * watchpoint using comparator #1; comparator #0 matching cycle
1420 * count; send data trace info through ITM and TPIU; etc
1421 */
1422 struct cortex_m_dwt_comparator *comparator;
1423
1424 for (comparator = cortex_m->dwt_comparator_list;
1425 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1426 comparator++, dwt_num++)
1427 continue;
1428 if (dwt_num >= cortex_m->dwt_num_comp) {
1429 LOG_ERROR("Can not find free DWT Comparator");
1430 return ERROR_FAIL;
1431 }
1432 comparator->used = true;
1433 watchpoint->set = dwt_num + 1;
1434
1435 comparator->comp = watchpoint->address;
1436 target_write_u32(target, comparator->dwt_comparator_address + 0,
1437 comparator->comp);
1438
1439 if ((cortex_m->dwt_devarch & 0x1FFFFF) != DWT_DEVARCH_ARMV8M) {
1440 uint32_t mask = 0, temp;
1441
1442 /* watchpoint params were validated earlier */
1443 temp = watchpoint->length;
1444 while (temp) {
1445 temp >>= 1;
1446 mask++;
1447 }
1448 mask--;
1449
1450 comparator->mask = mask;
1451 target_write_u32(target, comparator->dwt_comparator_address + 4,
1452 comparator->mask);
1453
1454 switch (watchpoint->rw) {
1455 case WPT_READ:
1456 comparator->function = 5;
1457 break;
1458 case WPT_WRITE:
1459 comparator->function = 6;
1460 break;
1461 case WPT_ACCESS:
1462 comparator->function = 7;
1463 break;
1464 }
1465 } else {
1466 uint32_t data_size = watchpoint->length >> 1;
1467 comparator->mask = (watchpoint->length >> 1) | 1;
1468
1469 switch (watchpoint->rw) {
1470 case WPT_ACCESS:
1471 comparator->function = 4;
1472 break;
1473 case WPT_WRITE:
1474 comparator->function = 5;
1475 break;
1476 case WPT_READ:
1477 comparator->function = 6;
1478 break;
1479 }
1480 comparator->function = comparator->function | (1 << 4) |
1481 (data_size << 10);
1482 }
1483
1484 target_write_u32(target, comparator->dwt_comparator_address + 8,
1485 comparator->function);
1486
1487 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1488 watchpoint->unique_id, dwt_num,
1489 (unsigned) comparator->comp,
1490 (unsigned) comparator->mask,
1491 (unsigned) comparator->function);
1492 return ERROR_OK;
1493 }
1494
1495 static int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1496 {
1497 struct cortex_m_common *cortex_m = target_to_cm(target);
1498 struct cortex_m_dwt_comparator *comparator;
1499 int dwt_num;
1500
1501 if (!watchpoint->set) {
1502 LOG_WARNING("watchpoint (wpid: %d) not set",
1503 watchpoint->unique_id);
1504 return ERROR_OK;
1505 }
1506
1507 dwt_num = watchpoint->set - 1;
1508
1509 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1510 watchpoint->unique_id, dwt_num,
1511 (unsigned) watchpoint->address);
1512
1513 if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1514 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1515 return ERROR_OK;
1516 }
1517
1518 comparator = cortex_m->dwt_comparator_list + dwt_num;
1519 comparator->used = false;
1520 comparator->function = 0;
1521 target_write_u32(target, comparator->dwt_comparator_address + 8,
1522 comparator->function);
1523
1524 watchpoint->set = false;
1525
1526 return ERROR_OK;
1527 }
1528
1529 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1530 {
1531 struct cortex_m_common *cortex_m = target_to_cm(target);
1532
1533 if (cortex_m->dwt_comp_available < 1) {
1534 LOG_DEBUG("no comparators?");
1535 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1536 }
1537
1538 /* hardware doesn't support data value masking */
1539 if (watchpoint->mask != ~(uint32_t)0) {
1540 LOG_DEBUG("watchpoint value masks not supported");
1541 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1542 }
1543
1544 /* hardware allows address masks of up to 32K */
1545 unsigned mask;
1546
1547 for (mask = 0; mask < 16; mask++) {
1548 if ((1u << mask) == watchpoint->length)
1549 break;
1550 }
1551 if (mask == 16) {
1552 LOG_DEBUG("unsupported watchpoint length");
1553 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1554 }
1555 if (watchpoint->address & ((1 << mask) - 1)) {
1556 LOG_DEBUG("watchpoint address is unaligned");
1557 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1558 }
1559
1560 /* Caller doesn't seem to be able to describe watching for data
1561 * values of zero; that flags "no value".
1562 *
1563 * REVISIT This DWT may well be able to watch for specific data
1564 * values. Requires comparator #1 to set DATAVMATCH and match
1565 * the data, and another comparator (DATAVADDR0) matching addr.
1566 */
1567 if (watchpoint->value) {
1568 LOG_DEBUG("data value watchpoint not YET supported");
1569 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1570 }
1571
1572 cortex_m->dwt_comp_available--;
1573 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1574
1575 return ERROR_OK;
1576 }
1577
1578 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1579 {
1580 struct cortex_m_common *cortex_m = target_to_cm(target);
1581
1582 /* REVISIT why check? DWT can be updated with core running ... */
1583 if (target->state != TARGET_HALTED) {
1584 LOG_WARNING("target not halted");
1585 return ERROR_TARGET_NOT_HALTED;
1586 }
1587
1588 if (watchpoint->set)
1589 cortex_m_unset_watchpoint(target, watchpoint);
1590
1591 cortex_m->dwt_comp_available++;
1592 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1593
1594 return ERROR_OK;
1595 }
1596
1597 void cortex_m_enable_watchpoints(struct target *target)
1598 {
1599 struct watchpoint *watchpoint = target->watchpoints;
1600
1601 /* set any pending watchpoints */
1602 while (watchpoint) {
1603 if (!watchpoint->set)
1604 cortex_m_set_watchpoint(target, watchpoint);
1605 watchpoint = watchpoint->next;
1606 }
1607 }
1608
1609 static int cortex_m_load_core_reg_u32(struct target *target,
1610 uint32_t num, uint32_t *value)
1611 {
1612 int retval;
1613
1614 /* NOTE: we "know" here that the register identifiers used
1615 * in the v7m header match the Cortex-M3 Debug Core Register
1616 * Selector values for R0..R15, xPSR, MSP, and PSP.
1617 */
1618 switch (num) {
1619 case 0 ... 18:
1620 /* read a normal core register */
1621 retval = cortexm_dap_read_coreregister_u32(target, value, num);
1622
1623 if (retval != ERROR_OK) {
1624 LOG_ERROR("JTAG failure %i", retval);
1625 return ERROR_JTAG_DEVICE_ERROR;
1626 }
1627 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
1628 break;
1629
1630 case ARMV7M_FPSCR:
1631 /* Floating-point Status and Registers */
1632 retval = target_write_u32(target, DCB_DCRSR, 0x21);
1633 if (retval != ERROR_OK)
1634 return retval;
1635 retval = target_read_u32(target, DCB_DCRDR, value);
1636 if (retval != ERROR_OK)
1637 return retval;
1638 LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value);
1639 break;
1640
1641 case ARMV7M_S0 ... ARMV7M_S31:
1642 /* Floating-point Status and Registers */
1643 retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
1644 if (retval != ERROR_OK)
1645 return retval;
1646 retval = target_read_u32(target, DCB_DCRDR, value);
1647 if (retval != ERROR_OK)
1648 return retval;
1649 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32,
1650 (int)(num - ARMV7M_S0), *value);
1651 break;
1652
1653 case ARMV7M_PRIMASK:
1654 case ARMV7M_BASEPRI:
1655 case ARMV7M_FAULTMASK:
1656 case ARMV7M_CONTROL:
1657 /* Cortex-M3 packages these four registers as bitfields
1658 * in one Debug Core register. So say r0 and r2 docs;
1659 * it was removed from r1 docs, but still works.
1660 */
1661 cortexm_dap_read_coreregister_u32(target, value, 20);
1662
1663 switch (num) {
1664 case ARMV7M_PRIMASK:
1665 *value = buf_get_u32((uint8_t *)value, 0, 1);
1666 break;
1667
1668 case ARMV7M_BASEPRI:
1669 *value = buf_get_u32((uint8_t *)value, 8, 8);
1670 break;
1671
1672 case ARMV7M_FAULTMASK:
1673 *value = buf_get_u32((uint8_t *)value, 16, 1);
1674 break;
1675
1676 case ARMV7M_CONTROL:
1677 *value = buf_get_u32((uint8_t *)value, 24, 3);
1678 break;
1679 }
1680
1681 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1682 break;
1683
1684 default:
1685 return ERROR_COMMAND_SYNTAX_ERROR;
1686 }
1687
1688 return ERROR_OK;
1689 }
1690
1691 static int cortex_m_store_core_reg_u32(struct target *target,
1692 uint32_t num, uint32_t value)
1693 {
1694 int retval;
1695 uint32_t reg;
1696 struct armv7m_common *armv7m = target_to_armv7m(target);
1697
1698 /* NOTE: we "know" here that the register identifiers used
1699 * in the v7m header match the Cortex-M3 Debug Core Register
1700 * Selector values for R0..R15, xPSR, MSP, and PSP.
1701 */
1702 switch (num) {
1703 case 0 ... 18:
1704 retval = cortexm_dap_write_coreregister_u32(target, value, num);
1705 if (retval != ERROR_OK) {
1706 struct reg *r;
1707
1708 LOG_ERROR("JTAG failure");
1709 r = armv7m->arm.core_cache->reg_list + num;
1710 r->dirty = r->valid;
1711 return ERROR_JTAG_DEVICE_ERROR;
1712 }
1713 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1714 break;
1715
1716 case ARMV7M_FPSCR:
1717 /* Floating-point Status and Registers */
1718 retval = target_write_u32(target, DCB_DCRDR, value);
1719 if (retval != ERROR_OK)
1720 return retval;
1721 retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
1722 if (retval != ERROR_OK)
1723 return retval;
1724 LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
1725 break;
1726
1727 case ARMV7M_S0 ... ARMV7M_S31:
1728 /* Floating-point Status and Registers */
1729 retval = target_write_u32(target, DCB_DCRDR, value);
1730 if (retval != ERROR_OK)
1731 return retval;
1732 retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
1733 if (retval != ERROR_OK)
1734 return retval;
1735 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32,
1736 (int)(num - ARMV7M_S0), value);
1737 break;
1738
1739 case ARMV7M_PRIMASK:
1740 case ARMV7M_BASEPRI:
1741 case ARMV7M_FAULTMASK:
1742 case ARMV7M_CONTROL:
1743 /* Cortex-M3 packages these four registers as bitfields
1744 * in one Debug Core register. So say r0 and r2 docs;
1745 * it was removed from r1 docs, but still works.
1746 */
1747 cortexm_dap_read_coreregister_u32(target, &reg, 20);
1748
1749 switch (num) {
1750 case ARMV7M_PRIMASK:
1751 buf_set_u32((uint8_t *)&reg, 0, 1, value);
1752 break;
1753
1754 case ARMV7M_BASEPRI:
1755 buf_set_u32((uint8_t *)&reg, 8, 8, value);
1756 break;
1757
1758 case ARMV7M_FAULTMASK:
1759 buf_set_u32((uint8_t *)&reg, 16, 1, value);
1760 break;
1761
1762 case ARMV7M_CONTROL:
1763 buf_set_u32((uint8_t *)&reg, 24, 3, value);
1764 break;
1765 }
1766
1767 cortexm_dap_write_coreregister_u32(target, reg, 20);
1768
1769 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1770 break;
1771
1772 default:
1773 return ERROR_COMMAND_SYNTAX_ERROR;
1774 }
1775
1776 return ERROR_OK;
1777 }
1778
1779 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1780 uint32_t size, uint32_t count, uint8_t *buffer)
1781 {
1782 struct armv7m_common *armv7m = target_to_armv7m(target);
1783
1784 if (armv7m->arm.is_armv6m) {
1785 /* armv6m does not handle unaligned memory access */
1786 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1787 return ERROR_TARGET_UNALIGNED_ACCESS;
1788 }
1789
1790 return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1791 }
1792
1793 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1794 uint32_t size, uint32_t count, const uint8_t *buffer)
1795 {
1796 struct armv7m_common *armv7m = target_to_armv7m(target);
1797
1798 if (armv7m->arm.is_armv6m) {
1799 /* armv6m does not handle unaligned memory access */
1800 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1801 return ERROR_TARGET_UNALIGNED_ACCESS;
1802 }
1803
1804 return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1805 }
1806
1807 static int cortex_m_init_target(struct command_context *cmd_ctx,
1808 struct target *target)
1809 {
1810 armv7m_build_reg_cache(target);
1811 arm_semihosting_init(target);
1812 return ERROR_OK;
1813 }
1814
1815 void cortex_m_deinit_target(struct target *target)
1816 {
1817 struct cortex_m_common *cortex_m = target_to_cm(target);
1818
1819 free(cortex_m->fp_comparator_list);
1820
1821 cortex_m_dwt_free(target);
1822 armv7m_free_reg_cache(target);
1823
1824 free(target->private_config);
1825 free(cortex_m);
1826 }
1827
1828 int cortex_m_profiling(struct target *target, uint32_t *samples,
1829 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1830 {
1831 struct timeval timeout, now;
1832 struct armv7m_common *armv7m = target_to_armv7m(target);
1833 uint32_t reg_value;
1834 int retval;
1835
1836 retval = target_read_u32(target, DWT_PCSR, &reg_value);
1837 if (retval != ERROR_OK) {
1838 LOG_ERROR("Error while reading PCSR");
1839 return retval;
1840 }
1841 if (reg_value == 0) {
1842 LOG_INFO("PCSR sampling not supported on this processor.");
1843 return target_profiling_default(target, samples, max_num_samples, num_samples, seconds);
1844 }
1845
1846 gettimeofday(&timeout, NULL);
1847 timeval_add_time(&timeout, seconds, 0);
1848
1849 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1850
1851 /* Make sure the target is running */
1852 target_poll(target);
1853 if (target->state == TARGET_HALTED)
1854 retval = target_resume(target, 1, 0, 0, 0);
1855
1856 if (retval != ERROR_OK) {
1857 LOG_ERROR("Error while resuming target");
1858 return retval;
1859 }
1860
1861 uint32_t sample_count = 0;
1862
1863 for (;;) {
1864 if (armv7m && armv7m->debug_ap) {
1865 uint32_t read_count = max_num_samples - sample_count;
1866 if (read_count > 1024)
1867 read_count = 1024;
1868
1869 retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1870 (void *)&samples[sample_count],
1871 4, read_count, DWT_PCSR);
1872 sample_count += read_count;
1873 } else {
1874 target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1875 }
1876
1877 if (retval != ERROR_OK) {
1878 LOG_ERROR("Error while reading PCSR");
1879 return retval;
1880 }
1881
1882
1883 gettimeofday(&now, NULL);
1884 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1885 LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1886 break;
1887 }
1888 }
1889
1890 *num_samples = sample_count;
1891 return retval;
1892 }
1893
1894
1895 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1896 * on r/w if the core is not running, and clear on resume or reset ... or
1897 * at least, in a post_restore_context() method.
1898 */
1899
1900 struct dwt_reg_state {
1901 struct target *target;
1902 uint32_t addr;
1903 uint8_t value[4]; /* scratch/cache */
1904 };
1905
1906 static int cortex_m_dwt_get_reg(struct reg *reg)
1907 {
1908 struct dwt_reg_state *state = reg->arch_info;
1909
1910 uint32_t tmp;
1911 int retval = target_read_u32(state->target, state->addr, &tmp);
1912 if (retval != ERROR_OK)
1913 return retval;
1914
1915 buf_set_u32(state->value, 0, 32, tmp);
1916 return ERROR_OK;
1917 }
1918
1919 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1920 {
1921 struct dwt_reg_state *state = reg->arch_info;
1922
1923 return target_write_u32(state->target, state->addr,
1924 buf_get_u32(buf, 0, reg->size));
1925 }
1926
1927 struct dwt_reg {
1928 uint32_t addr;
1929 const char *name;
1930 unsigned size;
1931 };
1932
1933 static const struct dwt_reg dwt_base_regs[] = {
1934 { DWT_CTRL, "dwt_ctrl", 32, },
1935 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1936 * increments while the core is asleep.
1937 */
1938 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1939 /* plus some 8 bit counters, useful for profiling with TPIU */
1940 };
1941
1942 static const struct dwt_reg dwt_comp[] = {
1943 #define DWT_COMPARATOR(i) \
1944 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1945 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1946 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1947 DWT_COMPARATOR(0),
1948 DWT_COMPARATOR(1),
1949 DWT_COMPARATOR(2),
1950 DWT_COMPARATOR(3),
1951 DWT_COMPARATOR(4),
1952 DWT_COMPARATOR(5),
1953 DWT_COMPARATOR(6),
1954 DWT_COMPARATOR(7),
1955 DWT_COMPARATOR(8),
1956 DWT_COMPARATOR(9),
1957 DWT_COMPARATOR(10),
1958 DWT_COMPARATOR(11),
1959 DWT_COMPARATOR(12),
1960 DWT_COMPARATOR(13),
1961 DWT_COMPARATOR(14),
1962 DWT_COMPARATOR(15),
1963 #undef DWT_COMPARATOR
1964 };
1965
1966 static const struct reg_arch_type dwt_reg_type = {
1967 .get = cortex_m_dwt_get_reg,
1968 .set = cortex_m_dwt_set_reg,
1969 };
1970
1971 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1972 {
1973 struct dwt_reg_state *state;
1974
1975 state = calloc(1, sizeof(*state));
1976 if (!state)
1977 return;
1978 state->addr = d->addr;
1979 state->target = t;
1980
1981 r->name = d->name;
1982 r->size = d->size;
1983 r->value = state->value;
1984 r->arch_info = state;
1985 r->type = &dwt_reg_type;
1986 }
1987
1988 static void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1989 {
1990 uint32_t dwtcr;
1991 struct reg_cache *cache;
1992 struct cortex_m_dwt_comparator *comparator;
1993 int reg, i;
1994
1995 target_read_u32(target, DWT_CTRL, &dwtcr);
1996 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
1997 if (!dwtcr) {
1998 LOG_DEBUG("no DWT");
1999 return;
2000 }
2001
2002 target_read_u32(target, DWT_DEVARCH, &cm->dwt_devarch);
2003 LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
2004
2005 cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
2006 cm->dwt_comp_available = cm->dwt_num_comp;
2007 cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
2008 sizeof(struct cortex_m_dwt_comparator));
2009 if (!cm->dwt_comparator_list) {
2010 fail0:
2011 cm->dwt_num_comp = 0;
2012 LOG_ERROR("out of mem");
2013 return;
2014 }
2015
2016 cache = calloc(1, sizeof(*cache));
2017 if (!cache) {
2018 fail1:
2019 free(cm->dwt_comparator_list);
2020 goto fail0;
2021 }
2022 cache->name = "Cortex-M DWT registers";
2023 cache->num_regs = 2 + cm->dwt_num_comp * 3;
2024 cache->reg_list = calloc(cache->num_regs, sizeof(*cache->reg_list));
2025 if (!cache->reg_list) {
2026 free(cache);
2027 goto fail1;
2028 }
2029
2030 for (reg = 0; reg < 2; reg++)
2031 cortex_m_dwt_addreg(target, cache->reg_list + reg,
2032 dwt_base_regs + reg);
2033
2034 comparator = cm->dwt_comparator_list;
2035 for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
2036 int j;
2037
2038 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
2039 for (j = 0; j < 3; j++, reg++)
2040 cortex_m_dwt_addreg(target, cache->reg_list + reg,
2041 dwt_comp + 3 * i + j);
2042
2043 /* make sure we clear any watchpoints enabled on the target */
2044 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
2045 }
2046
2047 *register_get_last_cache_p(&target->reg_cache) = cache;
2048 cm->dwt_cache = cache;
2049
2050 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
2051 dwtcr, cm->dwt_num_comp,
2052 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
2053
2054 /* REVISIT: if num_comp > 1, check whether comparator #1 can
2055 * implement single-address data value watchpoints ... so we
2056 * won't need to check it later, when asked to set one up.
2057 */
2058 }
2059
2060 static void cortex_m_dwt_free(struct target *target)
2061 {
2062 struct cortex_m_common *cm = target_to_cm(target);
2063 struct reg_cache *cache = cm->dwt_cache;
2064
2065 free(cm->dwt_comparator_list);
2066 cm->dwt_comparator_list = NULL;
2067 cm->dwt_num_comp = 0;
2068
2069 if (cache) {
2070 register_unlink_cache(&target->reg_cache, cache);
2071
2072 if (cache->reg_list) {
2073 for (size_t i = 0; i < cache->num_regs; i++)
2074 free(cache->reg_list[i].arch_info);
2075 free(cache->reg_list);
2076 }
2077 free(cache);
2078 }
2079 cm->dwt_cache = NULL;
2080 }
2081
2082 #define MVFR0 0xe000ef40
2083 #define MVFR1 0xe000ef44
2084
2085 #define MVFR0_DEFAULT_M4 0x10110021
2086 #define MVFR1_DEFAULT_M4 0x11000011
2087
2088 #define MVFR0_DEFAULT_M7_SP 0x10110021
2089 #define MVFR0_DEFAULT_M7_DP 0x10110221
2090 #define MVFR1_DEFAULT_M7_SP 0x11000011
2091 #define MVFR1_DEFAULT_M7_DP 0x12000011
2092
2093 static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp,
2094 struct adiv5_ap **debug_ap)
2095 {
2096 if (dap_find_ap(swjdp, AP_TYPE_AHB3_AP, debug_ap) == ERROR_OK)
2097 return ERROR_OK;
2098
2099 return dap_find_ap(swjdp, AP_TYPE_AHB5_AP, debug_ap);
2100 }
2101
2102 int cortex_m_examine(struct target *target)
2103 {
2104 int retval;
2105 uint32_t cpuid, fpcr, mvfr0, mvfr1;
2106 int i;
2107 struct cortex_m_common *cortex_m = target_to_cm(target);
2108 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
2109 struct armv7m_common *armv7m = target_to_armv7m(target);
2110
2111 /* stlink shares the examine handler but does not support
2112 * all its calls */
2113 if (!armv7m->stlink) {
2114 if (cortex_m->apsel == DP_APSEL_INVALID) {
2115 /* Search for the MEM-AP */
2116 retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
2117 if (retval != ERROR_OK) {
2118 LOG_ERROR("Could not find MEM-AP to control the core");
2119 return retval;
2120 }
2121 } else {
2122 armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
2123 }
2124
2125 /* Leave (only) generic DAP stuff for debugport_init(); */
2126 armv7m->debug_ap->memaccess_tck = 8;
2127
2128 retval = mem_ap_init(armv7m->debug_ap);
2129 if (retval != ERROR_OK)
2130 return retval;
2131 }
2132
2133 if (!target_was_examined(target)) {
2134 target_set_examined(target);
2135
2136 /* Read from Device Identification Registers */
2137 retval = target_read_u32(target, CPUID, &cpuid);
2138 if (retval != ERROR_OK)
2139 return retval;
2140
2141 /* Get CPU Type */
2142 i = (cpuid >> 4) & 0xf;
2143
2144 /* Check if it is an ARMv8-M core */
2145 armv7m->arm.is_armv8m = true;
2146
2147 switch (cpuid & ARM_CPUID_PARTNO_MASK) {
2148 case CORTEX_M23_PARTNO:
2149 i = 23;
2150 break;
2151 case CORTEX_M33_PARTNO:
2152 i = 33;
2153 break;
2154 case CORTEX_M35P_PARTNO:
2155 i = 35;
2156 break;
2157 case CORTEX_M55_PARTNO:
2158 i = 55;
2159 break;
2160 default:
2161 armv7m->arm.is_armv8m = false;
2162 break;
2163 }
2164
2165
2166 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
2167 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
2168 cortex_m->maskints_erratum = false;
2169 if (i == 7) {
2170 uint8_t rev, patch;
2171 rev = (cpuid >> 20) & 0xf;
2172 patch = (cpuid >> 0) & 0xf;
2173 if ((rev == 0) && (patch < 2)) {
2174 LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
2175 cortex_m->maskints_erratum = true;
2176 }
2177 }
2178 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2179
2180 /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
2181 cortex_m->vectreset_supported = i > 1;
2182
2183 if (i == 4) {
2184 target_read_u32(target, MVFR0, &mvfr0);
2185 target_read_u32(target, MVFR1, &mvfr1);
2186
2187 /* test for floating point feature on Cortex-M4 */
2188 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2189 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
2190 armv7m->fp_feature = FPv4_SP;
2191 }
2192 } else if (i == 7 || i == 33 || i == 35 || i == 55) {
2193 target_read_u32(target, MVFR0, &mvfr0);
2194 target_read_u32(target, MVFR1, &mvfr1);
2195
2196 /* test for floating point features on Cortex-M7 */
2197 if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2198 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
2199 armv7m->fp_feature = FPv5_SP;
2200 } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2201 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
2202 armv7m->fp_feature = FPv5_DP;
2203 }
2204 } else if (i == 0) {
2205 /* Cortex-M0 does not support unaligned memory access */
2206 armv7m->arm.is_armv6m = true;
2207 }
2208
2209 if (armv7m->fp_feature == FP_NONE &&
2210 armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
2211 /* free unavailable FPU registers */
2212 size_t idx;
2213
2214 for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
2215 idx < armv7m->arm.core_cache->num_regs;
2216 idx++) {
2217 free(armv7m->arm.core_cache->reg_list[idx].value);
2218 free(armv7m->arm.core_cache->reg_list[idx].feature);
2219 free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
2220 }
2221 armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
2222 }
2223
2224 if (!armv7m->stlink) {
2225 if (i == 3 || i == 4)
2226 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2227 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2228 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2229 else if (i == 7)
2230 /* Cortex-M7 has only 1024 bytes autoincrement range */
2231 armv7m->debug_ap->tar_autoincr_block = (1 << 10);
2232 }
2233
2234 /* Enable debug requests */
2235 retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr);
2236 if (retval != ERROR_OK)
2237 return retval;
2238 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
2239 uint32_t dhcsr = (cortex_m->dcb_dhcsr | C_DEBUGEN) & ~(C_HALT | C_STEP | C_MASKINTS);
2240
2241 retval = target_write_u32(target, DCB_DHCSR, DBGKEY | (dhcsr & 0x0000FFFFUL));
2242 if (retval != ERROR_OK)
2243 return retval;
2244 cortex_m->dcb_dhcsr = dhcsr;
2245 }
2246
2247 /* Configure trace modules */
2248 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2249 if (retval != ERROR_OK)
2250 return retval;
2251
2252 if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
2253 armv7m_trace_tpiu_config(target);
2254 armv7m_trace_itm_config(target);
2255 }
2256
2257 /* NOTE: FPB and DWT are both optional. */
2258
2259 /* Setup FPB */
2260 target_read_u32(target, FP_CTRL, &fpcr);
2261 /* bits [14:12] and [7:4] */
2262 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2263 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2264 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2265 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2266 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2267 free(cortex_m->fp_comparator_list);
2268 cortex_m->fp_comparator_list = calloc(
2269 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2270 sizeof(struct cortex_m_fp_comparator));
2271 cortex_m->fpb_enabled = fpcr & 1;
2272 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2273 cortex_m->fp_comparator_list[i].type =
2274 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2275 cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2276
2277 /* make sure we clear any breakpoints enabled on the target */
2278 target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2279 }
2280 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2281 fpcr,
2282 cortex_m->fp_num_code,
2283 cortex_m->fp_num_lit);
2284
2285 /* Setup DWT */
2286 cortex_m_dwt_free(target);
2287 cortex_m_dwt_setup(cortex_m, target);
2288
2289 /* These hardware breakpoints only work for code in flash! */
2290 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2291 target_name(target),
2292 cortex_m->fp_num_code,
2293 cortex_m->dwt_num_comp);
2294 }
2295
2296 return ERROR_OK;
2297 }
2298
2299 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2300 {
2301 struct armv7m_common *armv7m = target_to_armv7m(target);
2302 uint16_t dcrdr;
2303 uint8_t buf[2];
2304 int retval;
2305
2306 retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2307 if (retval != ERROR_OK)
2308 return retval;
2309
2310 dcrdr = target_buffer_get_u16(target, buf);
2311 *ctrl = (uint8_t)dcrdr;
2312 *value = (uint8_t)(dcrdr >> 8);
2313
2314 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2315
2316 /* write ack back to software dcc register
2317 * signify we have read data */
2318 if (dcrdr & (1 << 0)) {
2319 target_buffer_set_u16(target, buf, 0);
2320 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2321 if (retval != ERROR_OK)
2322 return retval;
2323 }
2324
2325 return ERROR_OK;
2326 }
2327
2328 static int cortex_m_target_request_data(struct target *target,
2329 uint32_t size, uint8_t *buffer)
2330 {
2331 uint8_t data;
2332 uint8_t ctrl;
2333 uint32_t i;
2334
2335 for (i = 0; i < (size * 4); i++) {
2336 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2337 if (retval != ERROR_OK)
2338 return retval;
2339 buffer[i] = data;
2340 }
2341
2342 return ERROR_OK;
2343 }
2344
2345 static int cortex_m_handle_target_request(void *priv)
2346 {
2347 struct target *target = priv;
2348 if (!target_was_examined(target))
2349 return ERROR_OK;
2350
2351 if (!target->dbg_msg_enabled)
2352 return ERROR_OK;
2353
2354 if (target->state == TARGET_RUNNING) {
2355 uint8_t data;
2356 uint8_t ctrl;
2357 int retval;
2358
2359 retval = cortex_m_dcc_read(target, &data, &ctrl);
2360 if (retval != ERROR_OK)
2361 return retval;
2362
2363 /* check if we have data */
2364 if (ctrl & (1 << 0)) {
2365 uint32_t request;
2366
2367 /* we assume target is quick enough */
2368 request = data;
2369 for (int i = 1; i <= 3; i++) {
2370 retval = cortex_m_dcc_read(target, &data, &ctrl);
2371 if (retval != ERROR_OK)
2372 return retval;
2373 request |= ((uint32_t)data << (i * 8));
2374 }
2375 target_request(target, request);
2376 }
2377 }
2378
2379 return ERROR_OK;
2380 }
2381
2382 static int cortex_m_init_arch_info(struct target *target,
2383 struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2384 {
2385 struct armv7m_common *armv7m = &cortex_m->armv7m;
2386
2387 armv7m_init_arch_info(target, armv7m);
2388
2389 /* default reset mode is to use srst if fitted
2390 * if not it will use CORTEX_M3_RESET_VECTRESET */
2391 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2392
2393 armv7m->arm.dap = dap;
2394
2395 /* register arch-specific functions */
2396 armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2397
2398 armv7m->post_debug_entry = NULL;
2399
2400 armv7m->pre_restore_context = NULL;
2401
2402 armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2403 armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2404
2405 target_register_timer_callback(cortex_m_handle_target_request, 1,
2406 TARGET_TIMER_TYPE_PERIODIC, target);
2407
2408 return ERROR_OK;
2409 }
2410
2411 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2412 {
2413 struct adiv5_private_config *pc;
2414
2415 pc = (struct adiv5_private_config *)target->private_config;
2416 if (adiv5_verify_config(pc) != ERROR_OK)
2417 return ERROR_FAIL;
2418
2419 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2420 if (cortex_m == NULL) {
2421 LOG_ERROR("No memory creating target");
2422 return ERROR_FAIL;
2423 }
2424
2425 cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2426 cortex_m->apsel = pc->ap_num;
2427
2428 cortex_m_init_arch_info(target, cortex_m, pc->dap);
2429
2430 return ERROR_OK;
2431 }
2432
2433 /*--------------------------------------------------------------------------*/
2434
2435 static int cortex_m_verify_pointer(struct command_invocation *cmd,
2436 struct cortex_m_common *cm)
2437 {
2438 if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2439 command_print(cmd, "target is not a Cortex-M");
2440 return ERROR_TARGET_INVALID;
2441 }
2442 return ERROR_OK;
2443 }
2444
2445 /*
2446 * Only stuff below this line should need to verify that its target
2447 * is a Cortex-M3. Everything else should have indirected through the
2448 * cortexm3_target structure, which is only used with CM3 targets.
2449 */
2450
2451 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2452 {
2453 struct target *target = get_current_target(CMD_CTX);
2454 struct cortex_m_common *cortex_m = target_to_cm(target);
2455 struct armv7m_common *armv7m = &cortex_m->armv7m;
2456 uint32_t demcr = 0;
2457 int retval;
2458
2459 static const struct {
2460 char name[10];
2461 unsigned mask;
2462 } vec_ids[] = {
2463 { "hard_err", VC_HARDERR, },
2464 { "int_err", VC_INTERR, },
2465 { "bus_err", VC_BUSERR, },
2466 { "state_err", VC_STATERR, },
2467 { "chk_err", VC_CHKERR, },
2468 { "nocp_err", VC_NOCPERR, },
2469 { "mm_err", VC_MMERR, },
2470 { "reset", VC_CORERESET, },
2471 };
2472
2473 retval = cortex_m_verify_pointer(CMD, cortex_m);
2474 if (retval != ERROR_OK)
2475 return retval;
2476
2477 if (!target_was_examined(target)) {
2478 LOG_ERROR("Target not examined yet");
2479 return ERROR_FAIL;
2480 }
2481
2482 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2483 if (retval != ERROR_OK)
2484 return retval;
2485
2486 if (CMD_ARGC > 0) {
2487 unsigned catch = 0;
2488
2489 if (CMD_ARGC == 1) {
2490 if (strcmp(CMD_ARGV[0], "all") == 0) {
2491 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2492 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2493 | VC_MMERR | VC_CORERESET;
2494 goto write;
2495 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2496 goto write;
2497 }
2498 while (CMD_ARGC-- > 0) {
2499 unsigned i;
2500 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2501 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2502 continue;
2503 catch |= vec_ids[i].mask;
2504 break;
2505 }
2506 if (i == ARRAY_SIZE(vec_ids)) {
2507 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2508 return ERROR_COMMAND_SYNTAX_ERROR;
2509 }
2510 }
2511 write:
2512 /* For now, armv7m->demcr only stores vector catch flags. */
2513 armv7m->demcr = catch;
2514
2515 demcr &= ~0xffff;
2516 demcr |= catch;
2517
2518 /* write, but don't assume it stuck (why not??) */
2519 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2520 if (retval != ERROR_OK)
2521 return retval;
2522 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2523 if (retval != ERROR_OK)
2524 return retval;
2525
2526 /* FIXME be sure to clear DEMCR on clean server shutdown.
2527 * Otherwise the vector catch hardware could fire when there's
2528 * no debugger hooked up, causing much confusion...
2529 */
2530 }
2531
2532 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2533 command_print(CMD, "%9s: %s", vec_ids[i].name,
2534 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2535 }
2536
2537 return ERROR_OK;
2538 }
2539
2540 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2541 {
2542 struct target *target = get_current_target(CMD_CTX);
2543 struct cortex_m_common *cortex_m = target_to_cm(target);
2544 int retval;
2545
2546 static const Jim_Nvp nvp_maskisr_modes[] = {
2547 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2548 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2549 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2550 { .name = "steponly", .value = CORTEX_M_ISRMASK_STEPONLY },
2551 { .name = NULL, .value = -1 },
2552 };
2553 const Jim_Nvp *n;
2554
2555
2556 retval = cortex_m_verify_pointer(CMD, cortex_m);
2557 if (retval != ERROR_OK)
2558 return retval;
2559
2560 if (target->state != TARGET_HALTED) {
2561 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
2562 return ERROR_OK;
2563 }
2564
2565 if (CMD_ARGC > 0) {
2566 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2567 if (n->name == NULL)
2568 return ERROR_COMMAND_SYNTAX_ERROR;
2569 cortex_m->isrmasking_mode = n->value;
2570 cortex_m_set_maskints_for_halt(target);
2571 }
2572
2573 n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2574 command_print(CMD, "cortex_m interrupt mask %s", n->name);
2575
2576 return ERROR_OK;
2577 }
2578
2579 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2580 {
2581 struct target *target = get_current_target(CMD_CTX);
2582 struct cortex_m_common *cortex_m = target_to_cm(target);
2583 int retval;
2584 char *reset_config;
2585
2586 retval = cortex_m_verify_pointer(CMD, cortex_m);
2587 if (retval != ERROR_OK)
2588 return retval;
2589
2590 if (CMD_ARGC > 0) {
2591 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2592 cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2593
2594 else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
2595 if (target_was_examined(target)
2596 && !cortex_m->vectreset_supported)
2597 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2598 else
2599 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2600
2601 } else
2602 return ERROR_COMMAND_SYNTAX_ERROR;
2603 }
2604
2605 switch (cortex_m->soft_reset_config) {
2606 case CORTEX_M_RESET_SYSRESETREQ:
2607 reset_config = "sysresetreq";
2608 break;
2609
2610 case CORTEX_M_RESET_VECTRESET:
2611 reset_config = "vectreset";
2612 break;
2613
2614 default:
2615 reset_config = "unknown";
2616 break;
2617 }
2618
2619 command_print(CMD, "cortex_m reset_config %s", reset_config);
2620
2621 return ERROR_OK;
2622 }
2623
2624 static const struct command_registration cortex_m_exec_command_handlers[] = {
2625 {
2626 .name = "maskisr",
2627 .handler = handle_cortex_m_mask_interrupts_command,
2628 .mode = COMMAND_EXEC,
2629 .help = "mask cortex_m interrupts",
2630 .usage = "['auto'|'on'|'off'|'steponly']",
2631 },
2632 {
2633 .name = "vector_catch",
2634 .handler = handle_cortex_m_vector_catch_command,
2635 .mode = COMMAND_EXEC,
2636 .help = "configure hardware vectors to trigger debug entry",
2637 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2638 },
2639 {
2640 .name = "reset_config",
2641 .handler = handle_cortex_m_reset_config_command,
2642 .mode = COMMAND_ANY,
2643 .help = "configure software reset handling",
2644 .usage = "['sysresetreq'|'vectreset']",
2645 },
2646 COMMAND_REGISTRATION_DONE
2647 };
2648 static const struct command_registration cortex_m_command_handlers[] = {
2649 {
2650 .chain = armv7m_command_handlers,
2651 },
2652 {
2653 .chain = armv7m_trace_command_handlers,
2654 },
2655 {
2656 .name = "cortex_m",
2657 .mode = COMMAND_EXEC,
2658 .help = "Cortex-M command group",
2659 .usage = "",
2660 .chain = cortex_m_exec_command_handlers,
2661 },
2662 COMMAND_REGISTRATION_DONE
2663 };
2664
2665 struct target_type cortexm_target = {
2666 .name = "cortex_m",
2667 .deprecated_name = "cortex_m3",
2668
2669 .poll = cortex_m_poll,
2670 .arch_state = armv7m_arch_state,
2671
2672 .target_request_data = cortex_m_target_request_data,
2673
2674 .halt = cortex_m_halt,
2675 .resume = cortex_m_resume,
2676 .step = cortex_m_step,
2677
2678 .assert_reset = cortex_m_assert_reset,
2679 .deassert_reset = cortex_m_deassert_reset,
2680 .soft_reset_halt = cortex_m_soft_reset_halt,
2681
2682 .get_gdb_arch = arm_get_gdb_arch,
2683 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2684
2685 .read_memory = cortex_m_read_memory,
2686 .write_memory = cortex_m_write_memory,
2687 .checksum_memory = armv7m_checksum_memory,
2688 .blank_check_memory = armv7m_blank_check_memory,
2689
2690 .run_algorithm = armv7m_run_algorithm,
2691 .start_algorithm = armv7m_start_algorithm,
2692 .wait_algorithm = armv7m_wait_algorithm,
2693
2694 .add_breakpoint = cortex_m_add_breakpoint,
2695 .remove_breakpoint = cortex_m_remove_breakpoint,
2696 .add_watchpoint = cortex_m_add_watchpoint,
2697 .remove_watchpoint = cortex_m_remove_watchpoint,
2698
2699 .commands = cortex_m_command_handlers,
2700 .target_create = cortex_m_target_create,
2701 .target_jim_configure = adiv5_jim_configure,
2702 .init_target = cortex_m_init_target,
2703 .examine = cortex_m_examine,
2704 .deinit_target = cortex_m_deinit_target,
2705
2706 .profiling = cortex_m_profiling,
2707 };
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