1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
29 ***************************************************************************/
34 #include "jtag/interface.h"
35 #include "breakpoints.h"
37 #include "target_request.h"
38 #include "target_type.h"
39 #include "arm_disassembler.h"
41 #include "arm_opcodes.h"
42 #include "arm_semihosting.h"
43 #include <helper/time_support.h>
45 /* NOTE: most of this should work fine for the Cortex-M1 and
46 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
47 * Some differences: M0/M1 doesn't have FBP remapping or the
48 * DWT tracing/profiling support. (So the cycle counter will
49 * not be usable; the other stuff isn't currently used here.)
51 * Although there are some workarounds for errata seen only in r0p0
52 * silicon, such old parts are hard to find and thus not much tested
57 * Returns the type of a break point required by address location
59 #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
62 /* forward declarations */
63 static int cortex_m3_store_core_reg_u32(struct target
*target
,
64 enum armv7m_regtype type
, uint32_t num
, uint32_t value
);
66 static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap
*swjdp
,
67 uint32_t *value
, int regnum
)
72 /* because the DCB_DCRDR is used for the emulated dcc channel
73 * we have to save/restore the DCB_DCRDR when used */
75 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
76 if (retval
!= ERROR_OK
)
79 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
80 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
81 if (retval
!= ERROR_OK
)
83 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
);
84 if (retval
!= ERROR_OK
)
87 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
88 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
89 if (retval
!= ERROR_OK
)
91 retval
= dap_queue_ap_read(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
92 if (retval
!= ERROR_OK
)
95 retval
= dap_run(swjdp
);
96 if (retval
!= ERROR_OK
)
99 /* restore DCB_DCRDR - this needs to be in a seperate
100 * transaction otherwise the emulated DCC channel breaks */
101 if (retval
== ERROR_OK
)
102 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
107 static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap
*swjdp
,
108 uint32_t value
, int regnum
)
113 /* because the DCB_DCRDR is used for the emulated dcc channel
114 * we have to save/restore the DCB_DCRDR when used */
116 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
117 if (retval
!= ERROR_OK
)
120 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
121 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
122 if (retval
!= ERROR_OK
)
124 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
125 if (retval
!= ERROR_OK
)
128 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
129 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
130 if (retval
!= ERROR_OK
)
132 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
| DCRSR_WnR
);
133 if (retval
!= ERROR_OK
)
136 retval
= dap_run(swjdp
);
137 if (retval
!= ERROR_OK
)
140 /* restore DCB_DCRDR - this needs to be in a seperate
141 * transaction otherwise the emulated DCC channel breaks */
142 if (retval
== ERROR_OK
)
143 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
148 static int cortex_m3_write_debug_halt_mask(struct target
*target
,
149 uint32_t mask_on
, uint32_t mask_off
)
151 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
152 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
154 /* mask off status bits */
155 cortex_m3
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
156 /* create new register mask */
157 cortex_m3
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
159 return mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, cortex_m3
->dcb_dhcsr
);
162 static int cortex_m3_clear_halt(struct target
*target
)
164 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
165 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
168 /* clear step if any */
169 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
171 /* Read Debug Fault Status Register */
172 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m3
->nvic_dfsr
);
173 if (retval
!= ERROR_OK
)
176 /* Clear Debug Fault Status */
177 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_DFSR
, cortex_m3
->nvic_dfsr
);
178 if (retval
!= ERROR_OK
)
180 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m3
->nvic_dfsr
);
185 static int cortex_m3_single_step_core(struct target
*target
)
187 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
188 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
192 /* backup dhcsr reg */
193 dhcsr_save
= cortex_m3
->dcb_dhcsr
;
195 /* Mask interrupts before clearing halt, if done already. This avoids
196 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
197 * HALT can put the core into an unknown state.
199 if (!(cortex_m3
->dcb_dhcsr
& C_MASKINTS
)) {
200 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
201 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
202 if (retval
!= ERROR_OK
)
205 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
206 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
207 if (retval
!= ERROR_OK
)
211 /* restore dhcsr reg */
212 cortex_m3
->dcb_dhcsr
= dhcsr_save
;
213 cortex_m3_clear_halt(target
);
218 static int cortex_m3_endreset_event(struct target
*target
)
223 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
224 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
225 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
226 struct cortex_m3_fp_comparator
*fp_list
= cortex_m3
->fp_comparator_list
;
227 struct cortex_m3_dwt_comparator
*dwt_list
= cortex_m3
->dwt_comparator_list
;
229 /* REVISIT The four debug monitor bits are currently ignored... */
230 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &dcb_demcr
);
231 if (retval
!= ERROR_OK
)
233 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"", dcb_demcr
);
235 /* this register is used for emulated dcc channel */
236 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
237 if (retval
!= ERROR_OK
)
240 /* Enable debug requests */
241 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
242 if (retval
!= ERROR_OK
)
244 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
)) {
245 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
246 if (retval
!= ERROR_OK
)
250 /* clear any interrupt masking */
251 cortex_m3_write_debug_halt_mask(target
, 0, C_MASKINTS
);
253 /* Enable features controlled by ITM and DWT blocks, and catch only
254 * the vectors we were told to pay attention to.
256 * Target firmware is responsible for all fault handling policy
257 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
258 * or manual updates to the NVIC SHCSR and CCR registers.
260 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
261 if (retval
!= ERROR_OK
)
264 /* Paranoia: evidently some (early?) chips don't preserve all the
265 * debug state (including FBP, DWT, etc) across reset...
269 retval
= target_write_u32(target
, FP_CTRL
, 3);
270 if (retval
!= ERROR_OK
)
273 cortex_m3
->fpb_enabled
= 1;
275 /* Restore FPB registers */
276 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++) {
277 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
278 if (retval
!= ERROR_OK
)
282 /* Restore DWT registers */
283 for (i
= 0; i
< cortex_m3
->dwt_num_comp
; i
++) {
284 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
286 if (retval
!= ERROR_OK
)
288 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
290 if (retval
!= ERROR_OK
)
292 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
293 dwt_list
[i
].function
);
294 if (retval
!= ERROR_OK
)
297 retval
= dap_run(swjdp
);
298 if (retval
!= ERROR_OK
)
301 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
303 /* make sure we have latest dhcsr flags */
304 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
309 static int cortex_m3_examine_debug_reason(struct target
*target
)
311 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
313 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
314 * only check the debug reason if we don't know it already */
316 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
317 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
318 if (cortex_m3
->nvic_dfsr
& DFSR_BKPT
) {
319 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
320 if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
321 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
322 } else if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
323 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
324 else if (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
)
325 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
326 else /* EXTERNAL, HALTED */
327 target
->debug_reason
= DBG_REASON_UNDEFINED
;
333 static int cortex_m3_examine_exception_reason(struct target
*target
)
335 uint32_t shcsr
= 0, except_sr
= 0, cfsr
= -1, except_ar
= -1;
336 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
337 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
340 retval
= mem_ap_read_u32(swjdp
, NVIC_SHCSR
, &shcsr
);
341 if (retval
!= ERROR_OK
)
343 switch (armv7m
->exception_number
) {
346 case 3: /* Hard Fault */
347 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_HFSR
, &except_sr
);
348 if (retval
!= ERROR_OK
)
350 if (except_sr
& 0x40000000) {
351 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &cfsr
);
352 if (retval
!= ERROR_OK
)
356 case 4: /* Memory Management */
357 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
358 if (retval
!= ERROR_OK
)
360 retval
= mem_ap_read_u32(swjdp
, NVIC_MMFAR
, &except_ar
);
361 if (retval
!= ERROR_OK
)
364 case 5: /* Bus Fault */
365 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
366 if (retval
!= ERROR_OK
)
368 retval
= mem_ap_read_u32(swjdp
, NVIC_BFAR
, &except_ar
);
369 if (retval
!= ERROR_OK
)
372 case 6: /* Usage Fault */
373 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
374 if (retval
!= ERROR_OK
)
377 case 11: /* SVCall */
379 case 12: /* Debug Monitor */
380 retval
= mem_ap_read_u32(swjdp
, NVIC_DFSR
, &except_sr
);
381 if (retval
!= ERROR_OK
)
384 case 14: /* PendSV */
386 case 15: /* SysTick */
392 retval
= dap_run(swjdp
);
393 if (retval
== ERROR_OK
)
394 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
395 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
396 armv7m_exception_string(armv7m
->exception_number
),
397 shcsr
, except_sr
, cfsr
, except_ar
);
401 static int cortex_m3_debug_entry(struct target
*target
)
406 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
407 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
408 struct arm
*arm
= &armv7m
->arm
;
409 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
414 cortex_m3_clear_halt(target
);
415 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
416 if (retval
!= ERROR_OK
)
419 retval
= armv7m
->examine_debug_reason(target
);
420 if (retval
!= ERROR_OK
)
423 /* Examine target state and mode
424 * First load register acessible through core debug port*/
425 int num_regs
= armv7m
->core_cache
->num_regs
;
427 for (i
= 0; i
< num_regs
; i
++) {
428 if (!armv7m
->core_cache
->reg_list
[i
].valid
)
429 armv7m
->read_core_reg(target
, i
);
432 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_xPSR
;
433 xPSR
= buf_get_u32(r
->value
, 0, 32);
435 #ifdef ARMV7_GDB_HACKS
436 /* FIXME this breaks on scan chains with more than one Cortex-M3.
437 * Instead, each CM3 should have its own dummy value...
439 /* copy real xpsr reg for gdb, setting thumb bit */
440 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 0, 32, xPSR
);
441 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 5, 1, 1);
442 armv7m_gdb_dummy_cpsr_reg
.valid
= r
->valid
;
443 armv7m_gdb_dummy_cpsr_reg
.dirty
= r
->dirty
;
446 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
449 cortex_m3_store_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 16, xPSR
& ~0xff);
452 /* Are we in an exception handler */
454 armv7m
->core_mode
= ARMV7M_MODE_HANDLER
;
455 armv7m
->exception_number
= (xPSR
& 0x1FF);
457 arm
->core_mode
= ARM_MODE_HANDLER
;
458 arm
->map
= armv7m_msp_reg_map
;
460 unsigned control
= buf_get_u32(armv7m
->core_cache
461 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 2);
463 /* is this thread privileged? */
464 armv7m
->core_mode
= control
& 1;
465 arm
->core_mode
= armv7m
->core_mode
466 ? ARM_MODE_USER_THREAD
469 /* which stack is it using? */
471 arm
->map
= armv7m_psp_reg_map
;
473 arm
->map
= armv7m_msp_reg_map
;
475 armv7m
->exception_number
= 0;
478 if (armv7m
->exception_number
)
479 cortex_m3_examine_exception_reason(target
);
481 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
482 armv7m_mode_strings
[armv7m
->core_mode
],
483 *(uint32_t *)(arm
->pc
->value
),
484 target_state_name(target
));
486 if (armv7m
->post_debug_entry
) {
487 retval
= armv7m
->post_debug_entry(target
);
488 if (retval
!= ERROR_OK
)
495 static int cortex_m3_poll(struct target
*target
)
497 int detected_failure
= ERROR_OK
;
498 int retval
= ERROR_OK
;
499 enum target_state prev_target_state
= target
->state
;
500 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
501 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
503 /* Read from Debug Halting Control and Status Register */
504 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
505 if (retval
!= ERROR_OK
) {
506 target
->state
= TARGET_UNKNOWN
;
510 /* Recover from lockup. See ARMv7-M architecture spec,
511 * section B1.5.15 "Unrecoverable exception cases".
513 if (cortex_m3
->dcb_dhcsr
& S_LOCKUP
) {
514 LOG_ERROR("%s -- clearing lockup after double fault",
515 target_name(target
));
516 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
517 target
->debug_reason
= DBG_REASON_DBGRQ
;
519 /* We have to execute the rest (the "finally" equivalent, but
520 * still throw this exception again).
522 detected_failure
= ERROR_FAIL
;
524 /* refresh status bits */
525 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
526 if (retval
!= ERROR_OK
)
530 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
) {
531 /* check if still in reset */
532 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
533 if (retval
!= ERROR_OK
)
536 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
) {
537 target
->state
= TARGET_RESET
;
542 if (target
->state
== TARGET_RESET
) {
543 /* Cannot switch context while running so endreset is
544 * called with target->state == TARGET_RESET
546 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
547 cortex_m3
->dcb_dhcsr
);
548 cortex_m3_endreset_event(target
);
549 target
->state
= TARGET_RUNNING
;
550 prev_target_state
= TARGET_RUNNING
;
553 if (cortex_m3
->dcb_dhcsr
& S_HALT
) {
554 target
->state
= TARGET_HALTED
;
556 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
)) {
557 retval
= cortex_m3_debug_entry(target
);
558 if (retval
!= ERROR_OK
)
561 if (arm_semihosting(target
, &retval
) != 0)
564 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
566 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
568 retval
= cortex_m3_debug_entry(target
);
569 if (retval
!= ERROR_OK
)
572 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
576 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
577 * How best to model low power modes?
580 if (target
->state
== TARGET_UNKNOWN
) {
581 /* check if processor is retiring instructions */
582 if (cortex_m3
->dcb_dhcsr
& S_RETIRE_ST
) {
583 target
->state
= TARGET_RUNNING
;
588 /* Did we detect a failure condition that we cleared? */
589 if (detected_failure
!= ERROR_OK
)
590 retval
= detected_failure
;
594 static int cortex_m3_halt(struct target
*target
)
596 LOG_DEBUG("target->state: %s",
597 target_state_name(target
));
599 if (target
->state
== TARGET_HALTED
) {
600 LOG_DEBUG("target was already halted");
604 if (target
->state
== TARGET_UNKNOWN
)
605 LOG_WARNING("target was in unknown state when halt was requested");
607 if (target
->state
== TARGET_RESET
) {
608 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
609 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
610 return ERROR_TARGET_FAILURE
;
612 /* we came here in a reset_halt or reset_init sequence
613 * debug entry was already prepared in cortex_m3_assert_reset()
615 target
->debug_reason
= DBG_REASON_DBGRQ
;
621 /* Write to Debug Halting Control and Status Register */
622 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
624 target
->debug_reason
= DBG_REASON_DBGRQ
;
629 static int cortex_m3_soft_reset_halt(struct target
*target
)
631 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
632 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
633 uint32_t dcb_dhcsr
= 0;
634 int retval
, timeout
= 0;
636 /* Enter debug state on reset; restore DEMCR in endreset_event() */
637 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
,
638 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
639 if (retval
!= ERROR_OK
)
642 /* Request a core-only reset */
643 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
644 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
645 if (retval
!= ERROR_OK
)
647 target
->state
= TARGET_RESET
;
649 /* registers are now invalid */
650 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
652 while (timeout
< 100) {
653 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &dcb_dhcsr
);
654 if (retval
== ERROR_OK
) {
655 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
,
656 &cortex_m3
->nvic_dfsr
);
657 if (retval
!= ERROR_OK
)
659 if ((dcb_dhcsr
& S_HALT
)
660 && (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
)) {
661 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
663 (unsigned) dcb_dhcsr
,
664 (unsigned) cortex_m3
->nvic_dfsr
);
665 cortex_m3_poll(target
);
666 /* FIXME restore user's vector catch config */
669 LOG_DEBUG("waiting for system reset-halt, "
670 "DHCSR 0x%08x, %d ms",
671 (unsigned) dcb_dhcsr
, timeout
);
680 static void cortex_m3_enable_breakpoints(struct target
*target
)
682 struct breakpoint
*breakpoint
= target
->breakpoints
;
684 /* set any pending breakpoints */
686 if (!breakpoint
->set
)
687 cortex_m3_set_breakpoint(target
, breakpoint
);
688 breakpoint
= breakpoint
->next
;
692 static int cortex_m3_resume(struct target
*target
, int current
,
693 uint32_t address
, int handle_breakpoints
, int debug_execution
)
695 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
696 struct breakpoint
*breakpoint
= NULL
;
700 if (target
->state
!= TARGET_HALTED
) {
701 LOG_WARNING("target not halted");
702 return ERROR_TARGET_NOT_HALTED
;
705 if (!debug_execution
) {
706 target_free_all_working_areas(target
);
707 cortex_m3_enable_breakpoints(target
);
708 cortex_m3_enable_watchpoints(target
);
711 if (debug_execution
) {
712 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_PRIMASK
;
714 /* Disable interrupts */
715 /* We disable interrupts in the PRIMASK register instead of
716 * masking with C_MASKINTS. This is probably the same issue
717 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
718 * in parallel with disabled interrupts can cause local faults
721 * REVISIT this clearly breaks non-debug execution, since the
722 * PRIMASK register state isn't saved/restored... workaround
723 * by never resuming app code after debug execution.
725 buf_set_u32(r
->value
, 0, 1, 1);
729 /* Make sure we are in Thumb mode */
730 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_xPSR
;
731 buf_set_u32(r
->value
, 24, 1, 1);
736 /* current = 1: continue on current pc, otherwise continue at <address> */
739 buf_set_u32(r
->value
, 0, 32, address
);
744 /* if we halted last time due to a bkpt instruction
745 * then we have to manually step over it, otherwise
746 * the core will break again */
748 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
750 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
752 resume_pc
= buf_get_u32(r
->value
, 0, 32);
754 armv7m_restore_context(target
);
756 /* the front-end may request us not to handle breakpoints */
757 if (handle_breakpoints
) {
758 /* Single step past breakpoint at current address */
759 breakpoint
= breakpoint_find(target
, resume_pc
);
761 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (ID: %d)",
763 breakpoint
->unique_id
);
764 cortex_m3_unset_breakpoint(target
, breakpoint
);
765 cortex_m3_single_step_core(target
);
766 cortex_m3_set_breakpoint(target
, breakpoint
);
771 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
773 target
->debug_reason
= DBG_REASON_NOTHALTED
;
775 /* registers are now invalid */
776 register_cache_invalidate(armv7m
->core_cache
);
778 if (!debug_execution
) {
779 target
->state
= TARGET_RUNNING
;
780 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
781 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
783 target
->state
= TARGET_DEBUG_RUNNING
;
784 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
785 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
791 /* int irqstepcount = 0; */
792 static int cortex_m3_step(struct target
*target
, int current
,
793 uint32_t address
, int handle_breakpoints
)
795 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
796 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
797 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
798 struct breakpoint
*breakpoint
= NULL
;
799 struct reg
*pc
= armv7m
->arm
.pc
;
800 bool bkpt_inst_found
= false;
802 bool isr_timed_out
= false;
804 if (target
->state
!= TARGET_HALTED
) {
805 LOG_WARNING("target not halted");
806 return ERROR_TARGET_NOT_HALTED
;
809 /* current = 1: continue on current pc, otherwise continue at <address> */
811 buf_set_u32(pc
->value
, 0, 32, address
);
813 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
815 /* the front-end may request us not to handle breakpoints */
816 if (handle_breakpoints
) {
817 breakpoint
= breakpoint_find(target
, pc_value
);
819 cortex_m3_unset_breakpoint(target
, breakpoint
);
822 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
824 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
826 armv7m_restore_context(target
);
828 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
830 /* if no bkpt instruction is found at pc then we can perform
831 * a normal step, otherwise we have to manually step over the bkpt
832 * instruction - as such simulate a step */
833 if (bkpt_inst_found
== false) {
834 /* Automatic ISR masking mode off: Just step over the next instruction */
835 if ((cortex_m3
->isrmasking_mode
!= CORTEX_M3_ISRMASK_AUTO
))
836 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
838 /* Process interrupts during stepping in a way they don't interfere
843 * Set a temporary break point at the current pc and let the core run
844 * with interrupts enabled. Pending interrupts get served and we run
845 * into the breakpoint again afterwards. Then we step over the next
846 * instruction with interrupts disabled.
848 * If the pending interrupts don't complete within time, we leave the
849 * core running. This may happen if the interrupts trigger faster
850 * than the core can process them or the handler doesn't return.
852 * If no more breakpoints are available we simply do a step with
853 * interrupts enabled.
857 /* Set a temporary break point */
858 retval
= breakpoint_add(target
, pc_value
, 2, BKPT_TYPE_BY_ADDR(pc_value
));
859 bool tmp_bp_set
= (retval
== ERROR_OK
);
861 /* No more breakpoints left, just do a step */
863 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
866 LOG_DEBUG("Starting core to serve pending interrupts");
867 int64_t t_start
= timeval_ms();
868 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
);
870 /* Wait for pending handlers to complete or timeout */
872 retval
= mem_ap_read_atomic_u32(swjdp
,
874 &cortex_m3
->dcb_dhcsr
);
875 if (retval
!= ERROR_OK
) {
876 target
->state
= TARGET_UNKNOWN
;
879 isr_timed_out
= ((timeval_ms() - t_start
) > 500);
880 } while (!((cortex_m3
->dcb_dhcsr
& S_HALT
) || isr_timed_out
));
882 /* Remove the temporary breakpoint */
883 breakpoint_remove(target
, pc_value
);
886 LOG_DEBUG("Interrupt handlers didn't complete within time, "
887 "leaving target running");
889 /* Step over next instruction with interrupts disabled */
890 cortex_m3_write_debug_halt_mask(target
,
893 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
894 /* Re-enable interrupts */
895 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
901 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
902 if (retval
!= ERROR_OK
)
905 /* registers are now invalid */
906 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
909 cortex_m3_set_breakpoint(target
, breakpoint
);
912 /* Leave the core running. The user has to stop execution manually. */
913 target
->debug_reason
= DBG_REASON_NOTHALTED
;
914 target
->state
= TARGET_RUNNING
;
918 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
919 " nvic_icsr = 0x%" PRIx32
,
920 cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
922 retval
= cortex_m3_debug_entry(target
);
923 if (retval
!= ERROR_OK
)
925 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
927 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
928 " nvic_icsr = 0x%" PRIx32
,
929 cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
934 static int cortex_m3_assert_reset(struct target
*target
)
936 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
937 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
938 enum cortex_m3_soft_reset_config reset_config
= cortex_m3
->soft_reset_config
;
940 LOG_DEBUG("target->state: %s",
941 target_state_name(target
));
943 enum reset_types jtag_reset_config
= jtag_get_reset_config();
945 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
946 /* allow scripts to override the reset event */
948 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
949 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
950 target
->state
= TARGET_RESET
;
955 /* some cores support connecting while srst is asserted
956 * use that mode is it has been configured */
958 bool srst_asserted
= false;
960 if (jtag_reset_config
& RESET_SRST_NO_GATING
) {
961 adapter_assert_reset();
962 srst_asserted
= true;
965 /* Enable debug requests */
967 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
968 if (retval
!= ERROR_OK
)
970 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
)) {
971 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
972 if (retval
!= ERROR_OK
)
976 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
977 if (retval
!= ERROR_OK
)
980 if (!target
->reset_halt
) {
981 /* Set/Clear C_MASKINTS in a separate operation */
982 if (cortex_m3
->dcb_dhcsr
& C_MASKINTS
) {
983 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
984 DBGKEY
| C_DEBUGEN
| C_HALT
);
985 if (retval
!= ERROR_OK
)
989 /* clear any debug flags before resuming */
990 cortex_m3_clear_halt(target
);
992 /* clear C_HALT in dhcsr reg */
993 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
995 /* Halt in debug on reset; endreset_event() restores DEMCR.
997 * REVISIT catching BUSERR presumably helps to defend against
998 * bad vector table entries. Should this include MMERR or
1001 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DEMCR
,
1002 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1003 if (retval
!= ERROR_OK
)
1007 if (jtag_reset_config
& RESET_HAS_SRST
) {
1008 /* default to asserting srst */
1010 adapter_assert_reset();
1012 /* Use a standard Cortex-M3 software reset mechanism.
1013 * We default to using VECRESET as it is supported on all current cores.
1014 * This has the disadvantage of not resetting the peripherals, so a
1015 * reset-init event handler is needed to perform any peripheral resets.
1017 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
1018 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M3_RESET_SYSRESETREQ
)
1019 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1020 if (retval
!= ERROR_OK
)
1023 LOG_DEBUG("Using Cortex-M3 %s", (reset_config
== CORTEX_M3_RESET_SYSRESETREQ
)
1024 ? "SYSRESETREQ" : "VECTRESET");
1026 if (reset_config
== CORTEX_M3_RESET_VECTRESET
) {
1027 LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
1028 "handler to reset any peripherals");
1032 /* I do not know why this is necessary, but it
1033 * fixes strange effects (step/resume cause NMI
1034 * after reset) on LM3S6918 -- Michael Schwingen
1037 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_AIRCR
, &tmp
);
1038 if (retval
!= ERROR_OK
)
1043 target
->state
= TARGET_RESET
;
1044 jtag_add_sleep(50000);
1046 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
1048 if (target
->reset_halt
) {
1049 retval
= target_halt(target
);
1050 if (retval
!= ERROR_OK
)
1057 static int cortex_m3_deassert_reset(struct target
*target
)
1059 LOG_DEBUG("target->state: %s",
1060 target_state_name(target
));
1062 /* deassert reset lines */
1063 adapter_deassert_reset();
1068 int cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1073 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1074 struct cortex_m3_fp_comparator
*comparator_list
= cortex_m3
->fp_comparator_list
;
1076 if (breakpoint
->set
) {
1077 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint
->unique_id
);
1081 if (cortex_m3
->auto_bp_type
)
1082 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1084 if (breakpoint
->type
== BKPT_HARD
) {
1085 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m3
->fp_num_code
))
1087 if (fp_num
>= cortex_m3
->fp_num_code
) {
1088 LOG_ERROR("Can not find free FPB Comparator!");
1091 breakpoint
->set
= fp_num
+ 1;
1092 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1093 comparator_list
[fp_num
].used
= 1;
1094 comparator_list
[fp_num
].fpcr_value
= (breakpoint
->address
& 0x1FFFFFFC) | hilo
| 1;
1095 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1096 comparator_list
[fp_num
].fpcr_value
);
1097 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"",
1099 comparator_list
[fp_num
].fpcr_value
);
1100 if (!cortex_m3
->fpb_enabled
) {
1101 LOG_DEBUG("FPB wasn't enabled, do it now");
1102 target_write_u32(target
, FP_CTRL
, 3);
1104 } else if (breakpoint
->type
== BKPT_SOFT
) {
1107 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1108 * semihosting; don't use that. Otherwise the BKPT
1109 * parameter is arbitrary.
1111 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1112 retval
= target_read_memory(target
,
1113 breakpoint
->address
& 0xFFFFFFFE,
1114 breakpoint
->length
, 1,
1115 breakpoint
->orig_instr
);
1116 if (retval
!= ERROR_OK
)
1118 retval
= target_write_memory(target
,
1119 breakpoint
->address
& 0xFFFFFFFE,
1120 breakpoint
->length
, 1,
1122 if (retval
!= ERROR_OK
)
1124 breakpoint
->set
= true;
1127 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1128 breakpoint
->unique_id
,
1129 (int)(breakpoint
->type
),
1130 breakpoint
->address
,
1137 int cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1140 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1141 struct cortex_m3_fp_comparator
*comparator_list
= cortex_m3
->fp_comparator_list
;
1143 if (!breakpoint
->set
) {
1144 LOG_WARNING("breakpoint not set");
1148 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1149 breakpoint
->unique_id
,
1150 (int)(breakpoint
->type
),
1151 breakpoint
->address
,
1155 if (breakpoint
->type
== BKPT_HARD
) {
1156 int fp_num
= breakpoint
->set
- 1;
1157 if ((fp_num
< 0) || (fp_num
>= cortex_m3
->fp_num_code
)) {
1158 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1161 comparator_list
[fp_num
].used
= 0;
1162 comparator_list
[fp_num
].fpcr_value
= 0;
1163 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1164 comparator_list
[fp_num
].fpcr_value
);
1166 /* restore original instruction (kept in target endianness) */
1167 if (breakpoint
->length
== 4) {
1168 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 4, 1,
1169 breakpoint
->orig_instr
);
1170 if (retval
!= ERROR_OK
)
1173 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 2, 1,
1174 breakpoint
->orig_instr
);
1175 if (retval
!= ERROR_OK
)
1179 breakpoint
->set
= false;
1184 int cortex_m3_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1186 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1188 if (cortex_m3
->auto_bp_type
) {
1189 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1190 #ifdef ARMV7_GDB_HACKS
1191 if (breakpoint
->length
!= 2) {
1192 /* XXX Hack: Replace all breakpoints with length != 2 with
1193 * a hardware breakpoint. */
1194 breakpoint
->type
= BKPT_HARD
;
1195 breakpoint
->length
= 2;
1200 if (breakpoint
->type
!= BKPT_TYPE_BY_ADDR(breakpoint
->address
)) {
1201 if (breakpoint
->type
== BKPT_HARD
) {
1202 LOG_INFO("flash patch comparator requested outside code memory region");
1203 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1206 if (breakpoint
->type
== BKPT_SOFT
) {
1207 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1208 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1212 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_m3
->fp_code_available
< 1)) {
1213 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1214 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1217 if ((breakpoint
->length
!= 2)) {
1218 LOG_INFO("only breakpoints of two bytes length supported");
1219 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1222 if (breakpoint
->type
== BKPT_HARD
)
1223 cortex_m3
->fp_code_available
--;
1225 return cortex_m3_set_breakpoint(target
, breakpoint
);
1228 int cortex_m3_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1230 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1232 /* REVISIT why check? FBP can be updated with core running ... */
1233 if (target
->state
!= TARGET_HALTED
) {
1234 LOG_WARNING("target not halted");
1235 return ERROR_TARGET_NOT_HALTED
;
1238 if (cortex_m3
->auto_bp_type
)
1239 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1241 if (breakpoint
->set
)
1242 cortex_m3_unset_breakpoint(target
, breakpoint
);
1244 if (breakpoint
->type
== BKPT_HARD
)
1245 cortex_m3
->fp_code_available
++;
1250 int cortex_m3_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1253 uint32_t mask
, temp
;
1254 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1256 /* watchpoint params were validated earlier */
1258 temp
= watchpoint
->length
;
1265 /* REVISIT Don't fully trust these "not used" records ... users
1266 * may set up breakpoints by hand, e.g. dual-address data value
1267 * watchpoint using comparator #1; comparator #0 matching cycle
1268 * count; send data trace info through ITM and TPIU; etc
1270 struct cortex_m3_dwt_comparator
*comparator
;
1272 for (comparator
= cortex_m3
->dwt_comparator_list
;
1273 comparator
->used
&& dwt_num
< cortex_m3
->dwt_num_comp
;
1274 comparator
++, dwt_num
++)
1276 if (dwt_num
>= cortex_m3
->dwt_num_comp
) {
1277 LOG_ERROR("Can not find free DWT Comparator");
1280 comparator
->used
= 1;
1281 watchpoint
->set
= dwt_num
+ 1;
1283 comparator
->comp
= watchpoint
->address
;
1284 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1287 comparator
->mask
= mask
;
1288 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1291 switch (watchpoint
->rw
) {
1293 comparator
->function
= 5;
1296 comparator
->function
= 6;
1299 comparator
->function
= 7;
1302 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1303 comparator
->function
);
1305 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1306 watchpoint
->unique_id
, dwt_num
,
1307 (unsigned) comparator
->comp
,
1308 (unsigned) comparator
->mask
,
1309 (unsigned) comparator
->function
);
1313 int cortex_m3_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1315 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1316 struct cortex_m3_dwt_comparator
*comparator
;
1319 if (!watchpoint
->set
) {
1320 LOG_WARNING("watchpoint (wpid: %d) not set",
1321 watchpoint
->unique_id
);
1325 dwt_num
= watchpoint
->set
- 1;
1327 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1328 watchpoint
->unique_id
, dwt_num
,
1329 (unsigned) watchpoint
->address
);
1331 if ((dwt_num
< 0) || (dwt_num
>= cortex_m3
->dwt_num_comp
)) {
1332 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1336 comparator
= cortex_m3
->dwt_comparator_list
+ dwt_num
;
1337 comparator
->used
= 0;
1338 comparator
->function
= 0;
1339 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1340 comparator
->function
);
1342 watchpoint
->set
= false;
1347 int cortex_m3_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1349 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1351 if (cortex_m3
->dwt_comp_available
< 1) {
1352 LOG_DEBUG("no comparators?");
1353 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1356 /* hardware doesn't support data value masking */
1357 if (watchpoint
->mask
!= ~(uint32_t)0) {
1358 LOG_DEBUG("watchpoint value masks not supported");
1359 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1362 /* hardware allows address masks of up to 32K */
1365 for (mask
= 0; mask
< 16; mask
++) {
1366 if ((1u << mask
) == watchpoint
->length
)
1370 LOG_DEBUG("unsupported watchpoint length");
1371 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1373 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1374 LOG_DEBUG("watchpoint address is unaligned");
1375 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1378 /* Caller doesn't seem to be able to describe watching for data
1379 * values of zero; that flags "no value".
1381 * REVISIT This DWT may well be able to watch for specific data
1382 * values. Requires comparator #1 to set DATAVMATCH and match
1383 * the data, and another comparator (DATAVADDR0) matching addr.
1385 if (watchpoint
->value
) {
1386 LOG_DEBUG("data value watchpoint not YET supported");
1387 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1390 cortex_m3
->dwt_comp_available
--;
1391 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1396 int cortex_m3_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1398 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1400 /* REVISIT why check? DWT can be updated with core running ... */
1401 if (target
->state
!= TARGET_HALTED
) {
1402 LOG_WARNING("target not halted");
1403 return ERROR_TARGET_NOT_HALTED
;
1406 if (watchpoint
->set
)
1407 cortex_m3_unset_watchpoint(target
, watchpoint
);
1409 cortex_m3
->dwt_comp_available
++;
1410 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1415 void cortex_m3_enable_watchpoints(struct target
*target
)
1417 struct watchpoint
*watchpoint
= target
->watchpoints
;
1419 /* set any pending watchpoints */
1420 while (watchpoint
) {
1421 if (!watchpoint
->set
)
1422 cortex_m3_set_watchpoint(target
, watchpoint
);
1423 watchpoint
= watchpoint
->next
;
1427 static int cortex_m3_load_core_reg_u32(struct target
*target
,
1428 enum armv7m_regtype type
, uint32_t num
, uint32_t *value
)
1431 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1432 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1434 /* NOTE: we "know" here that the register identifiers used
1435 * in the v7m header match the Cortex-M3 Debug Core Register
1436 * Selector values for R0..R15, xPSR, MSP, and PSP.
1440 /* read a normal core register */
1441 retval
= cortexm3_dap_read_coreregister_u32(swjdp
, value
, num
);
1443 if (retval
!= ERROR_OK
) {
1444 LOG_ERROR("JTAG failure %i", retval
);
1445 return ERROR_JTAG_DEVICE_ERROR
;
1447 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1450 case ARMV7M_PRIMASK
:
1451 case ARMV7M_BASEPRI
:
1452 case ARMV7M_FAULTMASK
:
1453 case ARMV7M_CONTROL
:
1454 /* Cortex-M3 packages these four registers as bitfields
1455 * in one Debug Core register. So say r0 and r2 docs;
1456 * it was removed from r1 docs, but still works.
1458 cortexm3_dap_read_coreregister_u32(swjdp
, value
, 20);
1461 case ARMV7M_PRIMASK
:
1462 *value
= buf_get_u32((uint8_t *)value
, 0, 1);
1465 case ARMV7M_BASEPRI
:
1466 *value
= buf_get_u32((uint8_t *)value
, 8, 8);
1469 case ARMV7M_FAULTMASK
:
1470 *value
= buf_get_u32((uint8_t *)value
, 16, 1);
1473 case ARMV7M_CONTROL
:
1474 *value
= buf_get_u32((uint8_t *)value
, 24, 2);
1478 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1482 return ERROR_COMMAND_SYNTAX_ERROR
;
1488 static int cortex_m3_store_core_reg_u32(struct target
*target
,
1489 enum armv7m_regtype type
, uint32_t num
, uint32_t value
)
1493 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1494 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1496 #ifdef ARMV7_GDB_HACKS
1497 /* If the LR register is being modified, make sure it will put us
1498 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1499 * hack to deal with the fact that gdb will sometimes "forge"
1500 * return addresses, and doesn't set the LSB correctly (i.e., when
1501 * printing expressions containing function calls, it sets LR = 0.)
1502 * Valid exception return codes have bit 0 set too.
1504 if (num
== ARMV7M_R14
)
1508 /* NOTE: we "know" here that the register identifiers used
1509 * in the v7m header match the Cortex-M3 Debug Core Register
1510 * Selector values for R0..R15, xPSR, MSP, and PSP.
1514 retval
= cortexm3_dap_write_coreregister_u32(swjdp
, value
, num
);
1515 if (retval
!= ERROR_OK
) {
1518 LOG_ERROR("JTAG failure");
1519 r
= armv7m
->core_cache
->reg_list
+ num
;
1520 r
->dirty
= r
->valid
;
1521 return ERROR_JTAG_DEVICE_ERROR
;
1523 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1526 case ARMV7M_PRIMASK
:
1527 case ARMV7M_BASEPRI
:
1528 case ARMV7M_FAULTMASK
:
1529 case ARMV7M_CONTROL
:
1530 /* Cortex-M3 packages these four registers as bitfields
1531 * in one Debug Core register. So say r0 and r2 docs;
1532 * it was removed from r1 docs, but still works.
1534 cortexm3_dap_read_coreregister_u32(swjdp
, ®
, 20);
1537 case ARMV7M_PRIMASK
:
1538 buf_set_u32((uint8_t *)®
, 0, 1, value
);
1541 case ARMV7M_BASEPRI
:
1542 buf_set_u32((uint8_t *)®
, 8, 8, value
);
1545 case ARMV7M_FAULTMASK
:
1546 buf_set_u32((uint8_t *)®
, 16, 1, value
);
1549 case ARMV7M_CONTROL
:
1550 buf_set_u32((uint8_t *)®
, 24, 2, value
);
1554 cortexm3_dap_write_coreregister_u32(swjdp
, reg
, 20);
1556 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1560 return ERROR_COMMAND_SYNTAX_ERROR
;
1566 static int cortex_m3_read_memory(struct target
*target
, uint32_t address
,
1567 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1569 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1570 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1571 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1573 if (armv7m
->arm
.is_armv6m
) {
1574 /* armv6m does not handle unaligned memory access */
1575 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1576 return ERROR_TARGET_UNALIGNED_ACCESS
;
1579 /* cortex_m3 handles unaligned memory access */
1580 if (count
&& buffer
) {
1583 retval
= mem_ap_read_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1586 retval
= mem_ap_read_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1589 retval
= mem_ap_read_buf_u8(swjdp
, buffer
, count
, address
);
1597 static int cortex_m3_write_memory(struct target
*target
, uint32_t address
,
1598 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1600 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1601 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1602 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1604 if (armv7m
->arm
.is_armv6m
) {
1605 /* armv6m does not handle unaligned memory access */
1606 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1607 return ERROR_TARGET_UNALIGNED_ACCESS
;
1610 if (count
&& buffer
) {
1613 retval
= mem_ap_write_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1616 retval
= mem_ap_write_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1619 retval
= mem_ap_write_buf_u8(swjdp
, buffer
, count
, address
);
1627 static int cortex_m3_bulk_write_memory(struct target
*target
, uint32_t address
,
1628 uint32_t count
, const uint8_t *buffer
)
1630 return cortex_m3_write_memory(target
, address
, 4, count
, buffer
);
1633 static int cortex_m3_init_target(struct command_context
*cmd_ctx
,
1634 struct target
*target
)
1636 armv7m_build_reg_cache(target
);
1640 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1641 * on r/w if the core is not running, and clear on resume or reset ... or
1642 * at least, in a post_restore_context() method.
1645 struct dwt_reg_state
{
1646 struct target
*target
;
1648 uint32_t value
; /* scratch/cache */
1651 static int cortex_m3_dwt_get_reg(struct reg
*reg
)
1653 struct dwt_reg_state
*state
= reg
->arch_info
;
1655 return target_read_u32(state
->target
, state
->addr
, &state
->value
);
1658 static int cortex_m3_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1660 struct dwt_reg_state
*state
= reg
->arch_info
;
1662 return target_write_u32(state
->target
, state
->addr
,
1663 buf_get_u32(buf
, 0, reg
->size
));
1672 static struct dwt_reg dwt_base_regs
[] = {
1673 { DWT_CTRL
, "dwt_ctrl", 32, },
1674 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1675 * increments while the core is asleep.
1677 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1678 /* plus some 8 bit counters, useful for profiling with TPIU */
1681 static struct dwt_reg dwt_comp
[] = {
1682 #define DWT_COMPARATOR(i) \
1683 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1684 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1685 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1690 #undef DWT_COMPARATOR
1693 static const struct reg_arch_type dwt_reg_type
= {
1694 .get
= cortex_m3_dwt_get_reg
,
1695 .set
= cortex_m3_dwt_set_reg
,
1698 static void cortex_m3_dwt_addreg(struct target
*t
, struct reg
*r
, struct dwt_reg
*d
)
1700 struct dwt_reg_state
*state
;
1702 state
= calloc(1, sizeof *state
);
1705 state
->addr
= d
->addr
;
1710 r
->value
= &state
->value
;
1711 r
->arch_info
= state
;
1712 r
->type
= &dwt_reg_type
;
1715 void cortex_m3_dwt_setup(struct cortex_m3_common
*cm3
, struct target
*target
)
1718 struct reg_cache
*cache
;
1719 struct cortex_m3_dwt_comparator
*comparator
;
1722 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1724 LOG_DEBUG("no DWT");
1728 cm3
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1729 cm3
->dwt_comp_available
= cm3
->dwt_num_comp
;
1730 cm3
->dwt_comparator_list
= calloc(cm3
->dwt_num_comp
,
1731 sizeof(struct cortex_m3_dwt_comparator
));
1732 if (!cm3
->dwt_comparator_list
) {
1734 cm3
->dwt_num_comp
= 0;
1735 LOG_ERROR("out of mem");
1739 cache
= calloc(1, sizeof *cache
);
1742 free(cm3
->dwt_comparator_list
);
1745 cache
->name
= "cortex-m3 dwt registers";
1746 cache
->num_regs
= 2 + cm3
->dwt_num_comp
* 3;
1747 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
1748 if (!cache
->reg_list
) {
1753 for (reg
= 0; reg
< 2; reg
++)
1754 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1755 dwt_base_regs
+ reg
);
1757 comparator
= cm3
->dwt_comparator_list
;
1758 for (i
= 0; i
< cm3
->dwt_num_comp
; i
++, comparator
++) {
1761 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
1762 for (j
= 0; j
< 3; j
++, reg
++)
1763 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1764 dwt_comp
+ 3 * i
+ j
);
1767 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
1768 cm3
->dwt_cache
= cache
;
1770 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
1771 dwtcr
, cm3
->dwt_num_comp
,
1772 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
1774 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1775 * implement single-address data value watchpoints ... so we
1776 * won't need to check it later, when asked to set one up.
1780 #define MVFR0 0xe000ef40
1781 #define MVFR1 0xe000ef44
1783 #define MVFR0_DEFAULT_M4 0x10110021
1784 #define MVFR1_DEFAULT_M4 0x11000011
1786 int cortex_m3_examine(struct target
*target
)
1789 uint32_t cpuid
, fpcr
, mvfr0
, mvfr1
;
1791 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1792 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
1793 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1795 /* stlink shares the examine handler but does not support
1797 if (!armv7m
->stlink
) {
1798 retval
= ahbap_debugport_init(swjdp
);
1799 if (retval
!= ERROR_OK
)
1803 if (!target_was_examined(target
)) {
1804 target_set_examined(target
);
1806 /* Read from Device Identification Registers */
1807 retval
= target_read_u32(target
, CPUID
, &cpuid
);
1808 if (retval
!= ERROR_OK
)
1812 i
= (cpuid
>> 4) & 0xf;
1814 LOG_DEBUG("Cortex-M%d r%" PRId8
"p%" PRId8
" processor detected",
1815 i
, (uint8_t)((cpuid
>> 20) & 0xf), (uint8_t)((cpuid
>> 0) & 0xf));
1816 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
1818 /* test for floating point feature on cortex-m4 */
1820 target_read_u32(target
, MVFR0
, &mvfr0
);
1821 target_read_u32(target
, MVFR1
, &mvfr1
);
1823 if ((mvfr0
== MVFR0_DEFAULT_M4
) && (mvfr1
== MVFR1_DEFAULT_M4
)) {
1824 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i
);
1825 armv7m
->fp_feature
= FPv4_SP
;
1827 } else if (i
== 0) {
1828 /* Cortex-M0 does not support unaligned memory access */
1829 armv7m
->arm
.is_armv6m
= true;
1832 /* NOTE: FPB and DWT are both optional. */
1835 target_read_u32(target
, FP_CTRL
, &fpcr
);
1836 cortex_m3
->auto_bp_type
= 1;
1837 cortex_m3
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF); /* bits
1841 cortex_m3
->fp_num_lit
= (fpcr
>> 8) & 0xF;
1842 cortex_m3
->fp_code_available
= cortex_m3
->fp_num_code
;
1843 cortex_m3
->fp_comparator_list
= calloc(
1844 cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
,
1845 sizeof(struct cortex_m3_fp_comparator
));
1846 cortex_m3
->fpb_enabled
= fpcr
& 1;
1847 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++) {
1848 cortex_m3
->fp_comparator_list
[i
].type
=
1849 (i
< cortex_m3
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
1850 cortex_m3
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
1852 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i",
1854 cortex_m3
->fp_num_code
,
1855 cortex_m3
->fp_num_lit
);
1858 cortex_m3_dwt_setup(cortex_m3
, target
);
1860 /* These hardware breakpoints only work for code in flash! */
1861 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1862 target_name(target
),
1863 cortex_m3
->fp_num_code
,
1864 cortex_m3
->dwt_num_comp
);
1870 static int cortex_m3_dcc_read(struct adiv5_dap
*swjdp
, uint8_t *value
, uint8_t *ctrl
)
1875 mem_ap_read_buf_u16(swjdp
, (uint8_t *)&dcrdr
, 1, DCB_DCRDR
);
1876 *ctrl
= (uint8_t)dcrdr
;
1877 *value
= (uint8_t)(dcrdr
>> 8);
1879 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
1881 /* write ack back to software dcc register
1882 * signify we have read data */
1883 if (dcrdr
& (1 << 0)) {
1885 retval
= mem_ap_write_buf_u16(swjdp
, (uint8_t *)&dcrdr
, 1, DCB_DCRDR
);
1886 if (retval
!= ERROR_OK
)
1893 static int cortex_m3_target_request_data(struct target
*target
,
1894 uint32_t size
, uint8_t *buffer
)
1896 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1897 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1902 for (i
= 0; i
< (size
* 4); i
++) {
1903 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1910 static int cortex_m3_handle_target_request(void *priv
)
1912 struct target
*target
= priv
;
1913 if (!target_was_examined(target
))
1915 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1916 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1918 if (!target
->dbg_msg_enabled
)
1921 if (target
->state
== TARGET_RUNNING
) {
1925 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1927 /* check if we have data */
1928 if (ctrl
& (1 << 0)) {
1931 /* we assume target is quick enough */
1933 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1934 request
|= (data
<< 8);
1935 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1936 request
|= (data
<< 16);
1937 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1938 request
|= (data
<< 24);
1939 target_request(target
, request
);
1946 static int cortex_m3_init_arch_info(struct target
*target
,
1947 struct cortex_m3_common
*cortex_m3
, struct jtag_tap
*tap
)
1950 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
1952 armv7m_init_arch_info(target
, armv7m
);
1954 /* prepare JTAG information for the new target */
1955 cortex_m3
->jtag_info
.tap
= tap
;
1956 cortex_m3
->jtag_info
.scann_size
= 4;
1958 /* default reset mode is to use srst if fitted
1959 * if not it will use CORTEX_M3_RESET_VECTRESET */
1960 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_VECTRESET
;
1962 armv7m
->arm
.dap
= &armv7m
->dap
;
1964 /* Leave (only) generic DAP stuff for debugport_init(); */
1965 armv7m
->dap
.jtag_info
= &cortex_m3
->jtag_info
;
1966 armv7m
->dap
.memaccess_tck
= 8;
1967 /* Cortex-M3 has 4096 bytes autoincrement range */
1968 armv7m
->dap
.tar_autoincr_block
= (1 << 12);
1970 /* register arch-specific functions */
1971 armv7m
->examine_debug_reason
= cortex_m3_examine_debug_reason
;
1973 armv7m
->post_debug_entry
= NULL
;
1975 armv7m
->pre_restore_context
= NULL
;
1977 armv7m
->load_core_reg_u32
= cortex_m3_load_core_reg_u32
;
1978 armv7m
->store_core_reg_u32
= cortex_m3_store_core_reg_u32
;
1980 target_register_timer_callback(cortex_m3_handle_target_request
, 1, 1, target
);
1982 retval
= arm_jtag_setup_connection(&cortex_m3
->jtag_info
);
1983 if (retval
!= ERROR_OK
)
1989 static int cortex_m3_target_create(struct target
*target
, Jim_Interp
*interp
)
1991 struct cortex_m3_common
*cortex_m3
= calloc(1, sizeof(struct cortex_m3_common
));
1993 cortex_m3
->common_magic
= CORTEX_M3_COMMON_MAGIC
;
1994 cortex_m3_init_arch_info(target
, cortex_m3
, target
->tap
);
1999 /*--------------------------------------------------------------------------*/
2001 static int cortex_m3_verify_pointer(struct command_context
*cmd_ctx
,
2002 struct cortex_m3_common
*cm3
)
2004 if (cm3
->common_magic
!= CORTEX_M3_COMMON_MAGIC
) {
2005 command_print(cmd_ctx
, "target is not a Cortex-M3");
2006 return ERROR_TARGET_INVALID
;
2012 * Only stuff below this line should need to verify that its target
2013 * is a Cortex-M3. Everything else should have indirected through the
2014 * cortexm3_target structure, which is only used with CM3 targets.
2017 static const struct {
2021 { "hard_err", VC_HARDERR
, },
2022 { "int_err", VC_INTERR
, },
2023 { "bus_err", VC_BUSERR
, },
2024 { "state_err", VC_STATERR
, },
2025 { "chk_err", VC_CHKERR
, },
2026 { "nocp_err", VC_NOCPERR
, },
2027 { "mm_err", VC_MMERR
, },
2028 { "reset", VC_CORERESET
, },
2031 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command
)
2033 struct target
*target
= get_current_target(CMD_CTX
);
2034 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2035 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
2036 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
2040 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2041 if (retval
!= ERROR_OK
)
2044 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2045 if (retval
!= ERROR_OK
)
2051 if (CMD_ARGC
== 1) {
2052 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2053 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2054 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2055 | VC_MMERR
| VC_CORERESET
;
2057 } else if (strcmp(CMD_ARGV
[0], "none") == 0)
2060 while (CMD_ARGC
-- > 0) {
2062 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2063 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2065 catch |= vec_ids
[i
].mask
;
2068 if (i
== ARRAY_SIZE(vec_ids
)) {
2069 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2070 return ERROR_COMMAND_SYNTAX_ERROR
;
2074 /* For now, armv7m->demcr only stores vector catch flags. */
2075 armv7m
->demcr
= catch;
2080 /* write, but don't assume it stuck (why not??) */
2081 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, demcr
);
2082 if (retval
!= ERROR_OK
)
2084 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2085 if (retval
!= ERROR_OK
)
2088 /* FIXME be sure to clear DEMCR on clean server shutdown.
2089 * Otherwise the vector catch hardware could fire when there's
2090 * no debugger hooked up, causing much confusion...
2094 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2095 command_print(CMD_CTX
, "%9s: %s", vec_ids
[i
].name
,
2096 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2102 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command
)
2104 struct target
*target
= get_current_target(CMD_CTX
);
2105 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2108 static const Jim_Nvp nvp_maskisr_modes
[] = {
2109 { .name
= "auto", .value
= CORTEX_M3_ISRMASK_AUTO
},
2110 { .name
= "off", .value
= CORTEX_M3_ISRMASK_OFF
},
2111 { .name
= "on", .value
= CORTEX_M3_ISRMASK_ON
},
2112 { .name
= NULL
, .value
= -1 },
2117 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2118 if (retval
!= ERROR_OK
)
2121 if (target
->state
!= TARGET_HALTED
) {
2122 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
2127 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
2128 if (n
->name
== NULL
)
2129 return ERROR_COMMAND_SYNTAX_ERROR
;
2130 cortex_m3
->isrmasking_mode
= n
->value
;
2133 if (cortex_m3
->isrmasking_mode
== CORTEX_M3_ISRMASK_ON
)
2134 cortex_m3_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
2136 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
2139 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_m3
->isrmasking_mode
);
2140 command_print(CMD_CTX
, "cortex_m3 interrupt mask %s", n
->name
);
2145 COMMAND_HANDLER(handle_cortex_m3_reset_config_command
)
2147 struct target
*target
= get_current_target(CMD_CTX
);
2148 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2152 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2153 if (retval
!= ERROR_OK
)
2157 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2158 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_SYSRESETREQ
;
2159 else if (strcmp(*CMD_ARGV
, "vectreset") == 0)
2160 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_VECTRESET
;
2163 switch (cortex_m3
->soft_reset_config
) {
2164 case CORTEX_M3_RESET_SYSRESETREQ
:
2165 reset_config
= "sysresetreq";
2168 case CORTEX_M3_RESET_VECTRESET
:
2169 reset_config
= "vectreset";
2173 reset_config
= "unknown";
2177 command_print(CMD_CTX
, "cortex_m3 reset_config %s", reset_config
);
2182 static const struct command_registration cortex_m3_exec_command_handlers
[] = {
2185 .handler
= handle_cortex_m3_mask_interrupts_command
,
2186 .mode
= COMMAND_EXEC
,
2187 .help
= "mask cortex_m3 interrupts",
2188 .usage
= "['auto'|'on'|'off']",
2191 .name
= "vector_catch",
2192 .handler
= handle_cortex_m3_vector_catch_command
,
2193 .mode
= COMMAND_EXEC
,
2194 .help
= "configure hardware vectors to trigger debug entry",
2195 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2198 .name
= "reset_config",
2199 .handler
= handle_cortex_m3_reset_config_command
,
2200 .mode
= COMMAND_ANY
,
2201 .help
= "configure software reset handling",
2202 .usage
= "['srst'|'sysresetreq'|'vectreset']",
2204 COMMAND_REGISTRATION_DONE
2206 static const struct command_registration cortex_m3_command_handlers
[] = {
2208 .chain
= armv7m_command_handlers
,
2211 .name
= "cortex_m3",
2212 .mode
= COMMAND_EXEC
,
2213 .help
= "Cortex-M3 command group",
2215 .chain
= cortex_m3_exec_command_handlers
,
2217 COMMAND_REGISTRATION_DONE
2220 struct target_type cortexm3_target
= {
2221 .name
= "cortex_m3",
2223 .poll
= cortex_m3_poll
,
2224 .arch_state
= armv7m_arch_state
,
2226 .target_request_data
= cortex_m3_target_request_data
,
2228 .halt
= cortex_m3_halt
,
2229 .resume
= cortex_m3_resume
,
2230 .step
= cortex_m3_step
,
2232 .assert_reset
= cortex_m3_assert_reset
,
2233 .deassert_reset
= cortex_m3_deassert_reset
,
2234 .soft_reset_halt
= cortex_m3_soft_reset_halt
,
2236 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2238 .read_memory
= cortex_m3_read_memory
,
2239 .write_memory
= cortex_m3_write_memory
,
2240 .bulk_write_memory
= cortex_m3_bulk_write_memory
,
2241 .checksum_memory
= armv7m_checksum_memory
,
2242 .blank_check_memory
= armv7m_blank_check_memory
,
2244 .run_algorithm
= armv7m_run_algorithm
,
2245 .start_algorithm
= armv7m_start_algorithm
,
2246 .wait_algorithm
= armv7m_wait_algorithm
,
2248 .add_breakpoint
= cortex_m3_add_breakpoint
,
2249 .remove_breakpoint
= cortex_m3_remove_breakpoint
,
2250 .add_watchpoint
= cortex_m3_add_watchpoint
,
2251 .remove_watchpoint
= cortex_m3_remove_watchpoint
,
2253 .commands
= cortex_m3_command_handlers
,
2254 .target_create
= cortex_m3_target_create
,
2255 .init_target
= cortex_m3_init_target
,
2256 .examine
= cortex_m3_examine
,
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