1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
29 ***************************************************************************/
34 #include "breakpoints.h"
36 #include "target_request.h"
37 #include "target_type.h"
38 #include "arm_disassembler.h"
40 #include "arm_opcodes.h"
41 #include "arm_semihosting.h"
42 #include <helper/time_support.h>
44 /* NOTE: most of this should work fine for the Cortex-M1 and
45 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
46 * Some differences: M0/M1 doesn't have FBP remapping or the
47 * DWT tracing/profiling support. (So the cycle counter will
48 * not be usable; the other stuff isn't currently used here.)
50 * Although there are some workarounds for errata seen only in r0p0
51 * silicon, such old parts are hard to find and thus not much tested
56 * Returns the type of a break point required by address location
58 #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
61 /* forward declarations */
62 static int cortex_m3_store_core_reg_u32(struct target
*target
,
63 enum armv7m_regtype type
, uint32_t num
, uint32_t value
);
65 static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap
*swjdp
,
66 uint32_t *value
, int regnum
)
71 /* because the DCB_DCRDR is used for the emulated dcc channel
72 * we have to save/restore the DCB_DCRDR when used */
74 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
75 if (retval
!= ERROR_OK
)
78 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
79 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
80 if (retval
!= ERROR_OK
)
82 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
);
83 if (retval
!= ERROR_OK
)
86 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
87 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
88 if (retval
!= ERROR_OK
)
90 retval
= dap_queue_ap_read(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
91 if (retval
!= ERROR_OK
)
94 retval
= dap_run(swjdp
);
95 if (retval
!= ERROR_OK
)
98 /* restore DCB_DCRDR - this needs to be in a seperate
99 * transaction otherwise the emulated DCC channel breaks */
100 if (retval
== ERROR_OK
)
101 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
106 static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap
*swjdp
,
107 uint32_t value
, int regnum
)
112 /* because the DCB_DCRDR is used for the emulated dcc channel
113 * we have to save/restore the DCB_DCRDR when used */
115 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
116 if (retval
!= ERROR_OK
)
119 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
120 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
121 if (retval
!= ERROR_OK
)
123 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
124 if (retval
!= ERROR_OK
)
127 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
128 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
129 if (retval
!= ERROR_OK
)
131 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
| DCRSR_WnR
);
132 if (retval
!= ERROR_OK
)
135 retval
= dap_run(swjdp
);
136 if (retval
!= ERROR_OK
)
139 /* restore DCB_DCRDR - this needs to be in a seperate
140 * transaction otherwise the emulated DCC channel breaks */
141 if (retval
== ERROR_OK
)
142 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
147 static int cortex_m3_write_debug_halt_mask(struct target
*target
,
148 uint32_t mask_on
, uint32_t mask_off
)
150 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
151 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
153 /* mask off status bits */
154 cortex_m3
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
155 /* create new register mask */
156 cortex_m3
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
158 return mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, cortex_m3
->dcb_dhcsr
);
161 static int cortex_m3_clear_halt(struct target
*target
)
163 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
164 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
167 /* clear step if any */
168 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
170 /* Read Debug Fault Status Register */
171 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m3
->nvic_dfsr
);
172 if (retval
!= ERROR_OK
)
175 /* Clear Debug Fault Status */
176 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_DFSR
, cortex_m3
->nvic_dfsr
);
177 if (retval
!= ERROR_OK
)
179 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m3
->nvic_dfsr
);
184 static int cortex_m3_single_step_core(struct target
*target
)
186 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
187 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
191 /* backup dhcsr reg */
192 dhcsr_save
= cortex_m3
->dcb_dhcsr
;
194 /* Mask interrupts before clearing halt, if done already. This avoids
195 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
196 * HALT can put the core into an unknown state.
198 if (!(cortex_m3
->dcb_dhcsr
& C_MASKINTS
))
200 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
201 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
202 if (retval
!= ERROR_OK
)
205 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
206 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
207 if (retval
!= ERROR_OK
)
211 /* restore dhcsr reg */
212 cortex_m3
->dcb_dhcsr
= dhcsr_save
;
213 cortex_m3_clear_halt(target
);
218 static int cortex_m3_endreset_event(struct target
*target
)
223 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
224 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
225 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
226 struct cortex_m3_fp_comparator
*fp_list
= cortex_m3
->fp_comparator_list
;
227 struct cortex_m3_dwt_comparator
*dwt_list
= cortex_m3
->dwt_comparator_list
;
229 /* REVISIT The four debug monitor bits are currently ignored... */
230 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &dcb_demcr
);
231 if (retval
!= ERROR_OK
)
233 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"",dcb_demcr
);
235 /* this register is used for emulated dcc channel */
236 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
237 if (retval
!= ERROR_OK
)
240 /* Enable debug requests */
241 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
242 if (retval
!= ERROR_OK
)
244 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
246 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
247 if (retval
!= ERROR_OK
)
251 /* clear any interrupt masking */
252 cortex_m3_write_debug_halt_mask(target
, 0, C_MASKINTS
);
254 /* Enable features controlled by ITM and DWT blocks, and catch only
255 * the vectors we were told to pay attention to.
257 * Target firmware is responsible for all fault handling policy
258 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
259 * or manual updates to the NVIC SHCSR and CCR registers.
261 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
262 if (retval
!= ERROR_OK
)
265 /* Paranoia: evidently some (early?) chips don't preserve all the
266 * debug state (including FBP, DWT, etc) across reset...
270 retval
= target_write_u32(target
, FP_CTRL
, 3);
271 if (retval
!= ERROR_OK
)
274 cortex_m3
->fpb_enabled
= 1;
276 /* Restore FPB registers */
277 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
279 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
280 if (retval
!= ERROR_OK
)
284 /* Restore DWT registers */
285 for (i
= 0; i
< cortex_m3
->dwt_num_comp
; i
++)
287 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
289 if (retval
!= ERROR_OK
)
291 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
293 if (retval
!= ERROR_OK
)
295 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
296 dwt_list
[i
].function
);
297 if (retval
!= ERROR_OK
)
300 retval
= dap_run(swjdp
);
301 if (retval
!= ERROR_OK
)
304 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
306 /* make sure we have latest dhcsr flags */
307 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
312 static int cortex_m3_examine_debug_reason(struct target
*target
)
314 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
316 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
317 /* only check the debug reason if we don't know it already */
319 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
320 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
322 if (cortex_m3
->nvic_dfsr
& DFSR_BKPT
)
324 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
325 if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
326 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
328 else if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
329 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
330 else if (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
)
331 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
332 else /* EXTERNAL, HALTED */
333 target
->debug_reason
= DBG_REASON_UNDEFINED
;
339 static int cortex_m3_examine_exception_reason(struct target
*target
)
341 uint32_t shcsr
= 0, except_sr
= 0, cfsr
= -1, except_ar
= -1;
342 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
343 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
346 retval
= mem_ap_read_u32(swjdp
, NVIC_SHCSR
, &shcsr
);
347 if (retval
!= ERROR_OK
)
349 switch (armv7m
->exception_number
)
353 case 3: /* Hard Fault */
354 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_HFSR
, &except_sr
);
355 if (retval
!= ERROR_OK
)
357 if (except_sr
& 0x40000000)
359 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &cfsr
);
360 if (retval
!= ERROR_OK
)
364 case 4: /* Memory Management */
365 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
366 if (retval
!= ERROR_OK
)
368 retval
= mem_ap_read_u32(swjdp
, NVIC_MMFAR
, &except_ar
);
369 if (retval
!= ERROR_OK
)
372 case 5: /* Bus Fault */
373 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
374 if (retval
!= ERROR_OK
)
376 retval
= mem_ap_read_u32(swjdp
, NVIC_BFAR
, &except_ar
);
377 if (retval
!= ERROR_OK
)
380 case 6: /* Usage Fault */
381 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
382 if (retval
!= ERROR_OK
)
385 case 11: /* SVCall */
387 case 12: /* Debug Monitor */
388 retval
= mem_ap_read_u32(swjdp
, NVIC_DFSR
, &except_sr
);
389 if (retval
!= ERROR_OK
)
392 case 14: /* PendSV */
394 case 15: /* SysTick */
400 retval
= dap_run(swjdp
);
401 if (retval
== ERROR_OK
)
402 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
403 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
404 armv7m_exception_string(armv7m
->exception_number
),
405 shcsr
, except_sr
, cfsr
, except_ar
);
409 /* PSP is used in some thread modes */
410 static const int armv7m_psp_reg_map
[17] = {
411 ARMV7M_R0
, ARMV7M_R1
, ARMV7M_R2
, ARMV7M_R3
,
412 ARMV7M_R4
, ARMV7M_R5
, ARMV7M_R6
, ARMV7M_R7
,
413 ARMV7M_R8
, ARMV7M_R9
, ARMV7M_R10
, ARMV7M_R11
,
414 ARMV7M_R12
, ARMV7M_PSP
, ARMV7M_R14
, ARMV7M_PC
,
418 /* MSP is used in handler and some thread modes */
419 static const int armv7m_msp_reg_map
[17] = {
420 ARMV7M_R0
, ARMV7M_R1
, ARMV7M_R2
, ARMV7M_R3
,
421 ARMV7M_R4
, ARMV7M_R5
, ARMV7M_R6
, ARMV7M_R7
,
422 ARMV7M_R8
, ARMV7M_R9
, ARMV7M_R10
, ARMV7M_R11
,
423 ARMV7M_R12
, ARMV7M_MSP
, ARMV7M_R14
, ARMV7M_PC
,
427 static int cortex_m3_debug_entry(struct target
*target
)
432 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
433 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
434 struct arm
*arm
= &armv7m
->arm
;
435 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
440 cortex_m3_clear_halt(target
);
441 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
442 if (retval
!= ERROR_OK
)
445 if ((retval
= armv7m
->examine_debug_reason(target
)) != ERROR_OK
)
448 /* Examine target state and mode */
449 /* First load register acessible through core debug port*/
450 int num_regs
= armv7m
->core_cache
->num_regs
;
452 for (i
= 0; i
< num_regs
; i
++)
454 if (!armv7m
->core_cache
->reg_list
[i
].valid
)
455 armv7m
->read_core_reg(target
, i
);
458 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_xPSR
;
459 xPSR
= buf_get_u32(r
->value
, 0, 32);
461 #ifdef ARMV7_GDB_HACKS
462 /* FIXME this breaks on scan chains with more than one Cortex-M3.
463 * Instead, each CM3 should have its own dummy value...
465 /* copy real xpsr reg for gdb, setting thumb bit */
466 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 0, 32, xPSR
);
467 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 5, 1, 1);
468 armv7m_gdb_dummy_cpsr_reg
.valid
= r
->valid
;
469 armv7m_gdb_dummy_cpsr_reg
.dirty
= r
->dirty
;
472 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
476 cortex_m3_store_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 16, xPSR
&~ 0xff);
479 /* Are we in an exception handler */
482 armv7m
->core_mode
= ARMV7M_MODE_HANDLER
;
483 armv7m
->exception_number
= (xPSR
& 0x1FF);
485 arm
->core_mode
= ARM_MODE_HANDLER
;
486 arm
->map
= armv7m_msp_reg_map
;
490 unsigned control
= buf_get_u32(armv7m
->core_cache
491 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 2);
493 /* is this thread privileged? */
494 armv7m
->core_mode
= control
& 1;
495 arm
->core_mode
= armv7m
->core_mode
496 ? ARM_MODE_USER_THREAD
499 /* which stack is it using? */
501 arm
->map
= armv7m_psp_reg_map
;
503 arm
->map
= armv7m_msp_reg_map
;
505 armv7m
->exception_number
= 0;
508 if (armv7m
->exception_number
)
510 cortex_m3_examine_exception_reason(target
);
513 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
514 armv7m_mode_strings
[armv7m
->core_mode
],
515 *(uint32_t*)(arm
->pc
->value
),
516 target_state_name(target
));
518 if (armv7m
->post_debug_entry
)
520 retval
= armv7m
->post_debug_entry(target
);
521 if (retval
!= ERROR_OK
)
528 static int cortex_m3_poll(struct target
*target
)
530 int detected_failure
= ERROR_OK
;
531 int retval
= ERROR_OK
;
532 enum target_state prev_target_state
= target
->state
;
533 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
534 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
536 /* Read from Debug Halting Control and Status Register */
537 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
538 if (retval
!= ERROR_OK
)
540 target
->state
= TARGET_UNKNOWN
;
544 /* Recover from lockup. See ARMv7-M architecture spec,
545 * section B1.5.15 "Unrecoverable exception cases".
547 if (cortex_m3
->dcb_dhcsr
& S_LOCKUP
) {
548 LOG_ERROR("%s -- clearing lockup after double fault",
549 target_name(target
));
550 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
551 target
->debug_reason
= DBG_REASON_DBGRQ
;
553 /* We have to execute the rest (the "finally" equivalent, but
554 * still throw this exception again).
556 detected_failure
= ERROR_FAIL
;
558 /* refresh status bits */
559 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
560 if (retval
!= ERROR_OK
)
564 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
566 /* check if still in reset */
567 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
568 if (retval
!= ERROR_OK
)
571 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
573 target
->state
= TARGET_RESET
;
578 if (target
->state
== TARGET_RESET
)
580 /* Cannot switch context while running so endreset is
581 * called with target->state == TARGET_RESET
583 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
584 cortex_m3
->dcb_dhcsr
);
585 cortex_m3_endreset_event(target
);
586 target
->state
= TARGET_RUNNING
;
587 prev_target_state
= TARGET_RUNNING
;
590 if (cortex_m3
->dcb_dhcsr
& S_HALT
)
592 target
->state
= TARGET_HALTED
;
594 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
))
596 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
599 if (arm_semihosting(target
, &retval
) != 0)
602 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
604 if (prev_target_state
== TARGET_DEBUG_RUNNING
)
607 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
610 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
614 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
615 * How best to model low power modes?
618 if (target
->state
== TARGET_UNKNOWN
)
620 /* check if processor is retiring instructions */
621 if (cortex_m3
->dcb_dhcsr
& S_RETIRE_ST
)
623 target
->state
= TARGET_RUNNING
;
628 /* Did we detect a failure condition that we cleared? */
629 if (detected_failure
!= ERROR_OK
)
630 retval
= detected_failure
;
634 static int cortex_m3_halt(struct target
*target
)
636 LOG_DEBUG("target->state: %s",
637 target_state_name(target
));
639 if (target
->state
== TARGET_HALTED
)
641 LOG_DEBUG("target was already halted");
645 if (target
->state
== TARGET_UNKNOWN
)
647 LOG_WARNING("target was in unknown state when halt was requested");
650 if (target
->state
== TARGET_RESET
)
652 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst())
654 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
655 return ERROR_TARGET_FAILURE
;
659 /* we came here in a reset_halt or reset_init sequence
660 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
662 target
->debug_reason
= DBG_REASON_DBGRQ
;
668 /* Write to Debug Halting Control and Status Register */
669 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
671 target
->debug_reason
= DBG_REASON_DBGRQ
;
676 static int cortex_m3_soft_reset_halt(struct target
*target
)
678 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
679 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
680 uint32_t dcb_dhcsr
= 0;
681 int retval
, timeout
= 0;
683 /* Enter debug state on reset; restore DEMCR in endreset_event() */
684 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
,
685 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
686 if (retval
!= ERROR_OK
)
689 /* Request a core-only reset */
690 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
691 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
692 if (retval
!= ERROR_OK
)
694 target
->state
= TARGET_RESET
;
696 /* registers are now invalid */
697 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
699 while (timeout
< 100)
701 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &dcb_dhcsr
);
702 if (retval
== ERROR_OK
)
704 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
,
705 &cortex_m3
->nvic_dfsr
);
706 if (retval
!= ERROR_OK
)
708 if ((dcb_dhcsr
& S_HALT
)
709 && (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
))
711 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
713 (unsigned) dcb_dhcsr
,
714 (unsigned) cortex_m3
->nvic_dfsr
);
715 cortex_m3_poll(target
);
716 /* FIXME restore user's vector catch config */
720 LOG_DEBUG("waiting for system reset-halt, "
721 "DHCSR 0x%08x, %d ms",
722 (unsigned) dcb_dhcsr
, timeout
);
731 static void cortex_m3_enable_breakpoints(struct target
*target
)
733 struct breakpoint
*breakpoint
= target
->breakpoints
;
735 /* set any pending breakpoints */
738 if (!breakpoint
->set
)
739 cortex_m3_set_breakpoint(target
, breakpoint
);
740 breakpoint
= breakpoint
->next
;
744 static int cortex_m3_resume(struct target
*target
, int current
,
745 uint32_t address
, int handle_breakpoints
, int debug_execution
)
747 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
748 struct breakpoint
*breakpoint
= NULL
;
752 if (target
->state
!= TARGET_HALTED
)
754 LOG_WARNING("target not halted");
755 return ERROR_TARGET_NOT_HALTED
;
758 if (!debug_execution
)
760 target_free_all_working_areas(target
);
761 cortex_m3_enable_breakpoints(target
);
762 cortex_m3_enable_watchpoints(target
);
767 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_PRIMASK
;
769 /* Disable interrupts */
770 /* We disable interrupts in the PRIMASK register instead of
771 * masking with C_MASKINTS. This is probably the same issue
772 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
773 * in parallel with disabled interrupts can cause local faults
776 * REVISIT this clearly breaks non-debug execution, since the
777 * PRIMASK register state isn't saved/restored... workaround
778 * by never resuming app code after debug execution.
780 buf_set_u32(r
->value
, 0, 1, 1);
784 /* Make sure we are in Thumb mode */
785 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_xPSR
;
786 buf_set_u32(r
->value
, 24, 1, 1);
791 /* current = 1: continue on current pc, otherwise continue at <address> */
795 buf_set_u32(r
->value
, 0, 32, address
);
800 /* if we halted last time due to a bkpt instruction
801 * then we have to manually step over it, otherwise
802 * the core will break again */
804 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
807 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
810 resume_pc
= buf_get_u32(r
->value
, 0, 32);
812 armv7m_restore_context(target
);
814 /* the front-end may request us not to handle breakpoints */
815 if (handle_breakpoints
)
817 /* Single step past breakpoint at current address */
818 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
820 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (ID: %d)",
822 breakpoint
->unique_id
);
823 cortex_m3_unset_breakpoint(target
, breakpoint
);
824 cortex_m3_single_step_core(target
);
825 cortex_m3_set_breakpoint(target
, breakpoint
);
830 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
832 target
->debug_reason
= DBG_REASON_NOTHALTED
;
834 /* registers are now invalid */
835 register_cache_invalidate(armv7m
->core_cache
);
837 if (!debug_execution
)
839 target
->state
= TARGET_RUNNING
;
840 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
841 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
845 target
->state
= TARGET_DEBUG_RUNNING
;
846 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
847 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
853 /* int irqstepcount = 0; */
854 static int cortex_m3_step(struct target
*target
, int current
,
855 uint32_t address
, int handle_breakpoints
)
857 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
858 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
859 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
860 struct breakpoint
*breakpoint
= NULL
;
861 struct reg
*pc
= armv7m
->arm
.pc
;
862 bool bkpt_inst_found
= false;
864 bool isr_timed_out
= false;
866 if (target
->state
!= TARGET_HALTED
)
868 LOG_WARNING("target not halted");
869 return ERROR_TARGET_NOT_HALTED
;
872 /* current = 1: continue on current pc, otherwise continue at <address> */
874 buf_set_u32(pc
->value
, 0, 32, address
);
876 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
878 /* the front-end may request us not to handle breakpoints */
879 if (handle_breakpoints
) {
880 breakpoint
= breakpoint_find(target
, pc_value
);
882 cortex_m3_unset_breakpoint(target
, breakpoint
);
885 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
887 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
889 armv7m_restore_context(target
);
891 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
893 /* if no bkpt instruction is found at pc then we can perform
894 * a normal step, otherwise we have to manually step over the bkpt
895 * instruction - as such simulate a step */
896 if (bkpt_inst_found
== false)
898 /* Automatic ISR masking mode off: Just step over the next instruction */
899 if ((cortex_m3
->isrmasking_mode
!= CORTEX_M3_ISRMASK_AUTO
))
901 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
905 /* Process interrupts during stepping in a way they don't interfere
910 * Set a temporary break point at the current pc and let the core run
911 * with interrupts enabled. Pending interrupts get served and we run
912 * into the breakpoint again afterwards. Then we step over the next
913 * instruction with interrupts disabled.
915 * If the pending interrupts don't complete within time, we leave the
916 * core running. This may happen if the interrupts trigger faster
917 * than the core can process them or the handler doesn't return.
919 * If no more breakpoints are available we simply do a step with
920 * interrupts enabled.
924 /* Set a temporary break point */
925 retval
= breakpoint_add(target
, pc_value
, 2, BKPT_TYPE_BY_ADDR(pc_value
));
926 bool tmp_bp_set
= (retval
== ERROR_OK
);
928 /* No more breakpoints left, just do a step */
931 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
936 LOG_DEBUG("Starting core to serve pending interrupts");
937 int64_t t_start
= timeval_ms();
938 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
);
940 /* Wait for pending handlers to complete or timeout */
942 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
943 if (retval
!= ERROR_OK
)
945 target
->state
= TARGET_UNKNOWN
;
948 isr_timed_out
= ((timeval_ms() - t_start
) > 500);
949 } while (!((cortex_m3
->dcb_dhcsr
& S_HALT
) || isr_timed_out
));
951 /* Remove the temporary breakpoint */
952 breakpoint_remove(target
, pc_value
);
956 LOG_DEBUG("Interrupt handlers didn't complete within time, "
957 "leaving target running");
961 /* Step over next instruction with interrupts disabled */
962 cortex_m3_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
963 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
964 /* Re-enable interrupts */
965 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
971 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
972 if (retval
!= ERROR_OK
)
975 /* registers are now invalid */
976 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
979 cortex_m3_set_breakpoint(target
, breakpoint
);
982 /* Leave the core running. The user has to stop execution manually. */
983 target
->debug_reason
= DBG_REASON_NOTHALTED
;
984 target
->state
= TARGET_RUNNING
;
988 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
989 " nvic_icsr = 0x%" PRIx32
,
990 cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
992 retval
= cortex_m3_debug_entry(target
);
993 if (retval
!= ERROR_OK
)
995 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
997 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
998 " nvic_icsr = 0x%" PRIx32
,
999 cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
1004 static int cortex_m3_assert_reset(struct target
*target
)
1006 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1007 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
1008 enum cortex_m3_soft_reset_config reset_config
= cortex_m3
->soft_reset_config
;
1010 LOG_DEBUG("target->state: %s",
1011 target_state_name(target
));
1013 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1015 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
1016 /* allow scripts to override the reset event */
1018 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1019 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
1020 target
->state
= TARGET_RESET
;
1025 /* Enable debug requests */
1027 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
1028 if (retval
!= ERROR_OK
)
1030 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
1032 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
1033 if (retval
!= ERROR_OK
)
1037 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
1038 if (retval
!= ERROR_OK
)
1041 if (!target
->reset_halt
)
1043 /* Set/Clear C_MASKINTS in a separate operation */
1044 if (cortex_m3
->dcb_dhcsr
& C_MASKINTS
)
1046 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
1047 DBGKEY
| C_DEBUGEN
| C_HALT
);
1048 if (retval
!= ERROR_OK
)
1052 /* clear any debug flags before resuming */
1053 cortex_m3_clear_halt(target
);
1055 /* clear C_HALT in dhcsr reg */
1056 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
1060 /* Halt in debug on reset; endreset_event() restores DEMCR.
1062 * REVISIT catching BUSERR presumably helps to defend against
1063 * bad vector table entries. Should this include MMERR or
1066 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DEMCR
,
1067 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1068 if (retval
!= ERROR_OK
)
1072 if (jtag_reset_config
& RESET_HAS_SRST
)
1074 /* default to asserting srst */
1075 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
1077 jtag_add_reset(1, 1);
1081 jtag_add_reset(0, 1);
1086 /* Use a standard Cortex-M3 software reset mechanism.
1087 * We default to using VECRESET as it is supported on all current cores.
1088 * This has the disadvantage of not resetting the peripherals, so a
1089 * reset-init event handler is needed to perform any peripheral resets.
1091 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
1092 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M3_RESET_SYSRESETREQ
)
1093 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1094 if (retval
!= ERROR_OK
)
1097 LOG_DEBUG("Using Cortex-M3 %s", (reset_config
== CORTEX_M3_RESET_SYSRESETREQ
)
1098 ? "SYSRESETREQ" : "VECTRESET");
1100 if (reset_config
== CORTEX_M3_RESET_VECTRESET
) {
1101 LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
1102 "handler to reset any peripherals");
1106 /* I do not know why this is necessary, but it
1107 * fixes strange effects (step/resume cause NMI
1108 * after reset) on LM3S6918 -- Michael Schwingen
1111 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_AIRCR
, &tmp
);
1112 if (retval
!= ERROR_OK
)
1117 target
->state
= TARGET_RESET
;
1118 jtag_add_sleep(50000);
1120 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
1122 if (target
->reset_halt
)
1124 if ((retval
= target_halt(target
)) != ERROR_OK
)
1131 static int cortex_m3_deassert_reset(struct target
*target
)
1133 LOG_DEBUG("target->state: %s",
1134 target_state_name(target
));
1136 /* deassert reset lines */
1137 jtag_add_reset(0, 0);
1143 cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1148 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1149 struct cortex_m3_fp_comparator
*comparator_list
= cortex_m3
->fp_comparator_list
;
1151 if (breakpoint
->set
)
1153 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint
->unique_id
);
1157 if (cortex_m3
->auto_bp_type
)
1159 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1162 if (breakpoint
->type
== BKPT_HARD
)
1164 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m3
->fp_num_code
))
1166 if (fp_num
>= cortex_m3
->fp_num_code
)
1168 LOG_ERROR("Can not find free FPB Comparator!");
1171 breakpoint
->set
= fp_num
+ 1;
1172 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1173 comparator_list
[fp_num
].used
= 1;
1174 comparator_list
[fp_num
].fpcr_value
= (breakpoint
->address
& 0x1FFFFFFC) | hilo
| 1;
1175 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
1176 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"", fp_num
, comparator_list
[fp_num
].fpcr_value
);
1177 if (!cortex_m3
->fpb_enabled
)
1179 LOG_DEBUG("FPB wasn't enabled, do it now");
1180 target_write_u32(target
, FP_CTRL
, 3);
1183 else if (breakpoint
->type
== BKPT_SOFT
)
1187 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1188 * semihosting; don't use that. Otherwise the BKPT
1189 * parameter is arbitrary.
1191 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1192 retval
= target_read_memory(target
,
1193 breakpoint
->address
& 0xFFFFFFFE,
1194 breakpoint
->length
, 1,
1195 breakpoint
->orig_instr
);
1196 if (retval
!= ERROR_OK
)
1198 retval
= target_write_memory(target
,
1199 breakpoint
->address
& 0xFFFFFFFE,
1200 breakpoint
->length
, 1,
1202 if (retval
!= ERROR_OK
)
1204 breakpoint
->set
= true;
1207 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1208 breakpoint
->unique_id
,
1209 (int)(breakpoint
->type
),
1210 breakpoint
->address
,
1218 cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1221 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1222 struct cortex_m3_fp_comparator
* comparator_list
= cortex_m3
->fp_comparator_list
;
1224 if (!breakpoint
->set
)
1226 LOG_WARNING("breakpoint not set");
1230 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1231 breakpoint
->unique_id
,
1232 (int)(breakpoint
->type
),
1233 breakpoint
->address
,
1237 if (breakpoint
->type
== BKPT_HARD
)
1239 int fp_num
= breakpoint
->set
- 1;
1240 if ((fp_num
< 0) || (fp_num
>= cortex_m3
->fp_num_code
))
1242 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1245 comparator_list
[fp_num
].used
= 0;
1246 comparator_list
[fp_num
].fpcr_value
= 0;
1247 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
1251 /* restore original instruction (kept in target endianness) */
1252 if (breakpoint
->length
== 4)
1254 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
1261 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
1267 breakpoint
->set
= false;
1273 cortex_m3_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1275 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1277 if (cortex_m3
->auto_bp_type
)
1279 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1280 #ifdef ARMV7_GDB_HACKS
1281 if (breakpoint
->length
!= 2) {
1282 /* XXX Hack: Replace all breakpoints with length != 2 with
1283 * a hardware breakpoint. */
1284 breakpoint
->type
= BKPT_HARD
;
1285 breakpoint
->length
= 2;
1290 if(breakpoint
->type
!= BKPT_TYPE_BY_ADDR(breakpoint
->address
)) {
1291 if (breakpoint
->type
== BKPT_HARD
)
1293 LOG_INFO("flash patch comparator requested outside code memory region");
1294 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1297 if (breakpoint
->type
== BKPT_SOFT
)
1299 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1300 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1304 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_m3
->fp_code_available
< 1))
1306 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1307 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1310 if ((breakpoint
->length
!= 2))
1312 LOG_INFO("only breakpoints of two bytes length supported");
1313 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1316 if (breakpoint
->type
== BKPT_HARD
)
1317 cortex_m3
->fp_code_available
--;
1319 return cortex_m3_set_breakpoint(target
, breakpoint
);
1323 cortex_m3_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1325 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1327 /* REVISIT why check? FBP can be updated with core running ... */
1328 if (target
->state
!= TARGET_HALTED
)
1330 LOG_WARNING("target not halted");
1331 return ERROR_TARGET_NOT_HALTED
;
1334 if (cortex_m3
->auto_bp_type
)
1336 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1339 if (breakpoint
->set
)
1341 cortex_m3_unset_breakpoint(target
, breakpoint
);
1344 if (breakpoint
->type
== BKPT_HARD
)
1345 cortex_m3
->fp_code_available
++;
1351 cortex_m3_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1354 uint32_t mask
, temp
;
1355 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1357 /* watchpoint params were validated earlier */
1359 temp
= watchpoint
->length
;
1366 /* REVISIT Don't fully trust these "not used" records ... users
1367 * may set up breakpoints by hand, e.g. dual-address data value
1368 * watchpoint using comparator #1; comparator #0 matching cycle
1369 * count; send data trace info through ITM and TPIU; etc
1371 struct cortex_m3_dwt_comparator
*comparator
;
1373 for (comparator
= cortex_m3
->dwt_comparator_list
;
1374 comparator
->used
&& dwt_num
< cortex_m3
->dwt_num_comp
;
1375 comparator
++, dwt_num
++)
1377 if (dwt_num
>= cortex_m3
->dwt_num_comp
)
1379 LOG_ERROR("Can not find free DWT Comparator");
1382 comparator
->used
= 1;
1383 watchpoint
->set
= dwt_num
+ 1;
1385 comparator
->comp
= watchpoint
->address
;
1386 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1389 comparator
->mask
= mask
;
1390 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1393 switch (watchpoint
->rw
) {
1395 comparator
->function
= 5;
1398 comparator
->function
= 6;
1401 comparator
->function
= 7;
1404 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1405 comparator
->function
);
1407 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1408 watchpoint
->unique_id
, dwt_num
,
1409 (unsigned) comparator
->comp
,
1410 (unsigned) comparator
->mask
,
1411 (unsigned) comparator
->function
);
1416 cortex_m3_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1418 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1419 struct cortex_m3_dwt_comparator
*comparator
;
1422 if (!watchpoint
->set
)
1424 LOG_WARNING("watchpoint (wpid: %d) not set",
1425 watchpoint
->unique_id
);
1429 dwt_num
= watchpoint
->set
- 1;
1431 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1432 watchpoint
->unique_id
, dwt_num
,
1433 (unsigned) watchpoint
->address
);
1435 if ((dwt_num
< 0) || (dwt_num
>= cortex_m3
->dwt_num_comp
))
1437 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1441 comparator
= cortex_m3
->dwt_comparator_list
+ dwt_num
;
1442 comparator
->used
= 0;
1443 comparator
->function
= 0;
1444 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1445 comparator
->function
);
1447 watchpoint
->set
= false;
1453 cortex_m3_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1455 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1457 if (cortex_m3
->dwt_comp_available
< 1)
1459 LOG_DEBUG("no comparators?");
1460 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1463 /* hardware doesn't support data value masking */
1464 if (watchpoint
->mask
!= ~(uint32_t)0) {
1465 LOG_DEBUG("watchpoint value masks not supported");
1466 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1469 /* hardware allows address masks of up to 32K */
1472 for (mask
= 0; mask
< 16; mask
++) {
1473 if ((1u << mask
) == watchpoint
->length
)
1477 LOG_DEBUG("unsupported watchpoint length");
1478 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1480 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1481 LOG_DEBUG("watchpoint address is unaligned");
1482 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1485 /* Caller doesn't seem to be able to describe watching for data
1486 * values of zero; that flags "no value".
1488 * REVISIT This DWT may well be able to watch for specific data
1489 * values. Requires comparator #1 to set DATAVMATCH and match
1490 * the data, and another comparator (DATAVADDR0) matching addr.
1492 if (watchpoint
->value
) {
1493 LOG_DEBUG("data value watchpoint not YET supported");
1494 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1497 cortex_m3
->dwt_comp_available
--;
1498 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1504 cortex_m3_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1506 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1508 /* REVISIT why check? DWT can be updated with core running ... */
1509 if (target
->state
!= TARGET_HALTED
)
1511 LOG_WARNING("target not halted");
1512 return ERROR_TARGET_NOT_HALTED
;
1515 if (watchpoint
->set
)
1517 cortex_m3_unset_watchpoint(target
, watchpoint
);
1520 cortex_m3
->dwt_comp_available
++;
1521 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1526 void cortex_m3_enable_watchpoints(struct target
*target
)
1528 struct watchpoint
*watchpoint
= target
->watchpoints
;
1530 /* set any pending watchpoints */
1533 if (!watchpoint
->set
)
1534 cortex_m3_set_watchpoint(target
, watchpoint
);
1535 watchpoint
= watchpoint
->next
;
1539 static int cortex_m3_load_core_reg_u32(struct target
*target
,
1540 enum armv7m_regtype type
, uint32_t num
, uint32_t * value
)
1543 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1544 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1546 /* NOTE: we "know" here that the register identifiers used
1547 * in the v7m header match the Cortex-M3 Debug Core Register
1548 * Selector values for R0..R15, xPSR, MSP, and PSP.
1552 /* read a normal core register */
1553 retval
= cortexm3_dap_read_coreregister_u32(swjdp
, value
, num
);
1555 if (retval
!= ERROR_OK
)
1557 LOG_ERROR("JTAG failure %i",retval
);
1558 return ERROR_JTAG_DEVICE_ERROR
;
1560 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"",(int)num
,*value
);
1563 case ARMV7M_PRIMASK
:
1564 case ARMV7M_BASEPRI
:
1565 case ARMV7M_FAULTMASK
:
1566 case ARMV7M_CONTROL
:
1567 /* Cortex-M3 packages these four registers as bitfields
1568 * in one Debug Core register. So say r0 and r2 docs;
1569 * it was removed from r1 docs, but still works.
1571 cortexm3_dap_read_coreregister_u32(swjdp
, value
, 20);
1575 case ARMV7M_PRIMASK
:
1576 *value
= buf_get_u32((uint8_t*)value
, 0, 1);
1579 case ARMV7M_BASEPRI
:
1580 *value
= buf_get_u32((uint8_t*)value
, 8, 8);
1583 case ARMV7M_FAULTMASK
:
1584 *value
= buf_get_u32((uint8_t*)value
, 16, 1);
1587 case ARMV7M_CONTROL
:
1588 *value
= buf_get_u32((uint8_t*)value
, 24, 2);
1592 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1596 return ERROR_COMMAND_SYNTAX_ERROR
;
1602 static int cortex_m3_store_core_reg_u32(struct target
*target
,
1603 enum armv7m_regtype type
, uint32_t num
, uint32_t value
)
1607 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1608 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1610 #ifdef ARMV7_GDB_HACKS
1611 /* If the LR register is being modified, make sure it will put us
1612 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1613 * hack to deal with the fact that gdb will sometimes "forge"
1614 * return addresses, and doesn't set the LSB correctly (i.e., when
1615 * printing expressions containing function calls, it sets LR = 0.)
1616 * Valid exception return codes have bit 0 set too.
1618 if (num
== ARMV7M_R14
)
1622 /* NOTE: we "know" here that the register identifiers used
1623 * in the v7m header match the Cortex-M3 Debug Core Register
1624 * Selector values for R0..R15, xPSR, MSP, and PSP.
1628 retval
= cortexm3_dap_write_coreregister_u32(swjdp
, value
, num
);
1629 if (retval
!= ERROR_OK
)
1633 LOG_ERROR("JTAG failure");
1634 r
= armv7m
->core_cache
->reg_list
+ num
;
1635 r
->dirty
= r
->valid
;
1636 return ERROR_JTAG_DEVICE_ERROR
;
1638 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1641 case ARMV7M_PRIMASK
:
1642 case ARMV7M_BASEPRI
:
1643 case ARMV7M_FAULTMASK
:
1644 case ARMV7M_CONTROL
:
1645 /* Cortex-M3 packages these four registers as bitfields
1646 * in one Debug Core register. So say r0 and r2 docs;
1647 * it was removed from r1 docs, but still works.
1649 cortexm3_dap_read_coreregister_u32(swjdp
, ®
, 20);
1653 case ARMV7M_PRIMASK
:
1654 buf_set_u32((uint8_t*)®
, 0, 1, value
);
1657 case ARMV7M_BASEPRI
:
1658 buf_set_u32((uint8_t*)®
, 8, 8, value
);
1661 case ARMV7M_FAULTMASK
:
1662 buf_set_u32((uint8_t*)®
, 16, 1, value
);
1665 case ARMV7M_CONTROL
:
1666 buf_set_u32((uint8_t*)®
, 24, 2, value
);
1670 cortexm3_dap_write_coreregister_u32(swjdp
, reg
, 20);
1672 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1676 return ERROR_COMMAND_SYNTAX_ERROR
;
1682 static int cortex_m3_read_memory(struct target
*target
, uint32_t address
,
1683 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1685 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1686 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1687 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1689 /* cortex_m3 handles unaligned memory access */
1690 if (count
&& buffer
) {
1693 retval
= mem_ap_read_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1696 retval
= mem_ap_read_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1699 retval
= mem_ap_read_buf_u8(swjdp
, buffer
, count
, address
);
1707 static int cortex_m3_write_memory(struct target
*target
, uint32_t address
,
1708 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1710 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1711 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1712 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1714 if (count
&& buffer
) {
1717 retval
= mem_ap_write_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1720 retval
= mem_ap_write_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1723 retval
= mem_ap_write_buf_u8(swjdp
, buffer
, count
, address
);
1731 static int cortex_m3_bulk_write_memory(struct target
*target
, uint32_t address
,
1732 uint32_t count
, const uint8_t *buffer
)
1734 return cortex_m3_write_memory(target
, address
, 4, count
, buffer
);
1737 static int cortex_m3_init_target(struct command_context
*cmd_ctx
,
1738 struct target
*target
)
1740 armv7m_build_reg_cache(target
);
1744 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1745 * on r/w if the core is not running, and clear on resume or reset ... or
1746 * at least, in a post_restore_context() method.
1749 struct dwt_reg_state
{
1750 struct target
*target
;
1752 uint32_t value
; /* scratch/cache */
1755 static int cortex_m3_dwt_get_reg(struct reg
*reg
)
1757 struct dwt_reg_state
*state
= reg
->arch_info
;
1759 return target_read_u32(state
->target
, state
->addr
, &state
->value
);
1762 static int cortex_m3_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1764 struct dwt_reg_state
*state
= reg
->arch_info
;
1766 return target_write_u32(state
->target
, state
->addr
,
1767 buf_get_u32(buf
, 0, reg
->size
));
1776 static struct dwt_reg dwt_base_regs
[] = {
1777 { DWT_CTRL
, "dwt_ctrl", 32, },
1778 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1779 * increments while the core is asleep.
1781 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1782 /* plus some 8 bit counters, useful for profiling with TPIU */
1785 static struct dwt_reg dwt_comp
[] = {
1786 #define DWT_COMPARATOR(i) \
1787 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1788 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1789 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1794 #undef DWT_COMPARATOR
1797 static const struct reg_arch_type dwt_reg_type
= {
1798 .get
= cortex_m3_dwt_get_reg
,
1799 .set
= cortex_m3_dwt_set_reg
,
1803 cortex_m3_dwt_addreg(struct target
*t
, struct reg
*r
, struct dwt_reg
*d
)
1805 struct dwt_reg_state
*state
;
1807 state
= calloc(1, sizeof *state
);
1810 state
->addr
= d
->addr
;
1815 r
->value
= &state
->value
;
1816 r
->arch_info
= state
;
1817 r
->type
= &dwt_reg_type
;
1821 cortex_m3_dwt_setup(struct cortex_m3_common
*cm3
, struct target
*target
)
1824 struct reg_cache
*cache
;
1825 struct cortex_m3_dwt_comparator
*comparator
;
1828 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1830 LOG_DEBUG("no DWT");
1834 cm3
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1835 cm3
->dwt_comp_available
= cm3
->dwt_num_comp
;
1836 cm3
->dwt_comparator_list
= calloc(cm3
->dwt_num_comp
,
1837 sizeof(struct cortex_m3_dwt_comparator
));
1838 if (!cm3
->dwt_comparator_list
) {
1840 cm3
->dwt_num_comp
= 0;
1841 LOG_ERROR("out of mem");
1845 cache
= calloc(1, sizeof *cache
);
1848 free(cm3
->dwt_comparator_list
);
1851 cache
->name
= "cortex-m3 dwt registers";
1852 cache
->num_regs
= 2 + cm3
->dwt_num_comp
* 3;
1853 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
1854 if (!cache
->reg_list
) {
1859 for (reg
= 0; reg
< 2; reg
++)
1860 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1861 dwt_base_regs
+ reg
);
1863 comparator
= cm3
->dwt_comparator_list
;
1864 for (i
= 0; i
< cm3
->dwt_num_comp
; i
++, comparator
++) {
1867 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
1868 for (j
= 0; j
< 3; j
++, reg
++)
1869 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1870 dwt_comp
+ 3 * i
+ j
);
1873 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
1874 cm3
->dwt_cache
= cache
;
1876 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
1877 dwtcr
, cm3
->dwt_num_comp
,
1878 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
1880 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1881 * implement single-address data value watchpoints ... so we
1882 * won't need to check it later, when asked to set one up.
1886 static int cortex_m3_examine(struct target
*target
)
1889 uint32_t cpuid
, fpcr
;
1891 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1892 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
1894 if ((retval
= ahbap_debugport_init(swjdp
)) != ERROR_OK
)
1897 if (!target_was_examined(target
))
1899 target_set_examined(target
);
1901 /* Read from Device Identification Registers */
1902 retval
= target_read_u32(target
, CPUID
, &cpuid
);
1903 if (retval
!= ERROR_OK
)
1906 if (((cpuid
>> 4) & 0xc3f) == 0xc23)
1907 LOG_DEBUG("Cortex-M3 r%" PRId8
"p%" PRId8
" processor detected",
1908 (uint8_t)((cpuid
>> 20) & 0xf), (uint8_t)((cpuid
>> 0) & 0xf));
1909 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
1911 /* NOTE: FPB and DWT are both optional. */
1914 target_read_u32(target
, FP_CTRL
, &fpcr
);
1915 cortex_m3
->auto_bp_type
= 1;
1916 cortex_m3
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF); /* bits [14:12] and [7:4] */
1917 cortex_m3
->fp_num_lit
= (fpcr
>> 8) & 0xF;
1918 cortex_m3
->fp_code_available
= cortex_m3
->fp_num_code
;
1919 cortex_m3
->fp_comparator_list
= calloc(cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
, sizeof(struct cortex_m3_fp_comparator
));
1920 cortex_m3
->fpb_enabled
= fpcr
& 1;
1921 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
1923 cortex_m3
->fp_comparator_list
[i
].type
= (i
< cortex_m3
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
1924 cortex_m3
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
1926 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i", fpcr
, cortex_m3
->fp_num_code
, cortex_m3
->fp_num_lit
);
1929 cortex_m3_dwt_setup(cortex_m3
, target
);
1931 /* These hardware breakpoints only work for code in flash! */
1932 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1933 target_name(target
),
1934 cortex_m3
->fp_num_code
,
1935 cortex_m3
->dwt_num_comp
);
1941 static int cortex_m3_dcc_read(struct adiv5_dap
*swjdp
, uint8_t *value
, uint8_t *ctrl
)
1946 mem_ap_read_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1947 *ctrl
= (uint8_t)dcrdr
;
1948 *value
= (uint8_t)(dcrdr
>> 8);
1950 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
1952 /* write ack back to software dcc register
1953 * signify we have read data */
1954 if (dcrdr
& (1 << 0))
1957 retval
= mem_ap_write_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1958 if (retval
!= ERROR_OK
)
1965 static int cortex_m3_target_request_data(struct target
*target
,
1966 uint32_t size
, uint8_t *buffer
)
1968 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1969 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1974 for (i
= 0; i
< (size
* 4); i
++)
1976 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1983 static int cortex_m3_handle_target_request(void *priv
)
1985 struct target
*target
= priv
;
1986 if (!target_was_examined(target
))
1988 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1989 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1991 if (!target
->dbg_msg_enabled
)
1994 if (target
->state
== TARGET_RUNNING
)
1999 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
2001 /* check if we have data */
2002 if (ctrl
& (1 << 0))
2006 /* we assume target is quick enough */
2008 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
2009 request
|= (data
<< 8);
2010 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
2011 request
|= (data
<< 16);
2012 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
2013 request
|= (data
<< 24);
2014 target_request(target
, request
);
2021 static int cortex_m3_init_arch_info(struct target
*target
,
2022 struct cortex_m3_common
*cortex_m3
, struct jtag_tap
*tap
)
2025 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
2027 armv7m_init_arch_info(target
, armv7m
);
2029 /* prepare JTAG information for the new target */
2030 cortex_m3
->jtag_info
.tap
= tap
;
2031 cortex_m3
->jtag_info
.scann_size
= 4;
2033 /* default reset mode is to use srst if fitted
2034 * if not it will use CORTEX_M3_RESET_VECTRESET */
2035 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_VECTRESET
;
2037 armv7m
->arm
.dap
= &armv7m
->dap
;
2039 /* Leave (only) generic DAP stuff for debugport_init(); */
2040 armv7m
->dap
.jtag_info
= &cortex_m3
->jtag_info
;
2041 armv7m
->dap
.memaccess_tck
= 8;
2042 /* Cortex-M3 has 4096 bytes autoincrement range */
2043 armv7m
->dap
.tar_autoincr_block
= (1 << 12);
2045 /* register arch-specific functions */
2046 armv7m
->examine_debug_reason
= cortex_m3_examine_debug_reason
;
2048 armv7m
->post_debug_entry
= NULL
;
2050 armv7m
->pre_restore_context
= NULL
;
2052 armv7m
->load_core_reg_u32
= cortex_m3_load_core_reg_u32
;
2053 armv7m
->store_core_reg_u32
= cortex_m3_store_core_reg_u32
;
2055 target_register_timer_callback(cortex_m3_handle_target_request
, 1, 1, target
);
2057 if ((retval
= arm_jtag_setup_connection(&cortex_m3
->jtag_info
)) != ERROR_OK
)
2065 static int cortex_m3_target_create(struct target
*target
, Jim_Interp
*interp
)
2067 struct cortex_m3_common
*cortex_m3
= calloc(1,sizeof(struct cortex_m3_common
));
2069 cortex_m3
->common_magic
= CORTEX_M3_COMMON_MAGIC
;
2070 cortex_m3_init_arch_info(target
, cortex_m3
, target
->tap
);
2075 /*--------------------------------------------------------------------------*/
2077 static int cortex_m3_verify_pointer(struct command_context
*cmd_ctx
,
2078 struct cortex_m3_common
*cm3
)
2080 if (cm3
->common_magic
!= CORTEX_M3_COMMON_MAGIC
) {
2081 command_print(cmd_ctx
, "target is not a Cortex-M3");
2082 return ERROR_TARGET_INVALID
;
2088 * Only stuff below this line should need to verify that its target
2089 * is a Cortex-M3. Everything else should have indirected through the
2090 * cortexm3_target structure, which is only used with CM3 targets.
2093 static const struct {
2097 { "hard_err", VC_HARDERR
, },
2098 { "int_err", VC_INTERR
, },
2099 { "bus_err", VC_BUSERR
, },
2100 { "state_err", VC_STATERR
, },
2101 { "chk_err", VC_CHKERR
, },
2102 { "nocp_err", VC_NOCPERR
, },
2103 { "mm_err", VC_MMERR
, },
2104 { "reset", VC_CORERESET
, },
2107 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command
)
2109 struct target
*target
= get_current_target(CMD_CTX
);
2110 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2111 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
2112 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
2116 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2117 if (retval
!= ERROR_OK
)
2120 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2121 if (retval
!= ERROR_OK
)
2127 if (CMD_ARGC
== 1) {
2128 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2129 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2130 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2131 | VC_MMERR
| VC_CORERESET
;
2133 } else if (strcmp(CMD_ARGV
[0], "none") == 0) {
2137 while (CMD_ARGC
-- > 0) {
2139 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2140 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2142 catch |= vec_ids
[i
].mask
;
2145 if (i
== ARRAY_SIZE(vec_ids
)) {
2146 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2147 return ERROR_COMMAND_SYNTAX_ERROR
;
2151 /* For now, armv7m->demcr only stores vector catch flags. */
2152 armv7m
->demcr
= catch;
2157 /* write, but don't assume it stuck (why not??) */
2158 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, demcr
);
2159 if (retval
!= ERROR_OK
)
2161 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2162 if (retval
!= ERROR_OK
)
2165 /* FIXME be sure to clear DEMCR on clean server shutdown.
2166 * Otherwise the vector catch hardware could fire when there's
2167 * no debugger hooked up, causing much confusion...
2171 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++)
2173 command_print(CMD_CTX
, "%9s: %s", vec_ids
[i
].name
,
2174 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2180 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command
)
2182 struct target
*target
= get_current_target(CMD_CTX
);
2183 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2186 static const Jim_Nvp nvp_maskisr_modes
[] = {
2187 { .name
= "auto", .value
= CORTEX_M3_ISRMASK_AUTO
},
2188 { .name
= "off" , .value
= CORTEX_M3_ISRMASK_OFF
},
2189 { .name
= "on" , .value
= CORTEX_M3_ISRMASK_ON
},
2190 { .name
= NULL
, .value
= -1 },
2195 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2196 if (retval
!= ERROR_OK
)
2199 if (target
->state
!= TARGET_HALTED
)
2201 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
2207 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
2208 if (n
->name
== NULL
)
2210 return ERROR_COMMAND_SYNTAX_ERROR
;
2212 cortex_m3
->isrmasking_mode
= n
->value
;
2215 if(cortex_m3
->isrmasking_mode
== CORTEX_M3_ISRMASK_ON
)
2217 cortex_m3_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
2221 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
2225 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_m3
->isrmasking_mode
);
2226 command_print(CMD_CTX
, "cortex_m3 interrupt mask %s", n
->name
);
2231 COMMAND_HANDLER(handle_cortex_m3_reset_config_command
)
2233 struct target
*target
= get_current_target(CMD_CTX
);
2234 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2238 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2239 if (retval
!= ERROR_OK
)
2244 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2245 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_SYSRESETREQ
;
2246 else if (strcmp(*CMD_ARGV
, "vectreset") == 0)
2247 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_VECTRESET
;
2250 switch (cortex_m3
->soft_reset_config
)
2252 case CORTEX_M3_RESET_SYSRESETREQ
:
2253 reset_config
= "sysresetreq";
2256 case CORTEX_M3_RESET_VECTRESET
:
2257 reset_config
= "vectreset";
2261 reset_config
= "unknown";
2265 command_print(CMD_CTX
, "cortex_m3 reset_config %s", reset_config
);
2270 static const struct command_registration cortex_m3_exec_command_handlers
[] = {
2273 .handler
= handle_cortex_m3_mask_interrupts_command
,
2274 .mode
= COMMAND_EXEC
,
2275 .help
= "mask cortex_m3 interrupts",
2276 .usage
= "['auto'|'on'|'off']",
2279 .name
= "vector_catch",
2280 .handler
= handle_cortex_m3_vector_catch_command
,
2281 .mode
= COMMAND_EXEC
,
2282 .help
= "configure hardware vectors to trigger debug entry",
2283 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2286 .name
= "reset_config",
2287 .handler
= handle_cortex_m3_reset_config_command
,
2288 .mode
= COMMAND_ANY
,
2289 .help
= "configure software reset handling",
2290 .usage
= "['srst'|'sysresetreq'|'vectreset']",
2292 COMMAND_REGISTRATION_DONE
2294 static const struct command_registration cortex_m3_command_handlers
[] = {
2296 .chain
= armv7m_command_handlers
,
2299 .name
= "cortex_m3",
2300 .mode
= COMMAND_EXEC
,
2301 .help
= "Cortex-M3 command group",
2302 .chain
= cortex_m3_exec_command_handlers
,
2304 COMMAND_REGISTRATION_DONE
2307 struct target_type cortexm3_target
=
2309 .name
= "cortex_m3",
2311 .poll
= cortex_m3_poll
,
2312 .arch_state
= armv7m_arch_state
,
2314 .target_request_data
= cortex_m3_target_request_data
,
2316 .halt
= cortex_m3_halt
,
2317 .resume
= cortex_m3_resume
,
2318 .step
= cortex_m3_step
,
2320 .assert_reset
= cortex_m3_assert_reset
,
2321 .deassert_reset
= cortex_m3_deassert_reset
,
2322 .soft_reset_halt
= cortex_m3_soft_reset_halt
,
2324 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2326 .read_memory
= cortex_m3_read_memory
,
2327 .write_memory
= cortex_m3_write_memory
,
2328 .bulk_write_memory
= cortex_m3_bulk_write_memory
,
2329 .checksum_memory
= armv7m_checksum_memory
,
2330 .blank_check_memory
= armv7m_blank_check_memory
,
2332 .run_algorithm
= armv7m_run_algorithm
,
2333 .start_algorithm
= armv7m_start_algorithm
,
2334 .wait_algorithm
= armv7m_wait_algorithm
,
2336 .add_breakpoint
= cortex_m3_add_breakpoint
,
2337 .remove_breakpoint
= cortex_m3_remove_breakpoint
,
2338 .add_watchpoint
= cortex_m3_add_watchpoint
,
2339 .remove_watchpoint
= cortex_m3_remove_watchpoint
,
2341 .commands
= cortex_m3_command_handlers
,
2342 .target_create
= cortex_m3_target_create
,
2343 .init_target
= cortex_m3_init_target
,
2344 .examine
= cortex_m3_examine
,
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