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[openocd.git] / src / target / cortex_m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 * *
26 * *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
28 * *
29 ***************************************************************************/
30 #ifdef HAVE_CONFIG_H
31 #include "config.h"
32 #endif
33
34 #include "jtag/interface.h"
35 #include "breakpoints.h"
36 #include "cortex_m.h"
37 #include "target_request.h"
38 #include "target_type.h"
39 #include "arm_disassembler.h"
40 #include "register.h"
41 #include "arm_opcodes.h"
42 #include "arm_semihosting.h"
43 #include <helper/time_support.h>
44
45 /* NOTE: most of this should work fine for the Cortex-M1 and
46 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
47 * Some differences: M0/M1 doesn't have FBP remapping or the
48 * DWT tracing/profiling support. (So the cycle counter will
49 * not be usable; the other stuff isn't currently used here.)
50 *
51 * Although there are some workarounds for errata seen only in r0p0
52 * silicon, such old parts are hard to find and thus not much tested
53 * any longer.
54 */
55
56 /**
57 * Returns the type of a break point required by address location
58 */
59 #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
60
61 /* forward declarations */
62 static int cortex_m_store_core_reg_u32(struct target *target,
63 uint32_t num, uint32_t value);
64 static void cortex_m_dwt_free(struct target *target);
65
66 static int cortexm_dap_read_coreregister_u32(struct target *target,
67 uint32_t *value, int regnum)
68 {
69 struct armv7m_common *armv7m = target_to_armv7m(target);
70 struct adiv5_dap *swjdp = armv7m->arm.dap;
71 int retval;
72 uint32_t dcrdr;
73
74 /* because the DCB_DCRDR is used for the emulated dcc channel
75 * we have to save/restore the DCB_DCRDR when used */
76 if (target->dbg_msg_enabled) {
77 retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
78 if (retval != ERROR_OK)
79 return retval;
80 }
81
82 retval = mem_ap_write_u32(swjdp, DCB_DCRSR, regnum);
83 if (retval != ERROR_OK)
84 return retval;
85
86 retval = mem_ap_read_atomic_u32(swjdp, DCB_DCRDR, value);
87 if (retval != ERROR_OK)
88 return retval;
89
90 if (target->dbg_msg_enabled) {
91 /* restore DCB_DCRDR - this needs to be in a separate
92 * transaction otherwise the emulated DCC channel breaks */
93 if (retval == ERROR_OK)
94 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
95 }
96
97 return retval;
98 }
99
100 static int cortexm_dap_write_coreregister_u32(struct target *target,
101 uint32_t value, int regnum)
102 {
103 struct armv7m_common *armv7m = target_to_armv7m(target);
104 struct adiv5_dap *swjdp = armv7m->arm.dap;
105 int retval;
106 uint32_t dcrdr;
107
108 /* because the DCB_DCRDR is used for the emulated dcc channel
109 * we have to save/restore the DCB_DCRDR when used */
110 if (target->dbg_msg_enabled) {
111 retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
112 if (retval != ERROR_OK)
113 return retval;
114 }
115
116 retval = mem_ap_write_u32(swjdp, DCB_DCRDR, value);
117 if (retval != ERROR_OK)
118 return retval;
119
120 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRSR, regnum | DCRSR_WnR);
121 if (retval != ERROR_OK)
122 return retval;
123
124 if (target->dbg_msg_enabled) {
125 /* restore DCB_DCRDR - this needs to be in a seperate
126 * transaction otherwise the emulated DCC channel breaks */
127 if (retval == ERROR_OK)
128 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
129 }
130
131 return retval;
132 }
133
134 static int cortex_m_write_debug_halt_mask(struct target *target,
135 uint32_t mask_on, uint32_t mask_off)
136 {
137 struct cortex_m_common *cortex_m = target_to_cm(target);
138 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
139
140 /* mask off status bits */
141 cortex_m->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
142 /* create new register mask */
143 cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
144
145 return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m->dcb_dhcsr);
146 }
147
148 static int cortex_m_clear_halt(struct target *target)
149 {
150 struct cortex_m_common *cortex_m = target_to_cm(target);
151 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
152 int retval;
153
154 /* clear step if any */
155 cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
156
157 /* Read Debug Fault Status Register */
158 retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m->nvic_dfsr);
159 if (retval != ERROR_OK)
160 return retval;
161
162 /* Clear Debug Fault Status */
163 retval = mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m->nvic_dfsr);
164 if (retval != ERROR_OK)
165 return retval;
166 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
167
168 return ERROR_OK;
169 }
170
171 static int cortex_m_single_step_core(struct target *target)
172 {
173 struct cortex_m_common *cortex_m = target_to_cm(target);
174 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
175 uint32_t dhcsr_save;
176 int retval;
177
178 /* backup dhcsr reg */
179 dhcsr_save = cortex_m->dcb_dhcsr;
180
181 /* Mask interrupts before clearing halt, if done already. This avoids
182 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
183 * HALT can put the core into an unknown state.
184 */
185 if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
186 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
187 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
188 if (retval != ERROR_OK)
189 return retval;
190 }
191 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
192 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
193 if (retval != ERROR_OK)
194 return retval;
195 LOG_DEBUG(" ");
196
197 /* restore dhcsr reg */
198 cortex_m->dcb_dhcsr = dhcsr_save;
199 cortex_m_clear_halt(target);
200
201 return ERROR_OK;
202 }
203
204 static int cortex_m_enable_fpb(struct target *target)
205 {
206 int retval = target_write_u32(target, FP_CTRL, 3);
207 if (retval != ERROR_OK)
208 return retval;
209
210 /* check the fpb is actually enabled */
211 uint32_t fpctrl;
212 retval = target_read_u32(target, FP_CTRL, &fpctrl);
213 if (retval != ERROR_OK)
214 return retval;
215
216 if (fpctrl & 1)
217 return ERROR_OK;
218
219 return ERROR_FAIL;
220 }
221
222 static int cortex_m_endreset_event(struct target *target)
223 {
224 int i;
225 int retval;
226 uint32_t dcb_demcr;
227 struct cortex_m_common *cortex_m = target_to_cm(target);
228 struct armv7m_common *armv7m = &cortex_m->armv7m;
229 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
230 struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
231 struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
232
233 /* REVISIT The four debug monitor bits are currently ignored... */
234 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
235 if (retval != ERROR_OK)
236 return retval;
237 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
238
239 /* this register is used for emulated dcc channel */
240 retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
241 if (retval != ERROR_OK)
242 return retval;
243
244 /* Enable debug requests */
245 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
246 if (retval != ERROR_OK)
247 return retval;
248 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
249 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
250 if (retval != ERROR_OK)
251 return retval;
252 }
253
254 /* clear any interrupt masking */
255 cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
256
257 /* Enable features controlled by ITM and DWT blocks, and catch only
258 * the vectors we were told to pay attention to.
259 *
260 * Target firmware is responsible for all fault handling policy
261 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
262 * or manual updates to the NVIC SHCSR and CCR registers.
263 */
264 retval = mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
265 if (retval != ERROR_OK)
266 return retval;
267
268 /* Paranoia: evidently some (early?) chips don't preserve all the
269 * debug state (including FBP, DWT, etc) across reset...
270 */
271
272 /* Enable FPB */
273 retval = cortex_m_enable_fpb(target);
274 if (retval != ERROR_OK) {
275 LOG_ERROR("Failed to enable the FPB");
276 return retval;
277 }
278
279 cortex_m->fpb_enabled = 1;
280
281 /* Restore FPB registers */
282 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
283 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
284 if (retval != ERROR_OK)
285 return retval;
286 }
287
288 /* Restore DWT registers */
289 for (i = 0; i < cortex_m->dwt_num_comp; i++) {
290 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
291 dwt_list[i].comp);
292 if (retval != ERROR_OK)
293 return retval;
294 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
295 dwt_list[i].mask);
296 if (retval != ERROR_OK)
297 return retval;
298 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
299 dwt_list[i].function);
300 if (retval != ERROR_OK)
301 return retval;
302 }
303 retval = dap_run(swjdp);
304 if (retval != ERROR_OK)
305 return retval;
306
307 register_cache_invalidate(armv7m->arm.core_cache);
308
309 /* make sure we have latest dhcsr flags */
310 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
311
312 return retval;
313 }
314
315 static int cortex_m_examine_debug_reason(struct target *target)
316 {
317 struct cortex_m_common *cortex_m = target_to_cm(target);
318
319 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
320 * only check the debug reason if we don't know it already */
321
322 if ((target->debug_reason != DBG_REASON_DBGRQ)
323 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
324 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
325 target->debug_reason = DBG_REASON_BREAKPOINT;
326 if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
327 target->debug_reason = DBG_REASON_WPTANDBKPT;
328 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
329 target->debug_reason = DBG_REASON_WATCHPOINT;
330 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
331 target->debug_reason = DBG_REASON_BREAKPOINT;
332 else /* EXTERNAL, HALTED */
333 target->debug_reason = DBG_REASON_UNDEFINED;
334 }
335
336 return ERROR_OK;
337 }
338
339 static int cortex_m_examine_exception_reason(struct target *target)
340 {
341 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
342 struct armv7m_common *armv7m = target_to_armv7m(target);
343 struct adiv5_dap *swjdp = armv7m->arm.dap;
344 int retval;
345
346 retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
347 if (retval != ERROR_OK)
348 return retval;
349 switch (armv7m->exception_number) {
350 case 2: /* NMI */
351 break;
352 case 3: /* Hard Fault */
353 retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
354 if (retval != ERROR_OK)
355 return retval;
356 if (except_sr & 0x40000000) {
357 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
358 if (retval != ERROR_OK)
359 return retval;
360 }
361 break;
362 case 4: /* Memory Management */
363 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
364 if (retval != ERROR_OK)
365 return retval;
366 retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
367 if (retval != ERROR_OK)
368 return retval;
369 break;
370 case 5: /* Bus Fault */
371 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
372 if (retval != ERROR_OK)
373 return retval;
374 retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
375 if (retval != ERROR_OK)
376 return retval;
377 break;
378 case 6: /* Usage Fault */
379 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
380 if (retval != ERROR_OK)
381 return retval;
382 break;
383 case 11: /* SVCall */
384 break;
385 case 12: /* Debug Monitor */
386 retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
387 if (retval != ERROR_OK)
388 return retval;
389 break;
390 case 14: /* PendSV */
391 break;
392 case 15: /* SysTick */
393 break;
394 default:
395 except_sr = 0;
396 break;
397 }
398 retval = dap_run(swjdp);
399 if (retval == ERROR_OK)
400 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
401 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
402 armv7m_exception_string(armv7m->exception_number),
403 shcsr, except_sr, cfsr, except_ar);
404 return retval;
405 }
406
407 static int cortex_m_debug_entry(struct target *target)
408 {
409 int i;
410 uint32_t xPSR;
411 int retval;
412 struct cortex_m_common *cortex_m = target_to_cm(target);
413 struct armv7m_common *armv7m = &cortex_m->armv7m;
414 struct arm *arm = &armv7m->arm;
415 struct adiv5_dap *swjdp = armv7m->arm.dap;
416 struct reg *r;
417
418 LOG_DEBUG(" ");
419
420 cortex_m_clear_halt(target);
421 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
422 if (retval != ERROR_OK)
423 return retval;
424
425 retval = armv7m->examine_debug_reason(target);
426 if (retval != ERROR_OK)
427 return retval;
428
429 /* Examine target state and mode
430 * First load register accessible through core debug port */
431 int num_regs = arm->core_cache->num_regs;
432
433 for (i = 0; i < num_regs; i++) {
434 r = &armv7m->arm.core_cache->reg_list[i];
435 if (!r->valid)
436 arm->read_core_reg(target, r, i, ARM_MODE_ANY);
437 }
438
439 r = arm->cpsr;
440 xPSR = buf_get_u32(r->value, 0, 32);
441
442 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
443 if (xPSR & 0xf00) {
444 r->dirty = r->valid;
445 cortex_m_store_core_reg_u32(target, 16, xPSR & ~0xff);
446 }
447
448 /* Are we in an exception handler */
449 if (xPSR & 0x1FF) {
450 armv7m->exception_number = (xPSR & 0x1FF);
451
452 arm->core_mode = ARM_MODE_HANDLER;
453 arm->map = armv7m_msp_reg_map;
454 } else {
455 unsigned control = buf_get_u32(arm->core_cache
456 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
457
458 /* is this thread privileged? */
459 arm->core_mode = control & 1
460 ? ARM_MODE_USER_THREAD
461 : ARM_MODE_THREAD;
462
463 /* which stack is it using? */
464 if (control & 2)
465 arm->map = armv7m_psp_reg_map;
466 else
467 arm->map = armv7m_msp_reg_map;
468
469 armv7m->exception_number = 0;
470 }
471
472 if (armv7m->exception_number)
473 cortex_m_examine_exception_reason(target);
474
475 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
476 arm_mode_name(arm->core_mode),
477 buf_get_u32(arm->pc->value, 0, 32),
478 target_state_name(target));
479
480 if (armv7m->post_debug_entry) {
481 retval = armv7m->post_debug_entry(target);
482 if (retval != ERROR_OK)
483 return retval;
484 }
485
486 return ERROR_OK;
487 }
488
489 static int cortex_m_poll(struct target *target)
490 {
491 int detected_failure = ERROR_OK;
492 int retval = ERROR_OK;
493 enum target_state prev_target_state = target->state;
494 struct cortex_m_common *cortex_m = target_to_cm(target);
495 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
496
497 /* Read from Debug Halting Control and Status Register */
498 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
499 if (retval != ERROR_OK) {
500 target->state = TARGET_UNKNOWN;
501 return retval;
502 }
503
504 /* Recover from lockup. See ARMv7-M architecture spec,
505 * section B1.5.15 "Unrecoverable exception cases".
506 */
507 if (cortex_m->dcb_dhcsr & S_LOCKUP) {
508 LOG_ERROR("%s -- clearing lockup after double fault",
509 target_name(target));
510 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
511 target->debug_reason = DBG_REASON_DBGRQ;
512
513 /* We have to execute the rest (the "finally" equivalent, but
514 * still throw this exception again).
515 */
516 detected_failure = ERROR_FAIL;
517
518 /* refresh status bits */
519 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
520 if (retval != ERROR_OK)
521 return retval;
522 }
523
524 if (cortex_m->dcb_dhcsr & S_RESET_ST) {
525 target->state = TARGET_RESET;
526 return ERROR_OK;
527 }
528
529 if (target->state == TARGET_RESET) {
530 /* Cannot switch context while running so endreset is
531 * called with target->state == TARGET_RESET
532 */
533 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
534 cortex_m->dcb_dhcsr);
535 retval = cortex_m_endreset_event(target);
536 if (retval != ERROR_OK) {
537 target->state = TARGET_UNKNOWN;
538 return retval;
539 }
540 target->state = TARGET_RUNNING;
541 prev_target_state = TARGET_RUNNING;
542 }
543
544 if (cortex_m->dcb_dhcsr & S_HALT) {
545 target->state = TARGET_HALTED;
546
547 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
548 retval = cortex_m_debug_entry(target);
549 if (retval != ERROR_OK)
550 return retval;
551
552 if (arm_semihosting(target, &retval) != 0)
553 return retval;
554
555 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
556 }
557 if (prev_target_state == TARGET_DEBUG_RUNNING) {
558 LOG_DEBUG(" ");
559 retval = cortex_m_debug_entry(target);
560 if (retval != ERROR_OK)
561 return retval;
562
563 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
564 }
565 }
566
567 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
568 * How best to model low power modes?
569 */
570
571 if (target->state == TARGET_UNKNOWN) {
572 /* check if processor is retiring instructions */
573 if (cortex_m->dcb_dhcsr & S_RETIRE_ST) {
574 target->state = TARGET_RUNNING;
575 retval = ERROR_OK;
576 }
577 }
578
579 /* Did we detect a failure condition that we cleared? */
580 if (detected_failure != ERROR_OK)
581 retval = detected_failure;
582 return retval;
583 }
584
585 static int cortex_m_halt(struct target *target)
586 {
587 LOG_DEBUG("target->state: %s",
588 target_state_name(target));
589
590 if (target->state == TARGET_HALTED) {
591 LOG_DEBUG("target was already halted");
592 return ERROR_OK;
593 }
594
595 if (target->state == TARGET_UNKNOWN)
596 LOG_WARNING("target was in unknown state when halt was requested");
597
598 if (target->state == TARGET_RESET) {
599 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
600 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
601 return ERROR_TARGET_FAILURE;
602 } else {
603 /* we came here in a reset_halt or reset_init sequence
604 * debug entry was already prepared in cortex_m3_assert_reset()
605 */
606 target->debug_reason = DBG_REASON_DBGRQ;
607
608 return ERROR_OK;
609 }
610 }
611
612 /* Write to Debug Halting Control and Status Register */
613 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
614
615 target->debug_reason = DBG_REASON_DBGRQ;
616
617 return ERROR_OK;
618 }
619
620 static int cortex_m_soft_reset_halt(struct target *target)
621 {
622 struct cortex_m_common *cortex_m = target_to_cm(target);
623 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
624 uint32_t dcb_dhcsr = 0;
625 int retval, timeout = 0;
626
627 /* soft_reset_halt is deprecated on cortex_m as the same functionality
628 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
629 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
630 * core, not the peripherals */
631 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
632
633 /* Enter debug state on reset; restore DEMCR in endreset_event() */
634 retval = mem_ap_write_u32(swjdp, DCB_DEMCR,
635 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
636 if (retval != ERROR_OK)
637 return retval;
638
639 /* Request a core-only reset */
640 retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
641 AIRCR_VECTKEY | AIRCR_VECTRESET);
642 if (retval != ERROR_OK)
643 return retval;
644 target->state = TARGET_RESET;
645
646 /* registers are now invalid */
647 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
648
649 while (timeout < 100) {
650 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
651 if (retval == ERROR_OK) {
652 retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
653 &cortex_m->nvic_dfsr);
654 if (retval != ERROR_OK)
655 return retval;
656 if ((dcb_dhcsr & S_HALT)
657 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
658 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
659 "DFSR 0x%08x",
660 (unsigned) dcb_dhcsr,
661 (unsigned) cortex_m->nvic_dfsr);
662 cortex_m_poll(target);
663 /* FIXME restore user's vector catch config */
664 return ERROR_OK;
665 } else
666 LOG_DEBUG("waiting for system reset-halt, "
667 "DHCSR 0x%08x, %d ms",
668 (unsigned) dcb_dhcsr, timeout);
669 }
670 timeout++;
671 alive_sleep(1);
672 }
673
674 return ERROR_OK;
675 }
676
677 void cortex_m_enable_breakpoints(struct target *target)
678 {
679 struct breakpoint *breakpoint = target->breakpoints;
680
681 /* set any pending breakpoints */
682 while (breakpoint) {
683 if (!breakpoint->set)
684 cortex_m_set_breakpoint(target, breakpoint);
685 breakpoint = breakpoint->next;
686 }
687 }
688
689 static int cortex_m_resume(struct target *target, int current,
690 uint32_t address, int handle_breakpoints, int debug_execution)
691 {
692 struct armv7m_common *armv7m = target_to_armv7m(target);
693 struct breakpoint *breakpoint = NULL;
694 uint32_t resume_pc;
695 struct reg *r;
696
697 if (target->state != TARGET_HALTED) {
698 LOG_WARNING("target not halted");
699 return ERROR_TARGET_NOT_HALTED;
700 }
701
702 if (!debug_execution) {
703 target_free_all_working_areas(target);
704 cortex_m_enable_breakpoints(target);
705 cortex_m_enable_watchpoints(target);
706 }
707
708 if (debug_execution) {
709 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
710
711 /* Disable interrupts */
712 /* We disable interrupts in the PRIMASK register instead of
713 * masking with C_MASKINTS. This is probably the same issue
714 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
715 * in parallel with disabled interrupts can cause local faults
716 * to not be taken.
717 *
718 * REVISIT this clearly breaks non-debug execution, since the
719 * PRIMASK register state isn't saved/restored... workaround
720 * by never resuming app code after debug execution.
721 */
722 buf_set_u32(r->value, 0, 1, 1);
723 r->dirty = true;
724 r->valid = true;
725
726 /* Make sure we are in Thumb mode */
727 r = armv7m->arm.cpsr;
728 buf_set_u32(r->value, 24, 1, 1);
729 r->dirty = true;
730 r->valid = true;
731 }
732
733 /* current = 1: continue on current pc, otherwise continue at <address> */
734 r = armv7m->arm.pc;
735 if (!current) {
736 buf_set_u32(r->value, 0, 32, address);
737 r->dirty = true;
738 r->valid = true;
739 }
740
741 /* if we halted last time due to a bkpt instruction
742 * then we have to manually step over it, otherwise
743 * the core will break again */
744
745 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
746 && !debug_execution)
747 armv7m_maybe_skip_bkpt_inst(target, NULL);
748
749 resume_pc = buf_get_u32(r->value, 0, 32);
750
751 armv7m_restore_context(target);
752
753 /* the front-end may request us not to handle breakpoints */
754 if (handle_breakpoints) {
755 /* Single step past breakpoint at current address */
756 breakpoint = breakpoint_find(target, resume_pc);
757 if (breakpoint) {
758 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %" PRIu32 ")",
759 breakpoint->address,
760 breakpoint->unique_id);
761 cortex_m_unset_breakpoint(target, breakpoint);
762 cortex_m_single_step_core(target);
763 cortex_m_set_breakpoint(target, breakpoint);
764 }
765 }
766
767 /* Restart core */
768 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
769
770 target->debug_reason = DBG_REASON_NOTHALTED;
771
772 /* registers are now invalid */
773 register_cache_invalidate(armv7m->arm.core_cache);
774
775 if (!debug_execution) {
776 target->state = TARGET_RUNNING;
777 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
778 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
779 } else {
780 target->state = TARGET_DEBUG_RUNNING;
781 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
782 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
783 }
784
785 return ERROR_OK;
786 }
787
788 /* int irqstepcount = 0; */
789 static int cortex_m_step(struct target *target, int current,
790 uint32_t address, int handle_breakpoints)
791 {
792 struct cortex_m_common *cortex_m = target_to_cm(target);
793 struct armv7m_common *armv7m = &cortex_m->armv7m;
794 struct adiv5_dap *swjdp = armv7m->arm.dap;
795 struct breakpoint *breakpoint = NULL;
796 struct reg *pc = armv7m->arm.pc;
797 bool bkpt_inst_found = false;
798 int retval;
799 bool isr_timed_out = false;
800
801 if (target->state != TARGET_HALTED) {
802 LOG_WARNING("target not halted");
803 return ERROR_TARGET_NOT_HALTED;
804 }
805
806 /* current = 1: continue on current pc, otherwise continue at <address> */
807 if (!current)
808 buf_set_u32(pc->value, 0, 32, address);
809
810 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
811
812 /* the front-end may request us not to handle breakpoints */
813 if (handle_breakpoints) {
814 breakpoint = breakpoint_find(target, pc_value);
815 if (breakpoint)
816 cortex_m_unset_breakpoint(target, breakpoint);
817 }
818
819 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
820
821 target->debug_reason = DBG_REASON_SINGLESTEP;
822
823 armv7m_restore_context(target);
824
825 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
826
827 /* if no bkpt instruction is found at pc then we can perform
828 * a normal step, otherwise we have to manually step over the bkpt
829 * instruction - as such simulate a step */
830 if (bkpt_inst_found == false) {
831 /* Automatic ISR masking mode off: Just step over the next instruction */
832 if ((cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO))
833 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
834 else {
835 /* Process interrupts during stepping in a way they don't interfere
836 * debugging.
837 *
838 * Principle:
839 *
840 * Set a temporary break point at the current pc and let the core run
841 * with interrupts enabled. Pending interrupts get served and we run
842 * into the breakpoint again afterwards. Then we step over the next
843 * instruction with interrupts disabled.
844 *
845 * If the pending interrupts don't complete within time, we leave the
846 * core running. This may happen if the interrupts trigger faster
847 * than the core can process them or the handler doesn't return.
848 *
849 * If no more breakpoints are available we simply do a step with
850 * interrupts enabled.
851 *
852 */
853
854 /* 2012-09-29 ph
855 *
856 * If a break point is already set on the lower half word then a break point on
857 * the upper half word will not break again when the core is restarted. So we
858 * just step over the instruction with interrupts disabled.
859 *
860 * The documentation has no information about this, it was found by observation
861 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
862 * suffer from this problem.
863 *
864 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
865 * address has it always cleared. The former is done to indicate thumb mode
866 * to gdb.
867 *
868 */
869 if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
870 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
871 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
872 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
873 /* Re-enable interrupts */
874 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
875 }
876 else {
877
878 /* Set a temporary break point */
879 if (breakpoint)
880 retval = cortex_m_set_breakpoint(target, breakpoint);
881 else
882 retval = breakpoint_add(target, pc_value, 2, BKPT_TYPE_BY_ADDR(pc_value));
883 bool tmp_bp_set = (retval == ERROR_OK);
884
885 /* No more breakpoints left, just do a step */
886 if (!tmp_bp_set)
887 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
888 else {
889 /* Start the core */
890 LOG_DEBUG("Starting core to serve pending interrupts");
891 int64_t t_start = timeval_ms();
892 cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
893
894 /* Wait for pending handlers to complete or timeout */
895 do {
896 retval = mem_ap_read_atomic_u32(swjdp,
897 DCB_DHCSR,
898 &cortex_m->dcb_dhcsr);
899 if (retval != ERROR_OK) {
900 target->state = TARGET_UNKNOWN;
901 return retval;
902 }
903 isr_timed_out = ((timeval_ms() - t_start) > 500);
904 } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
905
906 /* only remove breakpoint if we created it */
907 if (breakpoint)
908 cortex_m_unset_breakpoint(target, breakpoint);
909 else {
910 /* Remove the temporary breakpoint */
911 breakpoint_remove(target, pc_value);
912 }
913
914 if (isr_timed_out) {
915 LOG_DEBUG("Interrupt handlers didn't complete within time, "
916 "leaving target running");
917 } else {
918 /* Step over next instruction with interrupts disabled */
919 cortex_m_write_debug_halt_mask(target,
920 C_HALT | C_MASKINTS,
921 0);
922 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
923 /* Re-enable interrupts */
924 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
925 }
926 }
927 }
928 }
929 }
930
931 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
932 if (retval != ERROR_OK)
933 return retval;
934
935 /* registers are now invalid */
936 register_cache_invalidate(armv7m->arm.core_cache);
937
938 if (breakpoint)
939 cortex_m_set_breakpoint(target, breakpoint);
940
941 if (isr_timed_out) {
942 /* Leave the core running. The user has to stop execution manually. */
943 target->debug_reason = DBG_REASON_NOTHALTED;
944 target->state = TARGET_RUNNING;
945 return ERROR_OK;
946 }
947
948 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
949 " nvic_icsr = 0x%" PRIx32,
950 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
951
952 retval = cortex_m_debug_entry(target);
953 if (retval != ERROR_OK)
954 return retval;
955 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
956
957 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
958 " nvic_icsr = 0x%" PRIx32,
959 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
960
961 return ERROR_OK;
962 }
963
964 static int cortex_m_assert_reset(struct target *target)
965 {
966 struct cortex_m_common *cortex_m = target_to_cm(target);
967 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
968 enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
969
970 LOG_DEBUG("target->state: %s",
971 target_state_name(target));
972
973 enum reset_types jtag_reset_config = jtag_get_reset_config();
974
975 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
976 /* allow scripts to override the reset event */
977
978 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
979 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
980 target->state = TARGET_RESET;
981
982 return ERROR_OK;
983 }
984
985 /* some cores support connecting while srst is asserted
986 * use that mode is it has been configured */
987
988 bool srst_asserted = false;
989
990 if ((jtag_reset_config & RESET_HAS_SRST) &&
991 (jtag_reset_config & RESET_SRST_NO_GATING)) {
992 adapter_assert_reset();
993 srst_asserted = true;
994 }
995
996 /* Enable debug requests */
997 int retval;
998 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
999 if (retval != ERROR_OK)
1000 return retval;
1001 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
1002 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
1003 if (retval != ERROR_OK)
1004 return retval;
1005 }
1006
1007 /* If the processor is sleeping in a WFI or WFE instruction, the
1008 * C_HALT bit must be asserted to regain control */
1009 if (cortex_m->dcb_dhcsr & S_SLEEP) {
1010 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
1011 if (retval != ERROR_OK)
1012 return retval;
1013 }
1014
1015 retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
1016 if (retval != ERROR_OK)
1017 return retval;
1018
1019 if (!target->reset_halt) {
1020 /* Set/Clear C_MASKINTS in a separate operation */
1021 if (cortex_m->dcb_dhcsr & C_MASKINTS) {
1022 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
1023 DBGKEY | C_DEBUGEN | C_HALT);
1024 if (retval != ERROR_OK)
1025 return retval;
1026 }
1027
1028 /* clear any debug flags before resuming */
1029 cortex_m_clear_halt(target);
1030
1031 /* clear C_HALT in dhcsr reg */
1032 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1033 } else {
1034 /* Halt in debug on reset; endreset_event() restores DEMCR.
1035 *
1036 * REVISIT catching BUSERR presumably helps to defend against
1037 * bad vector table entries. Should this include MMERR or
1038 * other flags too?
1039 */
1040 retval = mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
1041 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1042 if (retval != ERROR_OK)
1043 return retval;
1044 }
1045
1046 if (jtag_reset_config & RESET_HAS_SRST) {
1047 /* default to asserting srst */
1048 if (!srst_asserted)
1049 adapter_assert_reset();
1050 } else {
1051 /* Use a standard Cortex-M3 software reset mechanism.
1052 * We default to using VECRESET as it is supported on all current cores.
1053 * This has the disadvantage of not resetting the peripherals, so a
1054 * reset-init event handler is needed to perform any peripheral resets.
1055 */
1056 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1057 ? "SYSRESETREQ" : "VECTRESET");
1058
1059 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1060 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1061 "handler to reset any peripherals or configure hardware srst support.");
1062 }
1063
1064 retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
1065 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1066 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1067 if (retval != ERROR_OK)
1068 LOG_DEBUG("Ignoring AP write error right after reset");
1069
1070 retval = ahbap_debugport_init(swjdp);
1071 if (retval != ERROR_OK) {
1072 LOG_ERROR("DP initialisation failed");
1073 return retval;
1074 }
1075
1076 {
1077 /* I do not know why this is necessary, but it
1078 * fixes strange effects (step/resume cause NMI
1079 * after reset) on LM3S6918 -- Michael Schwingen
1080 */
1081 uint32_t tmp;
1082 retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
1083 if (retval != ERROR_OK)
1084 return retval;
1085 }
1086 }
1087
1088 target->state = TARGET_RESET;
1089 jtag_add_sleep(50000);
1090
1091 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1092
1093 if (target->reset_halt) {
1094 retval = target_halt(target);
1095 if (retval != ERROR_OK)
1096 return retval;
1097 }
1098
1099 return ERROR_OK;
1100 }
1101
1102 static int cortex_m_deassert_reset(struct target *target)
1103 {
1104 LOG_DEBUG("target->state: %s",
1105 target_state_name(target));
1106
1107 /* deassert reset lines */
1108 adapter_deassert_reset();
1109
1110 enum reset_types jtag_reset_config = jtag_get_reset_config();
1111
1112 if ((jtag_reset_config & RESET_HAS_SRST) &&
1113 !(jtag_reset_config & RESET_SRST_NO_GATING)) {
1114 int retval = ahbap_debugport_init(target_to_cm(target)->armv7m.arm.dap);
1115 if (retval != ERROR_OK) {
1116 LOG_ERROR("DP initialisation failed");
1117 return retval;
1118 }
1119 }
1120
1121 return ERROR_OK;
1122 }
1123
1124 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1125 {
1126 int retval;
1127 int fp_num = 0;
1128 struct cortex_m_common *cortex_m = target_to_cm(target);
1129 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1130
1131 if (breakpoint->set) {
1132 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1133 return ERROR_OK;
1134 }
1135
1136 if (cortex_m->auto_bp_type)
1137 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1138
1139 if (breakpoint->type == BKPT_HARD) {
1140 uint32_t fpcr_value;
1141 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1142 fp_num++;
1143 if (fp_num >= cortex_m->fp_num_code) {
1144 LOG_ERROR("Can not find free FPB Comparator!");
1145 return ERROR_FAIL;
1146 }
1147 breakpoint->set = fp_num + 1;
1148 fpcr_value = breakpoint->address | 1;
1149 if (cortex_m->fp_rev == 0) {
1150 uint32_t hilo;
1151 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1152 fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1153 } else if (cortex_m->fp_rev > 1) {
1154 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1155 return ERROR_FAIL;
1156 }
1157 comparator_list[fp_num].used = 1;
1158 comparator_list[fp_num].fpcr_value = fpcr_value;
1159 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1160 comparator_list[fp_num].fpcr_value);
1161 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1162 fp_num,
1163 comparator_list[fp_num].fpcr_value);
1164 if (!cortex_m->fpb_enabled) {
1165 LOG_DEBUG("FPB wasn't enabled, do it now");
1166 retval = cortex_m_enable_fpb(target);
1167 if (retval != ERROR_OK) {
1168 LOG_ERROR("Failed to enable the FPB");
1169 return retval;
1170 }
1171
1172 cortex_m->fpb_enabled = 1;
1173 }
1174 } else if (breakpoint->type == BKPT_SOFT) {
1175 uint8_t code[4];
1176
1177 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1178 * semihosting; don't use that. Otherwise the BKPT
1179 * parameter is arbitrary.
1180 */
1181 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1182 retval = target_read_memory(target,
1183 breakpoint->address & 0xFFFFFFFE,
1184 breakpoint->length, 1,
1185 breakpoint->orig_instr);
1186 if (retval != ERROR_OK)
1187 return retval;
1188 retval = target_write_memory(target,
1189 breakpoint->address & 0xFFFFFFFE,
1190 breakpoint->length, 1,
1191 code);
1192 if (retval != ERROR_OK)
1193 return retval;
1194 breakpoint->set = true;
1195 }
1196
1197 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1198 breakpoint->unique_id,
1199 (int)(breakpoint->type),
1200 breakpoint->address,
1201 breakpoint->length,
1202 breakpoint->set);
1203
1204 return ERROR_OK;
1205 }
1206
1207 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1208 {
1209 int retval;
1210 struct cortex_m_common *cortex_m = target_to_cm(target);
1211 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1212
1213 if (!breakpoint->set) {
1214 LOG_WARNING("breakpoint not set");
1215 return ERROR_OK;
1216 }
1217
1218 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1219 breakpoint->unique_id,
1220 (int)(breakpoint->type),
1221 breakpoint->address,
1222 breakpoint->length,
1223 breakpoint->set);
1224
1225 if (breakpoint->type == BKPT_HARD) {
1226 int fp_num = breakpoint->set - 1;
1227 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1228 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1229 return ERROR_OK;
1230 }
1231 comparator_list[fp_num].used = 0;
1232 comparator_list[fp_num].fpcr_value = 0;
1233 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1234 comparator_list[fp_num].fpcr_value);
1235 } else {
1236 /* restore original instruction (kept in target endianness) */
1237 if (breakpoint->length == 4) {
1238 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1,
1239 breakpoint->orig_instr);
1240 if (retval != ERROR_OK)
1241 return retval;
1242 } else {
1243 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1,
1244 breakpoint->orig_instr);
1245 if (retval != ERROR_OK)
1246 return retval;
1247 }
1248 }
1249 breakpoint->set = false;
1250
1251 return ERROR_OK;
1252 }
1253
1254 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1255 {
1256 struct cortex_m_common *cortex_m = target_to_cm(target);
1257
1258 if (cortex_m->auto_bp_type)
1259 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1260
1261 if (breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
1262 if (breakpoint->type == BKPT_HARD) {
1263 LOG_INFO("flash patch comparator requested outside code memory region");
1264 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1265 }
1266
1267 if (breakpoint->type == BKPT_SOFT) {
1268 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1269 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1270 }
1271 }
1272
1273 if ((breakpoint->type == BKPT_HARD) && (cortex_m->fp_code_available < 1)) {
1274 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1275 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1276 }
1277
1278 if (breakpoint->length == 3) {
1279 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1280 breakpoint->length = 2;
1281 }
1282
1283 if ((breakpoint->length != 2)) {
1284 LOG_INFO("only breakpoints of two bytes length supported");
1285 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1286 }
1287
1288 if (breakpoint->type == BKPT_HARD)
1289 cortex_m->fp_code_available--;
1290
1291 return cortex_m_set_breakpoint(target, breakpoint);
1292 }
1293
1294 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1295 {
1296 struct cortex_m_common *cortex_m = target_to_cm(target);
1297
1298 /* REVISIT why check? FBP can be updated with core running ... */
1299 if (target->state != TARGET_HALTED) {
1300 LOG_WARNING("target not halted");
1301 return ERROR_TARGET_NOT_HALTED;
1302 }
1303
1304 if (cortex_m->auto_bp_type)
1305 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1306
1307 if (breakpoint->set)
1308 cortex_m_unset_breakpoint(target, breakpoint);
1309
1310 if (breakpoint->type == BKPT_HARD)
1311 cortex_m->fp_code_available++;
1312
1313 return ERROR_OK;
1314 }
1315
1316 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1317 {
1318 int dwt_num = 0;
1319 uint32_t mask, temp;
1320 struct cortex_m_common *cortex_m = target_to_cm(target);
1321
1322 /* watchpoint params were validated earlier */
1323 mask = 0;
1324 temp = watchpoint->length;
1325 while (temp) {
1326 temp >>= 1;
1327 mask++;
1328 }
1329 mask--;
1330
1331 /* REVISIT Don't fully trust these "not used" records ... users
1332 * may set up breakpoints by hand, e.g. dual-address data value
1333 * watchpoint using comparator #1; comparator #0 matching cycle
1334 * count; send data trace info through ITM and TPIU; etc
1335 */
1336 struct cortex_m_dwt_comparator *comparator;
1337
1338 for (comparator = cortex_m->dwt_comparator_list;
1339 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1340 comparator++, dwt_num++)
1341 continue;
1342 if (dwt_num >= cortex_m->dwt_num_comp) {
1343 LOG_ERROR("Can not find free DWT Comparator");
1344 return ERROR_FAIL;
1345 }
1346 comparator->used = 1;
1347 watchpoint->set = dwt_num + 1;
1348
1349 comparator->comp = watchpoint->address;
1350 target_write_u32(target, comparator->dwt_comparator_address + 0,
1351 comparator->comp);
1352
1353 comparator->mask = mask;
1354 target_write_u32(target, comparator->dwt_comparator_address + 4,
1355 comparator->mask);
1356
1357 switch (watchpoint->rw) {
1358 case WPT_READ:
1359 comparator->function = 5;
1360 break;
1361 case WPT_WRITE:
1362 comparator->function = 6;
1363 break;
1364 case WPT_ACCESS:
1365 comparator->function = 7;
1366 break;
1367 }
1368 target_write_u32(target, comparator->dwt_comparator_address + 8,
1369 comparator->function);
1370
1371 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1372 watchpoint->unique_id, dwt_num,
1373 (unsigned) comparator->comp,
1374 (unsigned) comparator->mask,
1375 (unsigned) comparator->function);
1376 return ERROR_OK;
1377 }
1378
1379 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1380 {
1381 struct cortex_m_common *cortex_m = target_to_cm(target);
1382 struct cortex_m_dwt_comparator *comparator;
1383 int dwt_num;
1384
1385 if (!watchpoint->set) {
1386 LOG_WARNING("watchpoint (wpid: %d) not set",
1387 watchpoint->unique_id);
1388 return ERROR_OK;
1389 }
1390
1391 dwt_num = watchpoint->set - 1;
1392
1393 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1394 watchpoint->unique_id, dwt_num,
1395 (unsigned) watchpoint->address);
1396
1397 if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1398 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1399 return ERROR_OK;
1400 }
1401
1402 comparator = cortex_m->dwt_comparator_list + dwt_num;
1403 comparator->used = 0;
1404 comparator->function = 0;
1405 target_write_u32(target, comparator->dwt_comparator_address + 8,
1406 comparator->function);
1407
1408 watchpoint->set = false;
1409
1410 return ERROR_OK;
1411 }
1412
1413 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1414 {
1415 struct cortex_m_common *cortex_m = target_to_cm(target);
1416
1417 if (cortex_m->dwt_comp_available < 1) {
1418 LOG_DEBUG("no comparators?");
1419 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1420 }
1421
1422 /* hardware doesn't support data value masking */
1423 if (watchpoint->mask != ~(uint32_t)0) {
1424 LOG_DEBUG("watchpoint value masks not supported");
1425 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1426 }
1427
1428 /* hardware allows address masks of up to 32K */
1429 unsigned mask;
1430
1431 for (mask = 0; mask < 16; mask++) {
1432 if ((1u << mask) == watchpoint->length)
1433 break;
1434 }
1435 if (mask == 16) {
1436 LOG_DEBUG("unsupported watchpoint length");
1437 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1438 }
1439 if (watchpoint->address & ((1 << mask) - 1)) {
1440 LOG_DEBUG("watchpoint address is unaligned");
1441 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1442 }
1443
1444 /* Caller doesn't seem to be able to describe watching for data
1445 * values of zero; that flags "no value".
1446 *
1447 * REVISIT This DWT may well be able to watch for specific data
1448 * values. Requires comparator #1 to set DATAVMATCH and match
1449 * the data, and another comparator (DATAVADDR0) matching addr.
1450 */
1451 if (watchpoint->value) {
1452 LOG_DEBUG("data value watchpoint not YET supported");
1453 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1454 }
1455
1456 cortex_m->dwt_comp_available--;
1457 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1458
1459 return ERROR_OK;
1460 }
1461
1462 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1463 {
1464 struct cortex_m_common *cortex_m = target_to_cm(target);
1465
1466 /* REVISIT why check? DWT can be updated with core running ... */
1467 if (target->state != TARGET_HALTED) {
1468 LOG_WARNING("target not halted");
1469 return ERROR_TARGET_NOT_HALTED;
1470 }
1471
1472 if (watchpoint->set)
1473 cortex_m_unset_watchpoint(target, watchpoint);
1474
1475 cortex_m->dwt_comp_available++;
1476 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1477
1478 return ERROR_OK;
1479 }
1480
1481 void cortex_m_enable_watchpoints(struct target *target)
1482 {
1483 struct watchpoint *watchpoint = target->watchpoints;
1484
1485 /* set any pending watchpoints */
1486 while (watchpoint) {
1487 if (!watchpoint->set)
1488 cortex_m_set_watchpoint(target, watchpoint);
1489 watchpoint = watchpoint->next;
1490 }
1491 }
1492
1493 static int cortex_m_load_core_reg_u32(struct target *target,
1494 uint32_t num, uint32_t *value)
1495 {
1496 int retval;
1497
1498 /* NOTE: we "know" here that the register identifiers used
1499 * in the v7m header match the Cortex-M3 Debug Core Register
1500 * Selector values for R0..R15, xPSR, MSP, and PSP.
1501 */
1502 switch (num) {
1503 case 0 ... 18:
1504 /* read a normal core register */
1505 retval = cortexm_dap_read_coreregister_u32(target, value, num);
1506
1507 if (retval != ERROR_OK) {
1508 LOG_ERROR("JTAG failure %i", retval);
1509 return ERROR_JTAG_DEVICE_ERROR;
1510 }
1511 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
1512 break;
1513
1514 case ARMV7M_FPSCR:
1515 /* Floating-point Status and Registers */
1516 retval = target_write_u32(target, DCB_DCRSR, 0x21);
1517 if (retval != ERROR_OK)
1518 return retval;
1519 retval = target_read_u32(target, DCB_DCRDR, value);
1520 if (retval != ERROR_OK)
1521 return retval;
1522 LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value);
1523 break;
1524
1525 case ARMV7M_S0 ... ARMV7M_S31:
1526 /* Floating-point Status and Registers */
1527 retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
1528 if (retval != ERROR_OK)
1529 return retval;
1530 retval = target_read_u32(target, DCB_DCRDR, value);
1531 if (retval != ERROR_OK)
1532 return retval;
1533 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32,
1534 (int)(num - ARMV7M_S0), *value);
1535 break;
1536
1537 case ARMV7M_PRIMASK:
1538 case ARMV7M_BASEPRI:
1539 case ARMV7M_FAULTMASK:
1540 case ARMV7M_CONTROL:
1541 /* Cortex-M3 packages these four registers as bitfields
1542 * in one Debug Core register. So say r0 and r2 docs;
1543 * it was removed from r1 docs, but still works.
1544 */
1545 cortexm_dap_read_coreregister_u32(target, value, 20);
1546
1547 switch (num) {
1548 case ARMV7M_PRIMASK:
1549 *value = buf_get_u32((uint8_t *)value, 0, 1);
1550 break;
1551
1552 case ARMV7M_BASEPRI:
1553 *value = buf_get_u32((uint8_t *)value, 8, 8);
1554 break;
1555
1556 case ARMV7M_FAULTMASK:
1557 *value = buf_get_u32((uint8_t *)value, 16, 1);
1558 break;
1559
1560 case ARMV7M_CONTROL:
1561 *value = buf_get_u32((uint8_t *)value, 24, 2);
1562 break;
1563 }
1564
1565 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1566 break;
1567
1568 default:
1569 return ERROR_COMMAND_SYNTAX_ERROR;
1570 }
1571
1572 return ERROR_OK;
1573 }
1574
1575 static int cortex_m_store_core_reg_u32(struct target *target,
1576 uint32_t num, uint32_t value)
1577 {
1578 int retval;
1579 uint32_t reg;
1580 struct armv7m_common *armv7m = target_to_armv7m(target);
1581
1582 /* NOTE: we "know" here that the register identifiers used
1583 * in the v7m header match the Cortex-M3 Debug Core Register
1584 * Selector values for R0..R15, xPSR, MSP, and PSP.
1585 */
1586 switch (num) {
1587 case 0 ... 18:
1588 retval = cortexm_dap_write_coreregister_u32(target, value, num);
1589 if (retval != ERROR_OK) {
1590 struct reg *r;
1591
1592 LOG_ERROR("JTAG failure");
1593 r = armv7m->arm.core_cache->reg_list + num;
1594 r->dirty = r->valid;
1595 return ERROR_JTAG_DEVICE_ERROR;
1596 }
1597 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1598 break;
1599
1600 case ARMV7M_FPSCR:
1601 /* Floating-point Status and Registers */
1602 retval = target_write_u32(target, DCB_DCRDR, value);
1603 if (retval != ERROR_OK)
1604 return retval;
1605 retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
1606 if (retval != ERROR_OK)
1607 return retval;
1608 LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
1609 break;
1610
1611 case ARMV7M_S0 ... ARMV7M_S31:
1612 /* Floating-point Status and Registers */
1613 retval = target_write_u32(target, DCB_DCRDR, value);
1614 if (retval != ERROR_OK)
1615 return retval;
1616 retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
1617 if (retval != ERROR_OK)
1618 return retval;
1619 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32,
1620 (int)(num - ARMV7M_S0), value);
1621 break;
1622
1623 case ARMV7M_PRIMASK:
1624 case ARMV7M_BASEPRI:
1625 case ARMV7M_FAULTMASK:
1626 case ARMV7M_CONTROL:
1627 /* Cortex-M3 packages these four registers as bitfields
1628 * in one Debug Core register. So say r0 and r2 docs;
1629 * it was removed from r1 docs, but still works.
1630 */
1631 cortexm_dap_read_coreregister_u32(target, &reg, 20);
1632
1633 switch (num) {
1634 case ARMV7M_PRIMASK:
1635 buf_set_u32((uint8_t *)&reg, 0, 1, value);
1636 break;
1637
1638 case ARMV7M_BASEPRI:
1639 buf_set_u32((uint8_t *)&reg, 8, 8, value);
1640 break;
1641
1642 case ARMV7M_FAULTMASK:
1643 buf_set_u32((uint8_t *)&reg, 16, 1, value);
1644 break;
1645
1646 case ARMV7M_CONTROL:
1647 buf_set_u32((uint8_t *)&reg, 24, 2, value);
1648 break;
1649 }
1650
1651 cortexm_dap_write_coreregister_u32(target, reg, 20);
1652
1653 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1654 break;
1655
1656 default:
1657 return ERROR_COMMAND_SYNTAX_ERROR;
1658 }
1659
1660 return ERROR_OK;
1661 }
1662
1663 static int cortex_m_read_memory(struct target *target, uint32_t address,
1664 uint32_t size, uint32_t count, uint8_t *buffer)
1665 {
1666 struct armv7m_common *armv7m = target_to_armv7m(target);
1667 struct adiv5_dap *swjdp = armv7m->arm.dap;
1668
1669 if (armv7m->arm.is_armv6m) {
1670 /* armv6m does not handle unaligned memory access */
1671 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1672 return ERROR_TARGET_UNALIGNED_ACCESS;
1673 }
1674
1675 return mem_ap_read(swjdp, buffer, size, count, address, true);
1676 }
1677
1678 static int cortex_m_write_memory(struct target *target, uint32_t address,
1679 uint32_t size, uint32_t count, const uint8_t *buffer)
1680 {
1681 struct armv7m_common *armv7m = target_to_armv7m(target);
1682 struct adiv5_dap *swjdp = armv7m->arm.dap;
1683
1684 if (armv7m->arm.is_armv6m) {
1685 /* armv6m does not handle unaligned memory access */
1686 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1687 return ERROR_TARGET_UNALIGNED_ACCESS;
1688 }
1689
1690 return mem_ap_write(swjdp, buffer, size, count, address, true);
1691 }
1692
1693 static int cortex_m_init_target(struct command_context *cmd_ctx,
1694 struct target *target)
1695 {
1696 armv7m_build_reg_cache(target);
1697 return ERROR_OK;
1698 }
1699
1700 void cortex_m_deinit_target(struct target *target)
1701 {
1702 struct cortex_m_common *cortex_m = target_to_cm(target);
1703
1704 free(cortex_m->fp_comparator_list);
1705
1706 cortex_m_dwt_free(target);
1707 armv7m_free_reg_cache(target);
1708
1709 free(cortex_m);
1710 }
1711
1712 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1713 * on r/w if the core is not running, and clear on resume or reset ... or
1714 * at least, in a post_restore_context() method.
1715 */
1716
1717 struct dwt_reg_state {
1718 struct target *target;
1719 uint32_t addr;
1720 uint8_t value[4]; /* scratch/cache */
1721 };
1722
1723 static int cortex_m_dwt_get_reg(struct reg *reg)
1724 {
1725 struct dwt_reg_state *state = reg->arch_info;
1726
1727 uint32_t tmp;
1728 int retval = target_read_u32(state->target, state->addr, &tmp);
1729 if (retval != ERROR_OK)
1730 return retval;
1731
1732 buf_set_u32(state->value, 0, 32, tmp);
1733 return ERROR_OK;
1734 }
1735
1736 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1737 {
1738 struct dwt_reg_state *state = reg->arch_info;
1739
1740 return target_write_u32(state->target, state->addr,
1741 buf_get_u32(buf, 0, reg->size));
1742 }
1743
1744 struct dwt_reg {
1745 uint32_t addr;
1746 char *name;
1747 unsigned size;
1748 };
1749
1750 static struct dwt_reg dwt_base_regs[] = {
1751 { DWT_CTRL, "dwt_ctrl", 32, },
1752 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1753 * increments while the core is asleep.
1754 */
1755 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1756 /* plus some 8 bit counters, useful for profiling with TPIU */
1757 };
1758
1759 static struct dwt_reg dwt_comp[] = {
1760 #define DWT_COMPARATOR(i) \
1761 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1762 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1763 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1764 DWT_COMPARATOR(0),
1765 DWT_COMPARATOR(1),
1766 DWT_COMPARATOR(2),
1767 DWT_COMPARATOR(3),
1768 #undef DWT_COMPARATOR
1769 };
1770
1771 static const struct reg_arch_type dwt_reg_type = {
1772 .get = cortex_m_dwt_get_reg,
1773 .set = cortex_m_dwt_set_reg,
1774 };
1775
1776 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1777 {
1778 struct dwt_reg_state *state;
1779
1780 state = calloc(1, sizeof *state);
1781 if (!state)
1782 return;
1783 state->addr = d->addr;
1784 state->target = t;
1785
1786 r->name = d->name;
1787 r->size = d->size;
1788 r->value = state->value;
1789 r->arch_info = state;
1790 r->type = &dwt_reg_type;
1791 }
1792
1793 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1794 {
1795 uint32_t dwtcr;
1796 struct reg_cache *cache;
1797 struct cortex_m_dwt_comparator *comparator;
1798 int reg, i;
1799
1800 target_read_u32(target, DWT_CTRL, &dwtcr);
1801 if (!dwtcr) {
1802 LOG_DEBUG("no DWT");
1803 return;
1804 }
1805
1806 cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1807 cm->dwt_comp_available = cm->dwt_num_comp;
1808 cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1809 sizeof(struct cortex_m_dwt_comparator));
1810 if (!cm->dwt_comparator_list) {
1811 fail0:
1812 cm->dwt_num_comp = 0;
1813 LOG_ERROR("out of mem");
1814 return;
1815 }
1816
1817 cache = calloc(1, sizeof *cache);
1818 if (!cache) {
1819 fail1:
1820 free(cm->dwt_comparator_list);
1821 goto fail0;
1822 }
1823 cache->name = "Cortex-M DWT registers";
1824 cache->num_regs = 2 + cm->dwt_num_comp * 3;
1825 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1826 if (!cache->reg_list) {
1827 free(cache);
1828 goto fail1;
1829 }
1830
1831 for (reg = 0; reg < 2; reg++)
1832 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1833 dwt_base_regs + reg);
1834
1835 comparator = cm->dwt_comparator_list;
1836 for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
1837 int j;
1838
1839 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1840 for (j = 0; j < 3; j++, reg++)
1841 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1842 dwt_comp + 3 * i + j);
1843
1844 /* make sure we clear any watchpoints enabled on the target */
1845 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
1846 }
1847
1848 *register_get_last_cache_p(&target->reg_cache) = cache;
1849 cm->dwt_cache = cache;
1850
1851 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1852 dwtcr, cm->dwt_num_comp,
1853 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1854
1855 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1856 * implement single-address data value watchpoints ... so we
1857 * won't need to check it later, when asked to set one up.
1858 */
1859 }
1860
1861 static void cortex_m_dwt_free(struct target *target)
1862 {
1863 struct cortex_m_common *cm = target_to_cm(target);
1864 struct reg_cache *cache = cm->dwt_cache;
1865
1866 free(cm->dwt_comparator_list);
1867 cm->dwt_comparator_list = NULL;
1868
1869 if (cache) {
1870 register_unlink_cache(&target->reg_cache, cache);
1871
1872 if (cache->reg_list) {
1873 for (size_t i = 0; i < cache->num_regs; i++)
1874 free(cache->reg_list[i].arch_info);
1875 free(cache->reg_list);
1876 }
1877 free(cache);
1878 }
1879 cm->dwt_cache = NULL;
1880 }
1881
1882 #define MVFR0 0xe000ef40
1883 #define MVFR1 0xe000ef44
1884
1885 #define MVFR0_DEFAULT_M4 0x10110021
1886 #define MVFR1_DEFAULT_M4 0x11000011
1887
1888 int cortex_m_examine(struct target *target)
1889 {
1890 int retval;
1891 uint32_t cpuid, fpcr, mvfr0, mvfr1;
1892 int i;
1893 struct cortex_m_common *cortex_m = target_to_cm(target);
1894 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
1895 struct armv7m_common *armv7m = target_to_armv7m(target);
1896
1897 /* stlink shares the examine handler but does not support
1898 * all its calls */
1899 if (!armv7m->stlink) {
1900 retval = ahbap_debugport_init(swjdp);
1901 if (retval != ERROR_OK)
1902 return retval;
1903 }
1904
1905 if (!target_was_examined(target)) {
1906 target_set_examined(target);
1907
1908 /* Read from Device Identification Registers */
1909 retval = target_read_u32(target, CPUID, &cpuid);
1910 if (retval != ERROR_OK)
1911 return retval;
1912
1913 /* Get CPU Type */
1914 i = (cpuid >> 4) & 0xf;
1915
1916 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
1917 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
1918 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1919
1920 /* test for floating point feature on cortex-m4 */
1921 if (i == 4) {
1922 target_read_u32(target, MVFR0, &mvfr0);
1923 target_read_u32(target, MVFR1, &mvfr1);
1924
1925 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
1926 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
1927 armv7m->fp_feature = FPv4_SP;
1928 }
1929 } else if (i == 0) {
1930 /* Cortex-M0 does not support unaligned memory access */
1931 armv7m->arm.is_armv6m = true;
1932 }
1933
1934 if (armv7m->fp_feature != FPv4_SP &&
1935 armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
1936 /* free unavailable FPU registers */
1937 size_t idx;
1938
1939 for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
1940 idx < armv7m->arm.core_cache->num_regs;
1941 idx++) {
1942 free(armv7m->arm.core_cache->reg_list[idx].value);
1943 free(armv7m->arm.core_cache->reg_list[idx].feature);
1944 free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
1945 }
1946 armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
1947 }
1948
1949 if (i == 4 || i == 3) {
1950 /* Cortex-M3/M4 has 4096 bytes autoincrement range */
1951 armv7m->dap.tar_autoincr_block = (1 << 12);
1952 }
1953
1954 /* Configure trace modules */
1955 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
1956 if (retval != ERROR_OK)
1957 return retval;
1958
1959 if (armv7m->trace_config.config_type != DISABLED) {
1960 armv7m_trace_tpiu_config(target);
1961 armv7m_trace_itm_config(target);
1962 }
1963
1964 /* NOTE: FPB and DWT are both optional. */
1965
1966 /* Setup FPB */
1967 target_read_u32(target, FP_CTRL, &fpcr);
1968 cortex_m->auto_bp_type = 1;
1969 /* bits [14:12] and [7:4] */
1970 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
1971 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
1972 cortex_m->fp_code_available = cortex_m->fp_num_code;
1973 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
1974 Revision is zero base, fp_rev == 1 means Rev.2 ! */
1975 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
1976 free(cortex_m->fp_comparator_list);
1977 cortex_m->fp_comparator_list = calloc(
1978 cortex_m->fp_num_code + cortex_m->fp_num_lit,
1979 sizeof(struct cortex_m_fp_comparator));
1980 cortex_m->fpb_enabled = fpcr & 1;
1981 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
1982 cortex_m->fp_comparator_list[i].type =
1983 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1984 cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1985
1986 /* make sure we clear any breakpoints enabled on the target */
1987 target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
1988 }
1989 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
1990 fpcr,
1991 cortex_m->fp_num_code,
1992 cortex_m->fp_num_lit);
1993
1994 /* Setup DWT */
1995 cortex_m_dwt_free(target);
1996 cortex_m_dwt_setup(cortex_m, target);
1997
1998 /* These hardware breakpoints only work for code in flash! */
1999 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2000 target_name(target),
2001 cortex_m->fp_num_code,
2002 cortex_m->dwt_num_comp);
2003 }
2004
2005 return ERROR_OK;
2006 }
2007
2008 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2009 {
2010 struct armv7m_common *armv7m = target_to_armv7m(target);
2011 struct adiv5_dap *swjdp = armv7m->arm.dap;
2012 uint16_t dcrdr;
2013 uint8_t buf[2];
2014 int retval;
2015
2016 retval = mem_ap_read(swjdp, buf, 2, 1, DCB_DCRDR, false);
2017 if (retval != ERROR_OK)
2018 return retval;
2019
2020 dcrdr = target_buffer_get_u16(target, buf);
2021 *ctrl = (uint8_t)dcrdr;
2022 *value = (uint8_t)(dcrdr >> 8);
2023
2024 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2025
2026 /* write ack back to software dcc register
2027 * signify we have read data */
2028 if (dcrdr & (1 << 0)) {
2029 target_buffer_set_u16(target, buf, 0);
2030 retval = mem_ap_write(swjdp, buf, 2, 1, DCB_DCRDR, false);
2031 if (retval != ERROR_OK)
2032 return retval;
2033 }
2034
2035 return ERROR_OK;
2036 }
2037
2038 static int cortex_m_target_request_data(struct target *target,
2039 uint32_t size, uint8_t *buffer)
2040 {
2041 uint8_t data;
2042 uint8_t ctrl;
2043 uint32_t i;
2044
2045 for (i = 0; i < (size * 4); i++) {
2046 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2047 if (retval != ERROR_OK)
2048 return retval;
2049 buffer[i] = data;
2050 }
2051
2052 return ERROR_OK;
2053 }
2054
2055 static int cortex_m_handle_target_request(void *priv)
2056 {
2057 struct target *target = priv;
2058 if (!target_was_examined(target))
2059 return ERROR_OK;
2060
2061 if (!target->dbg_msg_enabled)
2062 return ERROR_OK;
2063
2064 if (target->state == TARGET_RUNNING) {
2065 uint8_t data;
2066 uint8_t ctrl;
2067 int retval;
2068
2069 retval = cortex_m_dcc_read(target, &data, &ctrl);
2070 if (retval != ERROR_OK)
2071 return retval;
2072
2073 /* check if we have data */
2074 if (ctrl & (1 << 0)) {
2075 uint32_t request;
2076
2077 /* we assume target is quick enough */
2078 request = data;
2079 for (int i = 1; i <= 3; i++) {
2080 retval = cortex_m_dcc_read(target, &data, &ctrl);
2081 if (retval != ERROR_OK)
2082 return retval;
2083 request |= ((uint32_t)data << (i * 8));
2084 }
2085 target_request(target, request);
2086 }
2087 }
2088
2089 return ERROR_OK;
2090 }
2091
2092 static int cortex_m_init_arch_info(struct target *target,
2093 struct cortex_m_common *cortex_m, struct jtag_tap *tap)
2094 {
2095 int retval;
2096 struct armv7m_common *armv7m = &cortex_m->armv7m;
2097
2098 armv7m_init_arch_info(target, armv7m);
2099
2100 /* prepare JTAG information for the new target */
2101 cortex_m->jtag_info.tap = tap;
2102 cortex_m->jtag_info.scann_size = 4;
2103
2104 /* default reset mode is to use srst if fitted
2105 * if not it will use CORTEX_M3_RESET_VECTRESET */
2106 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2107
2108 armv7m->arm.dap = &armv7m->dap;
2109
2110 /* Leave (only) generic DAP stuff for debugport_init(); */
2111 armv7m->dap.jtag_info = &cortex_m->jtag_info;
2112 armv7m->dap.memaccess_tck = 8;
2113
2114 /* Cortex-M3/M4 has 4096 bytes autoincrement range
2115 * but set a safe default to 1024 to support Cortex-M0
2116 * this will be changed in cortex_m3_examine if a M3/M4 is detected */
2117 armv7m->dap.tar_autoincr_block = (1 << 10);
2118
2119 /* register arch-specific functions */
2120 armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2121
2122 armv7m->post_debug_entry = NULL;
2123
2124 armv7m->pre_restore_context = NULL;
2125
2126 armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2127 armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2128
2129 target_register_timer_callback(cortex_m_handle_target_request, 1, 1, target);
2130
2131 retval = arm_jtag_setup_connection(&cortex_m->jtag_info);
2132 if (retval != ERROR_OK)
2133 return retval;
2134
2135 return ERROR_OK;
2136 }
2137
2138 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2139 {
2140 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2141
2142 cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2143 cortex_m_init_arch_info(target, cortex_m, target->tap);
2144
2145 return ERROR_OK;
2146 }
2147
2148 /*--------------------------------------------------------------------------*/
2149
2150 static int cortex_m_verify_pointer(struct command_context *cmd_ctx,
2151 struct cortex_m_common *cm)
2152 {
2153 if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2154 command_print(cmd_ctx, "target is not a Cortex-M");
2155 return ERROR_TARGET_INVALID;
2156 }
2157 return ERROR_OK;
2158 }
2159
2160 /*
2161 * Only stuff below this line should need to verify that its target
2162 * is a Cortex-M3. Everything else should have indirected through the
2163 * cortexm3_target structure, which is only used with CM3 targets.
2164 */
2165
2166 static const struct {
2167 char name[10];
2168 unsigned mask;
2169 } vec_ids[] = {
2170 { "hard_err", VC_HARDERR, },
2171 { "int_err", VC_INTERR, },
2172 { "bus_err", VC_BUSERR, },
2173 { "state_err", VC_STATERR, },
2174 { "chk_err", VC_CHKERR, },
2175 { "nocp_err", VC_NOCPERR, },
2176 { "mm_err", VC_MMERR, },
2177 { "reset", VC_CORERESET, },
2178 };
2179
2180 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2181 {
2182 struct target *target = get_current_target(CMD_CTX);
2183 struct cortex_m_common *cortex_m = target_to_cm(target);
2184 struct armv7m_common *armv7m = &cortex_m->armv7m;
2185 struct adiv5_dap *swjdp = armv7m->arm.dap;
2186 uint32_t demcr = 0;
2187 int retval;
2188
2189 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2190 if (retval != ERROR_OK)
2191 return retval;
2192
2193 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2194 if (retval != ERROR_OK)
2195 return retval;
2196
2197 if (CMD_ARGC > 0) {
2198 unsigned catch = 0;
2199
2200 if (CMD_ARGC == 1) {
2201 if (strcmp(CMD_ARGV[0], "all") == 0) {
2202 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2203 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2204 | VC_MMERR | VC_CORERESET;
2205 goto write;
2206 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2207 goto write;
2208 }
2209 while (CMD_ARGC-- > 0) {
2210 unsigned i;
2211 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2212 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2213 continue;
2214 catch |= vec_ids[i].mask;
2215 break;
2216 }
2217 if (i == ARRAY_SIZE(vec_ids)) {
2218 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2219 return ERROR_COMMAND_SYNTAX_ERROR;
2220 }
2221 }
2222 write:
2223 /* For now, armv7m->demcr only stores vector catch flags. */
2224 armv7m->demcr = catch;
2225
2226 demcr &= ~0xffff;
2227 demcr |= catch;
2228
2229 /* write, but don't assume it stuck (why not??) */
2230 retval = mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
2231 if (retval != ERROR_OK)
2232 return retval;
2233 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2234 if (retval != ERROR_OK)
2235 return retval;
2236
2237 /* FIXME be sure to clear DEMCR on clean server shutdown.
2238 * Otherwise the vector catch hardware could fire when there's
2239 * no debugger hooked up, causing much confusion...
2240 */
2241 }
2242
2243 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2244 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2245 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2246 }
2247
2248 return ERROR_OK;
2249 }
2250
2251 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2252 {
2253 struct target *target = get_current_target(CMD_CTX);
2254 struct cortex_m_common *cortex_m = target_to_cm(target);
2255 int retval;
2256
2257 static const Jim_Nvp nvp_maskisr_modes[] = {
2258 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2259 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2260 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2261 { .name = NULL, .value = -1 },
2262 };
2263 const Jim_Nvp *n;
2264
2265
2266 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2267 if (retval != ERROR_OK)
2268 return retval;
2269
2270 if (target->state != TARGET_HALTED) {
2271 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2272 return ERROR_OK;
2273 }
2274
2275 if (CMD_ARGC > 0) {
2276 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2277 if (n->name == NULL)
2278 return ERROR_COMMAND_SYNTAX_ERROR;
2279 cortex_m->isrmasking_mode = n->value;
2280
2281
2282 if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
2283 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
2284 else
2285 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
2286 }
2287
2288 n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2289 command_print(CMD_CTX, "cortex_m interrupt mask %s", n->name);
2290
2291 return ERROR_OK;
2292 }
2293
2294 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2295 {
2296 struct target *target = get_current_target(CMD_CTX);
2297 struct cortex_m_common *cortex_m = target_to_cm(target);
2298 int retval;
2299 char *reset_config;
2300
2301 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2302 if (retval != ERROR_OK)
2303 return retval;
2304
2305 if (CMD_ARGC > 0) {
2306 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2307 cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2308 else if (strcmp(*CMD_ARGV, "vectreset") == 0)
2309 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2310 }
2311
2312 switch (cortex_m->soft_reset_config) {
2313 case CORTEX_M_RESET_SYSRESETREQ:
2314 reset_config = "sysresetreq";
2315 break;
2316
2317 case CORTEX_M_RESET_VECTRESET:
2318 reset_config = "vectreset";
2319 break;
2320
2321 default:
2322 reset_config = "unknown";
2323 break;
2324 }
2325
2326 command_print(CMD_CTX, "cortex_m reset_config %s", reset_config);
2327
2328 return ERROR_OK;
2329 }
2330
2331 static const struct command_registration cortex_m_exec_command_handlers[] = {
2332 {
2333 .name = "maskisr",
2334 .handler = handle_cortex_m_mask_interrupts_command,
2335 .mode = COMMAND_EXEC,
2336 .help = "mask cortex_m interrupts",
2337 .usage = "['auto'|'on'|'off']",
2338 },
2339 {
2340 .name = "vector_catch",
2341 .handler = handle_cortex_m_vector_catch_command,
2342 .mode = COMMAND_EXEC,
2343 .help = "configure hardware vectors to trigger debug entry",
2344 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2345 },
2346 {
2347 .name = "reset_config",
2348 .handler = handle_cortex_m_reset_config_command,
2349 .mode = COMMAND_ANY,
2350 .help = "configure software reset handling",
2351 .usage = "['srst'|'sysresetreq'|'vectreset']",
2352 },
2353 COMMAND_REGISTRATION_DONE
2354 };
2355 static const struct command_registration cortex_m_command_handlers[] = {
2356 {
2357 .chain = armv7m_command_handlers,
2358 },
2359 {
2360 .chain = armv7m_trace_command_handlers,
2361 },
2362 {
2363 .name = "cortex_m",
2364 .mode = COMMAND_EXEC,
2365 .help = "Cortex-M command group",
2366 .usage = "",
2367 .chain = cortex_m_exec_command_handlers,
2368 },
2369 COMMAND_REGISTRATION_DONE
2370 };
2371
2372 struct target_type cortexm_target = {
2373 .name = "cortex_m",
2374 .deprecated_name = "cortex_m3",
2375
2376 .poll = cortex_m_poll,
2377 .arch_state = armv7m_arch_state,
2378
2379 .target_request_data = cortex_m_target_request_data,
2380
2381 .halt = cortex_m_halt,
2382 .resume = cortex_m_resume,
2383 .step = cortex_m_step,
2384
2385 .assert_reset = cortex_m_assert_reset,
2386 .deassert_reset = cortex_m_deassert_reset,
2387 .soft_reset_halt = cortex_m_soft_reset_halt,
2388
2389 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2390
2391 .read_memory = cortex_m_read_memory,
2392 .write_memory = cortex_m_write_memory,
2393 .checksum_memory = armv7m_checksum_memory,
2394 .blank_check_memory = armv7m_blank_check_memory,
2395
2396 .run_algorithm = armv7m_run_algorithm,
2397 .start_algorithm = armv7m_start_algorithm,
2398 .wait_algorithm = armv7m_wait_algorithm,
2399
2400 .add_breakpoint = cortex_m_add_breakpoint,
2401 .remove_breakpoint = cortex_m_remove_breakpoint,
2402 .add_watchpoint = cortex_m_add_watchpoint,
2403 .remove_watchpoint = cortex_m_remove_watchpoint,
2404
2405 .commands = cortex_m_command_handlers,
2406 .target_create = cortex_m_target_create,
2407 .init_target = cortex_m_init_target,
2408 .examine = cortex_m_examine,
2409 .deinit_target = cortex_m_deinit_target,
2410 };
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