1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
29 ***************************************************************************/
34 #include "jtag/interface.h"
35 #include "breakpoints.h"
37 #include "target_request.h"
38 #include "target_type.h"
39 #include "arm_disassembler.h"
41 #include "arm_opcodes.h"
42 #include "arm_semihosting.h"
43 #include <helper/time_support.h>
45 /* NOTE: most of this should work fine for the Cortex-M1 and
46 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
47 * Some differences: M0/M1 doesn't have FBP remapping or the
48 * DWT tracing/profiling support. (So the cycle counter will
49 * not be usable; the other stuff isn't currently used here.)
51 * Although there are some workarounds for errata seen only in r0p0
52 * silicon, such old parts are hard to find and thus not much tested
57 * Returns the type of a break point required by address location
59 #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
62 /* forward declarations */
63 static int cortex_m3_store_core_reg_u32(struct target
*target
,
64 uint32_t num
, uint32_t value
);
66 static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap
*swjdp
,
67 uint32_t *value
, int regnum
)
72 /* because the DCB_DCRDR is used for the emulated dcc channel
73 * we have to save/restore the DCB_DCRDR when used */
75 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
76 if (retval
!= ERROR_OK
)
79 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
80 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
81 if (retval
!= ERROR_OK
)
83 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
);
84 if (retval
!= ERROR_OK
)
87 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
88 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
89 if (retval
!= ERROR_OK
)
91 retval
= dap_queue_ap_read(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
92 if (retval
!= ERROR_OK
)
95 retval
= dap_run(swjdp
);
96 if (retval
!= ERROR_OK
)
99 /* restore DCB_DCRDR - this needs to be in a seperate
100 * transaction otherwise the emulated DCC channel breaks */
101 if (retval
== ERROR_OK
)
102 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
107 static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap
*swjdp
,
108 uint32_t value
, int regnum
)
113 /* because the DCB_DCRDR is used for the emulated dcc channel
114 * we have to save/restore the DCB_DCRDR when used */
116 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
117 if (retval
!= ERROR_OK
)
120 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
121 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
122 if (retval
!= ERROR_OK
)
124 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
125 if (retval
!= ERROR_OK
)
128 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
129 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
130 if (retval
!= ERROR_OK
)
132 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
| DCRSR_WnR
);
133 if (retval
!= ERROR_OK
)
136 retval
= dap_run(swjdp
);
137 if (retval
!= ERROR_OK
)
140 /* restore DCB_DCRDR - this needs to be in a seperate
141 * transaction otherwise the emulated DCC channel breaks */
142 if (retval
== ERROR_OK
)
143 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
148 static int cortex_m3_write_debug_halt_mask(struct target
*target
,
149 uint32_t mask_on
, uint32_t mask_off
)
151 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
152 struct adiv5_dap
*swjdp
= cortex_m3
->armv7m
.arm
.dap
;
154 /* mask off status bits */
155 cortex_m3
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
156 /* create new register mask */
157 cortex_m3
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
159 return mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, cortex_m3
->dcb_dhcsr
);
162 static int cortex_m3_clear_halt(struct target
*target
)
164 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
165 struct adiv5_dap
*swjdp
= cortex_m3
->armv7m
.arm
.dap
;
168 /* clear step if any */
169 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
171 /* Read Debug Fault Status Register */
172 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m3
->nvic_dfsr
);
173 if (retval
!= ERROR_OK
)
176 /* Clear Debug Fault Status */
177 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_DFSR
, cortex_m3
->nvic_dfsr
);
178 if (retval
!= ERROR_OK
)
180 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m3
->nvic_dfsr
);
185 static int cortex_m3_single_step_core(struct target
*target
)
187 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
188 struct adiv5_dap
*swjdp
= cortex_m3
->armv7m
.arm
.dap
;
192 /* backup dhcsr reg */
193 dhcsr_save
= cortex_m3
->dcb_dhcsr
;
195 /* Mask interrupts before clearing halt, if done already. This avoids
196 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
197 * HALT can put the core into an unknown state.
199 if (!(cortex_m3
->dcb_dhcsr
& C_MASKINTS
)) {
200 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
201 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
202 if (retval
!= ERROR_OK
)
205 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
206 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
207 if (retval
!= ERROR_OK
)
211 /* restore dhcsr reg */
212 cortex_m3
->dcb_dhcsr
= dhcsr_save
;
213 cortex_m3_clear_halt(target
);
218 static int cortex_m3_endreset_event(struct target
*target
)
223 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
224 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
225 struct adiv5_dap
*swjdp
= cortex_m3
->armv7m
.arm
.dap
;
226 struct cortex_m3_fp_comparator
*fp_list
= cortex_m3
->fp_comparator_list
;
227 struct cortex_m3_dwt_comparator
*dwt_list
= cortex_m3
->dwt_comparator_list
;
229 /* REVISIT The four debug monitor bits are currently ignored... */
230 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &dcb_demcr
);
231 if (retval
!= ERROR_OK
)
233 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"", dcb_demcr
);
235 /* this register is used for emulated dcc channel */
236 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
237 if (retval
!= ERROR_OK
)
240 /* Enable debug requests */
241 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
242 if (retval
!= ERROR_OK
)
244 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
)) {
245 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
246 if (retval
!= ERROR_OK
)
250 /* clear any interrupt masking */
251 cortex_m3_write_debug_halt_mask(target
, 0, C_MASKINTS
);
253 /* Enable features controlled by ITM and DWT blocks, and catch only
254 * the vectors we were told to pay attention to.
256 * Target firmware is responsible for all fault handling policy
257 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
258 * or manual updates to the NVIC SHCSR and CCR registers.
260 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
261 if (retval
!= ERROR_OK
)
264 /* Paranoia: evidently some (early?) chips don't preserve all the
265 * debug state (including FBP, DWT, etc) across reset...
269 retval
= target_write_u32(target
, FP_CTRL
, 3);
270 if (retval
!= ERROR_OK
)
273 cortex_m3
->fpb_enabled
= 1;
275 /* Restore FPB registers */
276 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++) {
277 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
278 if (retval
!= ERROR_OK
)
282 /* Restore DWT registers */
283 for (i
= 0; i
< cortex_m3
->dwt_num_comp
; i
++) {
284 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
286 if (retval
!= ERROR_OK
)
288 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
290 if (retval
!= ERROR_OK
)
292 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
293 dwt_list
[i
].function
);
294 if (retval
!= ERROR_OK
)
297 retval
= dap_run(swjdp
);
298 if (retval
!= ERROR_OK
)
301 register_cache_invalidate(armv7m
->arm
.core_cache
);
303 /* make sure we have latest dhcsr flags */
304 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
309 static int cortex_m3_examine_debug_reason(struct target
*target
)
311 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
313 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
314 * only check the debug reason if we don't know it already */
316 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
317 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
318 if (cortex_m3
->nvic_dfsr
& DFSR_BKPT
) {
319 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
320 if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
321 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
322 } else if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
323 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
324 else if (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
)
325 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
326 else /* EXTERNAL, HALTED */
327 target
->debug_reason
= DBG_REASON_UNDEFINED
;
333 static int cortex_m3_examine_exception_reason(struct target
*target
)
335 uint32_t shcsr
= 0, except_sr
= 0, cfsr
= -1, except_ar
= -1;
336 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
337 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
340 retval
= mem_ap_read_u32(swjdp
, NVIC_SHCSR
, &shcsr
);
341 if (retval
!= ERROR_OK
)
343 switch (armv7m
->exception_number
) {
346 case 3: /* Hard Fault */
347 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_HFSR
, &except_sr
);
348 if (retval
!= ERROR_OK
)
350 if (except_sr
& 0x40000000) {
351 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &cfsr
);
352 if (retval
!= ERROR_OK
)
356 case 4: /* Memory Management */
357 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
358 if (retval
!= ERROR_OK
)
360 retval
= mem_ap_read_u32(swjdp
, NVIC_MMFAR
, &except_ar
);
361 if (retval
!= ERROR_OK
)
364 case 5: /* Bus Fault */
365 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
366 if (retval
!= ERROR_OK
)
368 retval
= mem_ap_read_u32(swjdp
, NVIC_BFAR
, &except_ar
);
369 if (retval
!= ERROR_OK
)
372 case 6: /* Usage Fault */
373 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
374 if (retval
!= ERROR_OK
)
377 case 11: /* SVCall */
379 case 12: /* Debug Monitor */
380 retval
= mem_ap_read_u32(swjdp
, NVIC_DFSR
, &except_sr
);
381 if (retval
!= ERROR_OK
)
384 case 14: /* PendSV */
386 case 15: /* SysTick */
392 retval
= dap_run(swjdp
);
393 if (retval
== ERROR_OK
)
394 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
395 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
396 armv7m_exception_string(armv7m
->exception_number
),
397 shcsr
, except_sr
, cfsr
, except_ar
);
401 static int cortex_m3_debug_entry(struct target
*target
)
406 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
407 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
408 struct arm
*arm
= &armv7m
->arm
;
409 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
414 cortex_m3_clear_halt(target
);
415 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
416 if (retval
!= ERROR_OK
)
419 retval
= armv7m
->examine_debug_reason(target
);
420 if (retval
!= ERROR_OK
)
423 /* Examine target state and mode
424 * First load register accessible through core debug port */
425 int num_regs
= arm
->core_cache
->num_regs
;
427 for (i
= 0; i
< num_regs
; i
++) {
428 r
= &armv7m
->arm
.core_cache
->reg_list
[i
];
430 arm
->read_core_reg(target
, r
, i
, ARM_MODE_ANY
);
433 r
= arm
->core_cache
->reg_list
+ ARMV7M_xPSR
;
434 xPSR
= buf_get_u32(r
->value
, 0, 32);
436 #ifdef ARMV7_GDB_HACKS
437 /* FIXME this breaks on scan chains with more than one Cortex-M3.
438 * Instead, each CM3 should have its own dummy value...
440 /* copy real xpsr reg for gdb, setting thumb bit */
441 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 0, 32, xPSR
);
442 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 5, 1, 1);
443 armv7m_gdb_dummy_cpsr_reg
.valid
= r
->valid
;
444 armv7m_gdb_dummy_cpsr_reg
.dirty
= r
->dirty
;
447 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
450 cortex_m3_store_core_reg_u32(target
, 16, xPSR
& ~0xff);
453 /* Are we in an exception handler */
455 armv7m
->exception_number
= (xPSR
& 0x1FF);
457 arm
->core_mode
= ARM_MODE_HANDLER
;
458 arm
->map
= armv7m_msp_reg_map
;
460 unsigned control
= buf_get_u32(arm
->core_cache
461 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 2);
463 /* is this thread privileged? */
464 arm
->core_mode
= control
& 1
465 ? ARM_MODE_USER_THREAD
468 /* which stack is it using? */
470 arm
->map
= armv7m_psp_reg_map
;
472 arm
->map
= armv7m_msp_reg_map
;
474 armv7m
->exception_number
= 0;
477 if (armv7m
->exception_number
)
478 cortex_m3_examine_exception_reason(target
);
480 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
481 arm_mode_name(arm
->core_mode
),
482 *(uint32_t *)(arm
->pc
->value
),
483 target_state_name(target
));
485 if (armv7m
->post_debug_entry
) {
486 retval
= armv7m
->post_debug_entry(target
);
487 if (retval
!= ERROR_OK
)
494 static int cortex_m3_poll(struct target
*target
)
496 int detected_failure
= ERROR_OK
;
497 int retval
= ERROR_OK
;
498 enum target_state prev_target_state
= target
->state
;
499 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
500 struct adiv5_dap
*swjdp
= cortex_m3
->armv7m
.arm
.dap
;
502 /* Read from Debug Halting Control and Status Register */
503 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
504 if (retval
!= ERROR_OK
) {
505 target
->state
= TARGET_UNKNOWN
;
509 /* Recover from lockup. See ARMv7-M architecture spec,
510 * section B1.5.15 "Unrecoverable exception cases".
512 if (cortex_m3
->dcb_dhcsr
& S_LOCKUP
) {
513 LOG_ERROR("%s -- clearing lockup after double fault",
514 target_name(target
));
515 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
516 target
->debug_reason
= DBG_REASON_DBGRQ
;
518 /* We have to execute the rest (the "finally" equivalent, but
519 * still throw this exception again).
521 detected_failure
= ERROR_FAIL
;
523 /* refresh status bits */
524 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
525 if (retval
!= ERROR_OK
)
529 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
) {
530 /* check if still in reset */
531 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
532 if (retval
!= ERROR_OK
)
535 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
) {
536 target
->state
= TARGET_RESET
;
541 if (target
->state
== TARGET_RESET
) {
542 /* Cannot switch context while running so endreset is
543 * called with target->state == TARGET_RESET
545 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
546 cortex_m3
->dcb_dhcsr
);
547 cortex_m3_endreset_event(target
);
548 target
->state
= TARGET_RUNNING
;
549 prev_target_state
= TARGET_RUNNING
;
552 if (cortex_m3
->dcb_dhcsr
& S_HALT
) {
553 target
->state
= TARGET_HALTED
;
555 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
)) {
556 retval
= cortex_m3_debug_entry(target
);
557 if (retval
!= ERROR_OK
)
560 if (arm_semihosting(target
, &retval
) != 0)
563 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
565 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
567 retval
= cortex_m3_debug_entry(target
);
568 if (retval
!= ERROR_OK
)
571 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
575 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
576 * How best to model low power modes?
579 if (target
->state
== TARGET_UNKNOWN
) {
580 /* check if processor is retiring instructions */
581 if (cortex_m3
->dcb_dhcsr
& S_RETIRE_ST
) {
582 target
->state
= TARGET_RUNNING
;
587 /* Did we detect a failure condition that we cleared? */
588 if (detected_failure
!= ERROR_OK
)
589 retval
= detected_failure
;
593 static int cortex_m3_halt(struct target
*target
)
595 LOG_DEBUG("target->state: %s",
596 target_state_name(target
));
598 if (target
->state
== TARGET_HALTED
) {
599 LOG_DEBUG("target was already halted");
603 if (target
->state
== TARGET_UNKNOWN
)
604 LOG_WARNING("target was in unknown state when halt was requested");
606 if (target
->state
== TARGET_RESET
) {
607 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
608 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
609 return ERROR_TARGET_FAILURE
;
611 /* we came here in a reset_halt or reset_init sequence
612 * debug entry was already prepared in cortex_m3_assert_reset()
614 target
->debug_reason
= DBG_REASON_DBGRQ
;
620 /* Write to Debug Halting Control and Status Register */
621 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
623 target
->debug_reason
= DBG_REASON_DBGRQ
;
628 static int cortex_m3_soft_reset_halt(struct target
*target
)
630 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
631 struct adiv5_dap
*swjdp
= cortex_m3
->armv7m
.arm
.dap
;
632 uint32_t dcb_dhcsr
= 0;
633 int retval
, timeout
= 0;
635 /* soft_reset_halt is deprecated on cortex_m as the same functionality
636 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
637 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
638 * core, not the peripherals */
639 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
641 /* Enter debug state on reset; restore DEMCR in endreset_event() */
642 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
,
643 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
644 if (retval
!= ERROR_OK
)
647 /* Request a core-only reset */
648 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
649 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
650 if (retval
!= ERROR_OK
)
652 target
->state
= TARGET_RESET
;
654 /* registers are now invalid */
655 register_cache_invalidate(cortex_m3
->armv7m
.arm
.core_cache
);
657 while (timeout
< 100) {
658 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &dcb_dhcsr
);
659 if (retval
== ERROR_OK
) {
660 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
,
661 &cortex_m3
->nvic_dfsr
);
662 if (retval
!= ERROR_OK
)
664 if ((dcb_dhcsr
& S_HALT
)
665 && (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
)) {
666 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
668 (unsigned) dcb_dhcsr
,
669 (unsigned) cortex_m3
->nvic_dfsr
);
670 cortex_m3_poll(target
);
671 /* FIXME restore user's vector catch config */
674 LOG_DEBUG("waiting for system reset-halt, "
675 "DHCSR 0x%08x, %d ms",
676 (unsigned) dcb_dhcsr
, timeout
);
685 void cortex_m3_enable_breakpoints(struct target
*target
)
687 struct breakpoint
*breakpoint
= target
->breakpoints
;
689 /* set any pending breakpoints */
691 if (!breakpoint
->set
)
692 cortex_m3_set_breakpoint(target
, breakpoint
);
693 breakpoint
= breakpoint
->next
;
697 static int cortex_m3_resume(struct target
*target
, int current
,
698 uint32_t address
, int handle_breakpoints
, int debug_execution
)
700 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
701 struct breakpoint
*breakpoint
= NULL
;
705 if (target
->state
!= TARGET_HALTED
) {
706 LOG_WARNING("target not halted");
707 return ERROR_TARGET_NOT_HALTED
;
710 if (!debug_execution
) {
711 target_free_all_working_areas(target
);
712 cortex_m3_enable_breakpoints(target
);
713 cortex_m3_enable_watchpoints(target
);
716 if (debug_execution
) {
717 r
= armv7m
->arm
.core_cache
->reg_list
+ ARMV7M_PRIMASK
;
719 /* Disable interrupts */
720 /* We disable interrupts in the PRIMASK register instead of
721 * masking with C_MASKINTS. This is probably the same issue
722 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
723 * in parallel with disabled interrupts can cause local faults
726 * REVISIT this clearly breaks non-debug execution, since the
727 * PRIMASK register state isn't saved/restored... workaround
728 * by never resuming app code after debug execution.
730 buf_set_u32(r
->value
, 0, 1, 1);
734 /* Make sure we are in Thumb mode */
735 r
= armv7m
->arm
.core_cache
->reg_list
+ ARMV7M_xPSR
;
736 buf_set_u32(r
->value
, 24, 1, 1);
741 /* current = 1: continue on current pc, otherwise continue at <address> */
744 buf_set_u32(r
->value
, 0, 32, address
);
749 /* if we halted last time due to a bkpt instruction
750 * then we have to manually step over it, otherwise
751 * the core will break again */
753 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
755 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
757 resume_pc
= buf_get_u32(r
->value
, 0, 32);
759 armv7m_restore_context(target
);
761 /* the front-end may request us not to handle breakpoints */
762 if (handle_breakpoints
) {
763 /* Single step past breakpoint at current address */
764 breakpoint
= breakpoint_find(target
, resume_pc
);
766 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (ID: %d)",
768 breakpoint
->unique_id
);
769 cortex_m3_unset_breakpoint(target
, breakpoint
);
770 cortex_m3_single_step_core(target
);
771 cortex_m3_set_breakpoint(target
, breakpoint
);
776 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
778 target
->debug_reason
= DBG_REASON_NOTHALTED
;
780 /* registers are now invalid */
781 register_cache_invalidate(armv7m
->arm
.core_cache
);
783 if (!debug_execution
) {
784 target
->state
= TARGET_RUNNING
;
785 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
786 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
788 target
->state
= TARGET_DEBUG_RUNNING
;
789 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
790 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
796 /* int irqstepcount = 0; */
797 static int cortex_m3_step(struct target
*target
, int current
,
798 uint32_t address
, int handle_breakpoints
)
800 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
801 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
802 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
803 struct breakpoint
*breakpoint
= NULL
;
804 struct reg
*pc
= armv7m
->arm
.pc
;
805 bool bkpt_inst_found
= false;
807 bool isr_timed_out
= false;
809 if (target
->state
!= TARGET_HALTED
) {
810 LOG_WARNING("target not halted");
811 return ERROR_TARGET_NOT_HALTED
;
814 /* current = 1: continue on current pc, otherwise continue at <address> */
816 buf_set_u32(pc
->value
, 0, 32, address
);
818 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
820 /* the front-end may request us not to handle breakpoints */
821 if (handle_breakpoints
) {
822 breakpoint
= breakpoint_find(target
, pc_value
);
824 cortex_m3_unset_breakpoint(target
, breakpoint
);
827 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
829 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
831 armv7m_restore_context(target
);
833 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
835 /* if no bkpt instruction is found at pc then we can perform
836 * a normal step, otherwise we have to manually step over the bkpt
837 * instruction - as such simulate a step */
838 if (bkpt_inst_found
== false) {
839 /* Automatic ISR masking mode off: Just step over the next instruction */
840 if ((cortex_m3
->isrmasking_mode
!= CORTEX_M3_ISRMASK_AUTO
))
841 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
843 /* Process interrupts during stepping in a way they don't interfere
848 * Set a temporary break point at the current pc and let the core run
849 * with interrupts enabled. Pending interrupts get served and we run
850 * into the breakpoint again afterwards. Then we step over the next
851 * instruction with interrupts disabled.
853 * If the pending interrupts don't complete within time, we leave the
854 * core running. This may happen if the interrupts trigger faster
855 * than the core can process them or the handler doesn't return.
857 * If no more breakpoints are available we simply do a step with
858 * interrupts enabled.
864 * If a break point is already set on the lower half word then a break point on
865 * the upper half word will not break again when the core is restarted. So we
866 * just step over the instruction with interrupts disabled.
868 * The documentation has no information about this, it was found by observation
869 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
870 * suffer from this problem.
872 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
873 * address has it always cleared. The former is done to indicate thumb mode
877 if ((pc_value
& 0x02) && breakpoint_find(target
, pc_value
& ~0x03)) {
878 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
879 cortex_m3_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
880 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
881 /* Re-enable interrupts */
882 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
886 /* Set a temporary break point */
888 retval
= cortex_m3_set_breakpoint(target
, breakpoint
);
890 retval
= breakpoint_add(target
, pc_value
, 2, BKPT_TYPE_BY_ADDR(pc_value
));
891 bool tmp_bp_set
= (retval
== ERROR_OK
);
893 /* No more breakpoints left, just do a step */
895 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
898 LOG_DEBUG("Starting core to serve pending interrupts");
899 int64_t t_start
= timeval_ms();
900 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
);
902 /* Wait for pending handlers to complete or timeout */
904 retval
= mem_ap_read_atomic_u32(swjdp
,
906 &cortex_m3
->dcb_dhcsr
);
907 if (retval
!= ERROR_OK
) {
908 target
->state
= TARGET_UNKNOWN
;
911 isr_timed_out
= ((timeval_ms() - t_start
) > 500);
912 } while (!((cortex_m3
->dcb_dhcsr
& S_HALT
) || isr_timed_out
));
914 /* only remove breakpoint if we created it */
916 cortex_m3_unset_breakpoint(target
, breakpoint
);
918 /* Remove the temporary breakpoint */
919 breakpoint_remove(target
, pc_value
);
923 LOG_DEBUG("Interrupt handlers didn't complete within time, "
924 "leaving target running");
926 /* Step over next instruction with interrupts disabled */
927 cortex_m3_write_debug_halt_mask(target
,
930 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
931 /* Re-enable interrupts */
932 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
939 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
940 if (retval
!= ERROR_OK
)
943 /* registers are now invalid */
944 register_cache_invalidate(armv7m
->arm
.core_cache
);
947 cortex_m3_set_breakpoint(target
, breakpoint
);
950 /* Leave the core running. The user has to stop execution manually. */
951 target
->debug_reason
= DBG_REASON_NOTHALTED
;
952 target
->state
= TARGET_RUNNING
;
956 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
957 " nvic_icsr = 0x%" PRIx32
,
958 cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
960 retval
= cortex_m3_debug_entry(target
);
961 if (retval
!= ERROR_OK
)
963 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
965 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
966 " nvic_icsr = 0x%" PRIx32
,
967 cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
972 static int cortex_m3_assert_reset(struct target
*target
)
974 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
975 struct adiv5_dap
*swjdp
= cortex_m3
->armv7m
.arm
.dap
;
976 enum cortex_m3_soft_reset_config reset_config
= cortex_m3
->soft_reset_config
;
978 LOG_DEBUG("target->state: %s",
979 target_state_name(target
));
981 enum reset_types jtag_reset_config
= jtag_get_reset_config();
983 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
984 /* allow scripts to override the reset event */
986 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
987 register_cache_invalidate(cortex_m3
->armv7m
.arm
.core_cache
);
988 target
->state
= TARGET_RESET
;
993 /* some cores support connecting while srst is asserted
994 * use that mode is it has been configured */
996 bool srst_asserted
= false;
998 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
999 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
1000 adapter_assert_reset();
1001 srst_asserted
= true;
1004 /* Enable debug requests */
1006 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
1007 if (retval
!= ERROR_OK
)
1009 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
)) {
1010 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
1011 if (retval
!= ERROR_OK
)
1015 /* If the processor is sleeping in a WFI or WFE instruction, the
1016 * C_HALT bit must be asserted to regain control */
1017 if (cortex_m3
->dcb_dhcsr
& S_SLEEP
) {
1018 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_HALT
| C_DEBUGEN
);
1019 if (retval
!= ERROR_OK
)
1023 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
1024 if (retval
!= ERROR_OK
)
1027 if (!target
->reset_halt
) {
1028 /* Set/Clear C_MASKINTS in a separate operation */
1029 if (cortex_m3
->dcb_dhcsr
& C_MASKINTS
) {
1030 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
1031 DBGKEY
| C_DEBUGEN
| C_HALT
);
1032 if (retval
!= ERROR_OK
)
1036 /* clear any debug flags before resuming */
1037 cortex_m3_clear_halt(target
);
1039 /* clear C_HALT in dhcsr reg */
1040 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
1042 /* Halt in debug on reset; endreset_event() restores DEMCR.
1044 * REVISIT catching BUSERR presumably helps to defend against
1045 * bad vector table entries. Should this include MMERR or
1048 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DEMCR
,
1049 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1050 if (retval
!= ERROR_OK
)
1054 if (jtag_reset_config
& RESET_HAS_SRST
) {
1055 /* default to asserting srst */
1057 adapter_assert_reset();
1059 /* Use a standard Cortex-M3 software reset mechanism.
1060 * We default to using VECRESET as it is supported on all current cores.
1061 * This has the disadvantage of not resetting the peripherals, so a
1062 * reset-init event handler is needed to perform any peripheral resets.
1064 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
1065 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M3_RESET_SYSRESETREQ
)
1066 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1067 if (retval
!= ERROR_OK
)
1070 LOG_DEBUG("Using Cortex-M %s", (reset_config
== CORTEX_M3_RESET_SYSRESETREQ
)
1071 ? "SYSRESETREQ" : "VECTRESET");
1073 if (reset_config
== CORTEX_M3_RESET_VECTRESET
) {
1074 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1075 "handler to reset any peripherals or configure hardware srst support.");
1079 /* I do not know why this is necessary, but it
1080 * fixes strange effects (step/resume cause NMI
1081 * after reset) on LM3S6918 -- Michael Schwingen
1084 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_AIRCR
, &tmp
);
1085 if (retval
!= ERROR_OK
)
1090 target
->state
= TARGET_RESET
;
1091 jtag_add_sleep(50000);
1093 register_cache_invalidate(cortex_m3
->armv7m
.arm
.core_cache
);
1095 if (target
->reset_halt
) {
1096 retval
= target_halt(target
);
1097 if (retval
!= ERROR_OK
)
1104 static int cortex_m3_deassert_reset(struct target
*target
)
1106 LOG_DEBUG("target->state: %s",
1107 target_state_name(target
));
1109 /* deassert reset lines */
1110 adapter_deassert_reset();
1115 int cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1120 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1121 struct cortex_m3_fp_comparator
*comparator_list
= cortex_m3
->fp_comparator_list
;
1123 if (breakpoint
->set
) {
1124 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint
->unique_id
);
1128 if (cortex_m3
->auto_bp_type
)
1129 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1131 if (breakpoint
->type
== BKPT_HARD
) {
1132 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m3
->fp_num_code
))
1134 if (fp_num
>= cortex_m3
->fp_num_code
) {
1135 LOG_ERROR("Can not find free FPB Comparator!");
1138 breakpoint
->set
= fp_num
+ 1;
1139 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1140 comparator_list
[fp_num
].used
= 1;
1141 comparator_list
[fp_num
].fpcr_value
= (breakpoint
->address
& 0x1FFFFFFC) | hilo
| 1;
1142 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1143 comparator_list
[fp_num
].fpcr_value
);
1144 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"",
1146 comparator_list
[fp_num
].fpcr_value
);
1147 if (!cortex_m3
->fpb_enabled
) {
1148 LOG_DEBUG("FPB wasn't enabled, do it now");
1149 target_write_u32(target
, FP_CTRL
, 3);
1151 } else if (breakpoint
->type
== BKPT_SOFT
) {
1154 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1155 * semihosting; don't use that. Otherwise the BKPT
1156 * parameter is arbitrary.
1158 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1159 retval
= target_read_memory(target
,
1160 breakpoint
->address
& 0xFFFFFFFE,
1161 breakpoint
->length
, 1,
1162 breakpoint
->orig_instr
);
1163 if (retval
!= ERROR_OK
)
1165 retval
= target_write_memory(target
,
1166 breakpoint
->address
& 0xFFFFFFFE,
1167 breakpoint
->length
, 1,
1169 if (retval
!= ERROR_OK
)
1171 breakpoint
->set
= true;
1174 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1175 breakpoint
->unique_id
,
1176 (int)(breakpoint
->type
),
1177 breakpoint
->address
,
1184 int cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1187 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1188 struct cortex_m3_fp_comparator
*comparator_list
= cortex_m3
->fp_comparator_list
;
1190 if (!breakpoint
->set
) {
1191 LOG_WARNING("breakpoint not set");
1195 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1196 breakpoint
->unique_id
,
1197 (int)(breakpoint
->type
),
1198 breakpoint
->address
,
1202 if (breakpoint
->type
== BKPT_HARD
) {
1203 int fp_num
= breakpoint
->set
- 1;
1204 if ((fp_num
< 0) || (fp_num
>= cortex_m3
->fp_num_code
)) {
1205 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1208 comparator_list
[fp_num
].used
= 0;
1209 comparator_list
[fp_num
].fpcr_value
= 0;
1210 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1211 comparator_list
[fp_num
].fpcr_value
);
1213 /* restore original instruction (kept in target endianness) */
1214 if (breakpoint
->length
== 4) {
1215 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 4, 1,
1216 breakpoint
->orig_instr
);
1217 if (retval
!= ERROR_OK
)
1220 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 2, 1,
1221 breakpoint
->orig_instr
);
1222 if (retval
!= ERROR_OK
)
1226 breakpoint
->set
= false;
1231 int cortex_m3_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1233 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1235 if (cortex_m3
->auto_bp_type
) {
1236 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1237 #ifdef ARMV7_GDB_HACKS
1238 if (breakpoint
->length
!= 2) {
1239 /* XXX Hack: Replace all breakpoints with length != 2 with
1240 * a hardware breakpoint. */
1241 breakpoint
->type
= BKPT_HARD
;
1242 breakpoint
->length
= 2;
1247 if (breakpoint
->type
!= BKPT_TYPE_BY_ADDR(breakpoint
->address
)) {
1248 if (breakpoint
->type
== BKPT_HARD
) {
1249 LOG_INFO("flash patch comparator requested outside code memory region");
1250 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1253 if (breakpoint
->type
== BKPT_SOFT
) {
1254 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1255 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1259 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_m3
->fp_code_available
< 1)) {
1260 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1261 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1264 if ((breakpoint
->length
!= 2)) {
1265 LOG_INFO("only breakpoints of two bytes length supported");
1266 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1269 if (breakpoint
->type
== BKPT_HARD
)
1270 cortex_m3
->fp_code_available
--;
1272 return cortex_m3_set_breakpoint(target
, breakpoint
);
1275 int cortex_m3_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1277 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1279 /* REVISIT why check? FBP can be updated with core running ... */
1280 if (target
->state
!= TARGET_HALTED
) {
1281 LOG_WARNING("target not halted");
1282 return ERROR_TARGET_NOT_HALTED
;
1285 if (cortex_m3
->auto_bp_type
)
1286 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1288 if (breakpoint
->set
)
1289 cortex_m3_unset_breakpoint(target
, breakpoint
);
1291 if (breakpoint
->type
== BKPT_HARD
)
1292 cortex_m3
->fp_code_available
++;
1297 int cortex_m3_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1300 uint32_t mask
, temp
;
1301 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1303 /* watchpoint params were validated earlier */
1305 temp
= watchpoint
->length
;
1312 /* REVISIT Don't fully trust these "not used" records ... users
1313 * may set up breakpoints by hand, e.g. dual-address data value
1314 * watchpoint using comparator #1; comparator #0 matching cycle
1315 * count; send data trace info through ITM and TPIU; etc
1317 struct cortex_m3_dwt_comparator
*comparator
;
1319 for (comparator
= cortex_m3
->dwt_comparator_list
;
1320 comparator
->used
&& dwt_num
< cortex_m3
->dwt_num_comp
;
1321 comparator
++, dwt_num
++)
1323 if (dwt_num
>= cortex_m3
->dwt_num_comp
) {
1324 LOG_ERROR("Can not find free DWT Comparator");
1327 comparator
->used
= 1;
1328 watchpoint
->set
= dwt_num
+ 1;
1330 comparator
->comp
= watchpoint
->address
;
1331 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1334 comparator
->mask
= mask
;
1335 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1338 switch (watchpoint
->rw
) {
1340 comparator
->function
= 5;
1343 comparator
->function
= 6;
1346 comparator
->function
= 7;
1349 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1350 comparator
->function
);
1352 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1353 watchpoint
->unique_id
, dwt_num
,
1354 (unsigned) comparator
->comp
,
1355 (unsigned) comparator
->mask
,
1356 (unsigned) comparator
->function
);
1360 int cortex_m3_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1362 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1363 struct cortex_m3_dwt_comparator
*comparator
;
1366 if (!watchpoint
->set
) {
1367 LOG_WARNING("watchpoint (wpid: %d) not set",
1368 watchpoint
->unique_id
);
1372 dwt_num
= watchpoint
->set
- 1;
1374 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1375 watchpoint
->unique_id
, dwt_num
,
1376 (unsigned) watchpoint
->address
);
1378 if ((dwt_num
< 0) || (dwt_num
>= cortex_m3
->dwt_num_comp
)) {
1379 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1383 comparator
= cortex_m3
->dwt_comparator_list
+ dwt_num
;
1384 comparator
->used
= 0;
1385 comparator
->function
= 0;
1386 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1387 comparator
->function
);
1389 watchpoint
->set
= false;
1394 int cortex_m3_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1396 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1398 if (cortex_m3
->dwt_comp_available
< 1) {
1399 LOG_DEBUG("no comparators?");
1400 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1403 /* hardware doesn't support data value masking */
1404 if (watchpoint
->mask
!= ~(uint32_t)0) {
1405 LOG_DEBUG("watchpoint value masks not supported");
1406 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1409 /* hardware allows address masks of up to 32K */
1412 for (mask
= 0; mask
< 16; mask
++) {
1413 if ((1u << mask
) == watchpoint
->length
)
1417 LOG_DEBUG("unsupported watchpoint length");
1418 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1420 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1421 LOG_DEBUG("watchpoint address is unaligned");
1422 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1425 /* Caller doesn't seem to be able to describe watching for data
1426 * values of zero; that flags "no value".
1428 * REVISIT This DWT may well be able to watch for specific data
1429 * values. Requires comparator #1 to set DATAVMATCH and match
1430 * the data, and another comparator (DATAVADDR0) matching addr.
1432 if (watchpoint
->value
) {
1433 LOG_DEBUG("data value watchpoint not YET supported");
1434 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1437 cortex_m3
->dwt_comp_available
--;
1438 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1443 int cortex_m3_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1445 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1447 /* REVISIT why check? DWT can be updated with core running ... */
1448 if (target
->state
!= TARGET_HALTED
) {
1449 LOG_WARNING("target not halted");
1450 return ERROR_TARGET_NOT_HALTED
;
1453 if (watchpoint
->set
)
1454 cortex_m3_unset_watchpoint(target
, watchpoint
);
1456 cortex_m3
->dwt_comp_available
++;
1457 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1462 void cortex_m3_enable_watchpoints(struct target
*target
)
1464 struct watchpoint
*watchpoint
= target
->watchpoints
;
1466 /* set any pending watchpoints */
1467 while (watchpoint
) {
1468 if (!watchpoint
->set
)
1469 cortex_m3_set_watchpoint(target
, watchpoint
);
1470 watchpoint
= watchpoint
->next
;
1474 static int cortex_m3_load_core_reg_u32(struct target
*target
,
1475 uint32_t num
, uint32_t *value
)
1478 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1479 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1481 /* NOTE: we "know" here that the register identifiers used
1482 * in the v7m header match the Cortex-M3 Debug Core Register
1483 * Selector values for R0..R15, xPSR, MSP, and PSP.
1487 /* read a normal core register */
1488 retval
= cortexm3_dap_read_coreregister_u32(swjdp
, value
, num
);
1490 if (retval
!= ERROR_OK
) {
1491 LOG_ERROR("JTAG failure %i", retval
);
1492 return ERROR_JTAG_DEVICE_ERROR
;
1494 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1497 case ARMV7M_PRIMASK
:
1498 case ARMV7M_BASEPRI
:
1499 case ARMV7M_FAULTMASK
:
1500 case ARMV7M_CONTROL
:
1501 /* Cortex-M3 packages these four registers as bitfields
1502 * in one Debug Core register. So say r0 and r2 docs;
1503 * it was removed from r1 docs, but still works.
1505 cortexm3_dap_read_coreregister_u32(swjdp
, value
, 20);
1508 case ARMV7M_PRIMASK
:
1509 *value
= buf_get_u32((uint8_t *)value
, 0, 1);
1512 case ARMV7M_BASEPRI
:
1513 *value
= buf_get_u32((uint8_t *)value
, 8, 8);
1516 case ARMV7M_FAULTMASK
:
1517 *value
= buf_get_u32((uint8_t *)value
, 16, 1);
1520 case ARMV7M_CONTROL
:
1521 *value
= buf_get_u32((uint8_t *)value
, 24, 2);
1525 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1529 return ERROR_COMMAND_SYNTAX_ERROR
;
1535 static int cortex_m3_store_core_reg_u32(struct target
*target
,
1536 uint32_t num
, uint32_t value
)
1540 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1541 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1543 #ifdef ARMV7_GDB_HACKS
1544 /* If the LR register is being modified, make sure it will put us
1545 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1546 * hack to deal with the fact that gdb will sometimes "forge"
1547 * return addresses, and doesn't set the LSB correctly (i.e., when
1548 * printing expressions containing function calls, it sets LR = 0.)
1549 * Valid exception return codes have bit 0 set too.
1551 if (num
== ARMV7M_R14
)
1555 /* NOTE: we "know" here that the register identifiers used
1556 * in the v7m header match the Cortex-M3 Debug Core Register
1557 * Selector values for R0..R15, xPSR, MSP, and PSP.
1561 retval
= cortexm3_dap_write_coreregister_u32(swjdp
, value
, num
);
1562 if (retval
!= ERROR_OK
) {
1565 LOG_ERROR("JTAG failure");
1566 r
= armv7m
->arm
.core_cache
->reg_list
+ num
;
1567 r
->dirty
= r
->valid
;
1568 return ERROR_JTAG_DEVICE_ERROR
;
1570 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1573 case ARMV7M_PRIMASK
:
1574 case ARMV7M_BASEPRI
:
1575 case ARMV7M_FAULTMASK
:
1576 case ARMV7M_CONTROL
:
1577 /* Cortex-M3 packages these four registers as bitfields
1578 * in one Debug Core register. So say r0 and r2 docs;
1579 * it was removed from r1 docs, but still works.
1581 cortexm3_dap_read_coreregister_u32(swjdp
, ®
, 20);
1584 case ARMV7M_PRIMASK
:
1585 buf_set_u32((uint8_t *)®
, 0, 1, value
);
1588 case ARMV7M_BASEPRI
:
1589 buf_set_u32((uint8_t *)®
, 8, 8, value
);
1592 case ARMV7M_FAULTMASK
:
1593 buf_set_u32((uint8_t *)®
, 16, 1, value
);
1596 case ARMV7M_CONTROL
:
1597 buf_set_u32((uint8_t *)®
, 24, 2, value
);
1601 cortexm3_dap_write_coreregister_u32(swjdp
, reg
, 20);
1603 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1607 return ERROR_COMMAND_SYNTAX_ERROR
;
1613 static int cortex_m3_read_memory(struct target
*target
, uint32_t address
,
1614 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1616 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1617 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1618 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1620 if (armv7m
->arm
.is_armv6m
) {
1621 /* armv6m does not handle unaligned memory access */
1622 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1623 return ERROR_TARGET_UNALIGNED_ACCESS
;
1626 /* cortex_m3 handles unaligned memory access */
1627 if (count
&& buffer
) {
1630 retval
= mem_ap_read_buf_u32(swjdp
, buffer
, 4 * count
, address
, true);
1633 retval
= mem_ap_read_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1636 retval
= mem_ap_read_buf_u8(swjdp
, buffer
, count
, address
);
1644 static int cortex_m3_write_memory(struct target
*target
, uint32_t address
,
1645 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1647 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1648 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1649 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1651 if (armv7m
->arm
.is_armv6m
) {
1652 /* armv6m does not handle unaligned memory access */
1653 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1654 return ERROR_TARGET_UNALIGNED_ACCESS
;
1657 if (count
&& buffer
) {
1660 retval
= mem_ap_write_buf_u32(swjdp
, buffer
, 4 * count
, address
, true);
1663 retval
= mem_ap_write_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1666 retval
= mem_ap_write_buf_u8(swjdp
, buffer
, count
, address
);
1674 static int cortex_m3_init_target(struct command_context
*cmd_ctx
,
1675 struct target
*target
)
1677 armv7m_build_reg_cache(target
);
1681 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1682 * on r/w if the core is not running, and clear on resume or reset ... or
1683 * at least, in a post_restore_context() method.
1686 struct dwt_reg_state
{
1687 struct target
*target
;
1689 uint32_t value
; /* scratch/cache */
1692 static int cortex_m3_dwt_get_reg(struct reg
*reg
)
1694 struct dwt_reg_state
*state
= reg
->arch_info
;
1696 return target_read_u32(state
->target
, state
->addr
, &state
->value
);
1699 static int cortex_m3_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1701 struct dwt_reg_state
*state
= reg
->arch_info
;
1703 return target_write_u32(state
->target
, state
->addr
,
1704 buf_get_u32(buf
, 0, reg
->size
));
1713 static struct dwt_reg dwt_base_regs
[] = {
1714 { DWT_CTRL
, "dwt_ctrl", 32, },
1715 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1716 * increments while the core is asleep.
1718 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1719 /* plus some 8 bit counters, useful for profiling with TPIU */
1722 static struct dwt_reg dwt_comp
[] = {
1723 #define DWT_COMPARATOR(i) \
1724 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1725 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1726 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1731 #undef DWT_COMPARATOR
1734 static const struct reg_arch_type dwt_reg_type
= {
1735 .get
= cortex_m3_dwt_get_reg
,
1736 .set
= cortex_m3_dwt_set_reg
,
1739 static void cortex_m3_dwt_addreg(struct target
*t
, struct reg
*r
, struct dwt_reg
*d
)
1741 struct dwt_reg_state
*state
;
1743 state
= calloc(1, sizeof *state
);
1746 state
->addr
= d
->addr
;
1751 r
->value
= &state
->value
;
1752 r
->arch_info
= state
;
1753 r
->type
= &dwt_reg_type
;
1756 void cortex_m3_dwt_setup(struct cortex_m3_common
*cm3
, struct target
*target
)
1759 struct reg_cache
*cache
;
1760 struct cortex_m3_dwt_comparator
*comparator
;
1763 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1765 LOG_DEBUG("no DWT");
1769 cm3
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1770 cm3
->dwt_comp_available
= cm3
->dwt_num_comp
;
1771 cm3
->dwt_comparator_list
= calloc(cm3
->dwt_num_comp
,
1772 sizeof(struct cortex_m3_dwt_comparator
));
1773 if (!cm3
->dwt_comparator_list
) {
1775 cm3
->dwt_num_comp
= 0;
1776 LOG_ERROR("out of mem");
1780 cache
= calloc(1, sizeof *cache
);
1783 free(cm3
->dwt_comparator_list
);
1786 cache
->name
= "cortex-m3 dwt registers";
1787 cache
->num_regs
= 2 + cm3
->dwt_num_comp
* 3;
1788 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
1789 if (!cache
->reg_list
) {
1794 for (reg
= 0; reg
< 2; reg
++)
1795 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1796 dwt_base_regs
+ reg
);
1798 comparator
= cm3
->dwt_comparator_list
;
1799 for (i
= 0; i
< cm3
->dwt_num_comp
; i
++, comparator
++) {
1802 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
1803 for (j
= 0; j
< 3; j
++, reg
++)
1804 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1805 dwt_comp
+ 3 * i
+ j
);
1807 /* make sure we clear any watchpoints enabled on the target */
1808 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8, 0);
1811 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
1812 cm3
->dwt_cache
= cache
;
1814 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
1815 dwtcr
, cm3
->dwt_num_comp
,
1816 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
1818 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1819 * implement single-address data value watchpoints ... so we
1820 * won't need to check it later, when asked to set one up.
1824 #define MVFR0 0xe000ef40
1825 #define MVFR1 0xe000ef44
1827 #define MVFR0_DEFAULT_M4 0x10110021
1828 #define MVFR1_DEFAULT_M4 0x11000011
1830 int cortex_m3_examine(struct target
*target
)
1833 uint32_t cpuid
, fpcr
, mvfr0
, mvfr1
;
1835 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1836 struct adiv5_dap
*swjdp
= cortex_m3
->armv7m
.arm
.dap
;
1837 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1839 /* stlink shares the examine handler but does not support
1841 if (!armv7m
->stlink
) {
1842 retval
= ahbap_debugport_init(swjdp
);
1843 if (retval
!= ERROR_OK
)
1847 if (!target_was_examined(target
)) {
1848 target_set_examined(target
);
1850 /* Read from Device Identification Registers */
1851 retval
= target_read_u32(target
, CPUID
, &cpuid
);
1852 if (retval
!= ERROR_OK
)
1856 i
= (cpuid
>> 4) & 0xf;
1858 LOG_DEBUG("Cortex-M%d r%" PRId8
"p%" PRId8
" processor detected",
1859 i
, (uint8_t)((cpuid
>> 20) & 0xf), (uint8_t)((cpuid
>> 0) & 0xf));
1860 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
1862 /* test for floating point feature on cortex-m4 */
1864 target_read_u32(target
, MVFR0
, &mvfr0
);
1865 target_read_u32(target
, MVFR1
, &mvfr1
);
1867 if ((mvfr0
== MVFR0_DEFAULT_M4
) && (mvfr1
== MVFR1_DEFAULT_M4
)) {
1868 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i
);
1869 armv7m
->fp_feature
= FPv4_SP
;
1871 } else if (i
== 0) {
1872 /* Cortex-M0 does not support unaligned memory access */
1873 armv7m
->arm
.is_armv6m
= true;
1876 if (i
== 4 || i
== 3) {
1877 /* Cortex-M3/M4 has 4096 bytes autoincrement range */
1878 armv7m
->dap
.tar_autoincr_block
= (1 << 12);
1881 /* NOTE: FPB and DWT are both optional. */
1884 target_read_u32(target
, FP_CTRL
, &fpcr
);
1885 cortex_m3
->auto_bp_type
= 1;
1886 cortex_m3
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF); /* bits
1890 cortex_m3
->fp_num_lit
= (fpcr
>> 8) & 0xF;
1891 cortex_m3
->fp_code_available
= cortex_m3
->fp_num_code
;
1892 cortex_m3
->fp_comparator_list
= calloc(
1893 cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
,
1894 sizeof(struct cortex_m3_fp_comparator
));
1895 cortex_m3
->fpb_enabled
= fpcr
& 1;
1896 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++) {
1897 cortex_m3
->fp_comparator_list
[i
].type
=
1898 (i
< cortex_m3
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
1899 cortex_m3
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
1901 /* make sure we clear any breakpoints enabled on the target */
1902 target_write_u32(target
, cortex_m3
->fp_comparator_list
[i
].fpcr_address
, 0);
1904 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i",
1906 cortex_m3
->fp_num_code
,
1907 cortex_m3
->fp_num_lit
);
1910 cortex_m3_dwt_setup(cortex_m3
, target
);
1912 /* These hardware breakpoints only work for code in flash! */
1913 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1914 target_name(target
),
1915 cortex_m3
->fp_num_code
,
1916 cortex_m3
->dwt_num_comp
);
1922 static int cortex_m3_dcc_read(struct adiv5_dap
*swjdp
, uint8_t *value
, uint8_t *ctrl
)
1927 mem_ap_read_buf_u16(swjdp
, (uint8_t *)&dcrdr
, 1, DCB_DCRDR
);
1928 *ctrl
= (uint8_t)dcrdr
;
1929 *value
= (uint8_t)(dcrdr
>> 8);
1931 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
1933 /* write ack back to software dcc register
1934 * signify we have read data */
1935 if (dcrdr
& (1 << 0)) {
1937 retval
= mem_ap_write_buf_u16(swjdp
, (uint8_t *)&dcrdr
, 1, DCB_DCRDR
);
1938 if (retval
!= ERROR_OK
)
1945 static int cortex_m3_target_request_data(struct target
*target
,
1946 uint32_t size
, uint8_t *buffer
)
1948 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1949 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1954 for (i
= 0; i
< (size
* 4); i
++) {
1955 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1962 static int cortex_m3_handle_target_request(void *priv
)
1964 struct target
*target
= priv
;
1965 if (!target_was_examined(target
))
1967 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1968 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1970 if (!target
->dbg_msg_enabled
)
1973 if (target
->state
== TARGET_RUNNING
) {
1977 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1979 /* check if we have data */
1980 if (ctrl
& (1 << 0)) {
1983 /* we assume target is quick enough */
1985 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1986 request
|= (data
<< 8);
1987 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1988 request
|= (data
<< 16);
1989 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1990 request
|= (data
<< 24);
1991 target_request(target
, request
);
1998 static int cortex_m3_init_arch_info(struct target
*target
,
1999 struct cortex_m3_common
*cortex_m3
, struct jtag_tap
*tap
)
2002 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
2004 armv7m_init_arch_info(target
, armv7m
);
2006 /* prepare JTAG information for the new target */
2007 cortex_m3
->jtag_info
.tap
= tap
;
2008 cortex_m3
->jtag_info
.scann_size
= 4;
2010 /* default reset mode is to use srst if fitted
2011 * if not it will use CORTEX_M3_RESET_VECTRESET */
2012 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_VECTRESET
;
2014 armv7m
->arm
.dap
= &armv7m
->dap
;
2016 /* Leave (only) generic DAP stuff for debugport_init(); */
2017 armv7m
->dap
.jtag_info
= &cortex_m3
->jtag_info
;
2018 armv7m
->dap
.memaccess_tck
= 8;
2020 /* Cortex-M3/M4 has 4096 bytes autoincrement range
2021 * but set a safe default to 1024 to support Cortex-M0
2022 * this will be changed in cortex_m3_examine if a M3/M4 is detected */
2023 armv7m
->dap
.tar_autoincr_block
= (1 << 10);
2025 /* register arch-specific functions */
2026 armv7m
->examine_debug_reason
= cortex_m3_examine_debug_reason
;
2028 armv7m
->post_debug_entry
= NULL
;
2030 armv7m
->pre_restore_context
= NULL
;
2032 armv7m
->load_core_reg_u32
= cortex_m3_load_core_reg_u32
;
2033 armv7m
->store_core_reg_u32
= cortex_m3_store_core_reg_u32
;
2035 target_register_timer_callback(cortex_m3_handle_target_request
, 1, 1, target
);
2037 retval
= arm_jtag_setup_connection(&cortex_m3
->jtag_info
);
2038 if (retval
!= ERROR_OK
)
2044 static int cortex_m3_target_create(struct target
*target
, Jim_Interp
*interp
)
2046 struct cortex_m3_common
*cortex_m3
= calloc(1, sizeof(struct cortex_m3_common
));
2048 cortex_m3
->common_magic
= CORTEX_M3_COMMON_MAGIC
;
2049 cortex_m3_init_arch_info(target
, cortex_m3
, target
->tap
);
2054 /*--------------------------------------------------------------------------*/
2056 static int cortex_m3_verify_pointer(struct command_context
*cmd_ctx
,
2057 struct cortex_m3_common
*cm3
)
2059 if (cm3
->common_magic
!= CORTEX_M3_COMMON_MAGIC
) {
2060 command_print(cmd_ctx
, "target is not a Cortex-M");
2061 return ERROR_TARGET_INVALID
;
2067 * Only stuff below this line should need to verify that its target
2068 * is a Cortex-M3. Everything else should have indirected through the
2069 * cortexm3_target structure, which is only used with CM3 targets.
2072 static const struct {
2076 { "hard_err", VC_HARDERR
, },
2077 { "int_err", VC_INTERR
, },
2078 { "bus_err", VC_BUSERR
, },
2079 { "state_err", VC_STATERR
, },
2080 { "chk_err", VC_CHKERR
, },
2081 { "nocp_err", VC_NOCPERR
, },
2082 { "mm_err", VC_MMERR
, },
2083 { "reset", VC_CORERESET
, },
2086 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command
)
2088 struct target
*target
= get_current_target(CMD_CTX
);
2089 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2090 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
2091 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
2095 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2096 if (retval
!= ERROR_OK
)
2099 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2100 if (retval
!= ERROR_OK
)
2106 if (CMD_ARGC
== 1) {
2107 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2108 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2109 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2110 | VC_MMERR
| VC_CORERESET
;
2112 } else if (strcmp(CMD_ARGV
[0], "none") == 0)
2115 while (CMD_ARGC
-- > 0) {
2117 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2118 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2120 catch |= vec_ids
[i
].mask
;
2123 if (i
== ARRAY_SIZE(vec_ids
)) {
2124 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2125 return ERROR_COMMAND_SYNTAX_ERROR
;
2129 /* For now, armv7m->demcr only stores vector catch flags. */
2130 armv7m
->demcr
= catch;
2135 /* write, but don't assume it stuck (why not??) */
2136 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, demcr
);
2137 if (retval
!= ERROR_OK
)
2139 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2140 if (retval
!= ERROR_OK
)
2143 /* FIXME be sure to clear DEMCR on clean server shutdown.
2144 * Otherwise the vector catch hardware could fire when there's
2145 * no debugger hooked up, causing much confusion...
2149 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2150 command_print(CMD_CTX
, "%9s: %s", vec_ids
[i
].name
,
2151 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2157 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command
)
2159 struct target
*target
= get_current_target(CMD_CTX
);
2160 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2163 static const Jim_Nvp nvp_maskisr_modes
[] = {
2164 { .name
= "auto", .value
= CORTEX_M3_ISRMASK_AUTO
},
2165 { .name
= "off", .value
= CORTEX_M3_ISRMASK_OFF
},
2166 { .name
= "on", .value
= CORTEX_M3_ISRMASK_ON
},
2167 { .name
= NULL
, .value
= -1 },
2172 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2173 if (retval
!= ERROR_OK
)
2176 if (target
->state
!= TARGET_HALTED
) {
2177 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
2182 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
2183 if (n
->name
== NULL
)
2184 return ERROR_COMMAND_SYNTAX_ERROR
;
2185 cortex_m3
->isrmasking_mode
= n
->value
;
2188 if (cortex_m3
->isrmasking_mode
== CORTEX_M3_ISRMASK_ON
)
2189 cortex_m3_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
2191 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
2194 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_m3
->isrmasking_mode
);
2195 command_print(CMD_CTX
, "cortex_m3 interrupt mask %s", n
->name
);
2200 COMMAND_HANDLER(handle_cortex_m3_reset_config_command
)
2202 struct target
*target
= get_current_target(CMD_CTX
);
2203 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2207 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2208 if (retval
!= ERROR_OK
)
2212 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2213 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_SYSRESETREQ
;
2214 else if (strcmp(*CMD_ARGV
, "vectreset") == 0)
2215 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_VECTRESET
;
2218 switch (cortex_m3
->soft_reset_config
) {
2219 case CORTEX_M3_RESET_SYSRESETREQ
:
2220 reset_config
= "sysresetreq";
2223 case CORTEX_M3_RESET_VECTRESET
:
2224 reset_config
= "vectreset";
2228 reset_config
= "unknown";
2232 command_print(CMD_CTX
, "cortex_m3 reset_config %s", reset_config
);
2237 static const struct command_registration cortex_m3_exec_command_handlers
[] = {
2240 .handler
= handle_cortex_m3_mask_interrupts_command
,
2241 .mode
= COMMAND_EXEC
,
2242 .help
= "mask cortex_m3 interrupts",
2243 .usage
= "['auto'|'on'|'off']",
2246 .name
= "vector_catch",
2247 .handler
= handle_cortex_m3_vector_catch_command
,
2248 .mode
= COMMAND_EXEC
,
2249 .help
= "configure hardware vectors to trigger debug entry",
2250 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2253 .name
= "reset_config",
2254 .handler
= handle_cortex_m3_reset_config_command
,
2255 .mode
= COMMAND_ANY
,
2256 .help
= "configure software reset handling",
2257 .usage
= "['srst'|'sysresetreq'|'vectreset']",
2259 COMMAND_REGISTRATION_DONE
2261 static const struct command_registration cortex_m3_command_handlers
[] = {
2263 .chain
= armv7m_command_handlers
,
2267 .mode
= COMMAND_EXEC
,
2268 .help
= "Cortex-M command group",
2270 .chain
= cortex_m3_exec_command_handlers
,
2272 COMMAND_REGISTRATION_DONE
2275 struct target_type cortexm3_target
= {
2277 .deprecated_name
= "cortex_m3",
2279 .poll
= cortex_m3_poll
,
2280 .arch_state
= armv7m_arch_state
,
2282 .target_request_data
= cortex_m3_target_request_data
,
2284 .halt
= cortex_m3_halt
,
2285 .resume
= cortex_m3_resume
,
2286 .step
= cortex_m3_step
,
2288 .assert_reset
= cortex_m3_assert_reset
,
2289 .deassert_reset
= cortex_m3_deassert_reset
,
2290 .soft_reset_halt
= cortex_m3_soft_reset_halt
,
2292 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2294 .read_memory
= cortex_m3_read_memory
,
2295 .write_memory
= cortex_m3_write_memory
,
2296 .checksum_memory
= armv7m_checksum_memory
,
2297 .blank_check_memory
= armv7m_blank_check_memory
,
2299 .run_algorithm
= armv7m_run_algorithm
,
2300 .start_algorithm
= armv7m_start_algorithm
,
2301 .wait_algorithm
= armv7m_wait_algorithm
,
2303 .add_breakpoint
= cortex_m3_add_breakpoint
,
2304 .remove_breakpoint
= cortex_m3_remove_breakpoint
,
2305 .add_watchpoint
= cortex_m3_add_watchpoint
,
2306 .remove_watchpoint
= cortex_m3_remove_watchpoint
,
2308 .commands
= cortex_m3_command_handlers
,
2309 .target_create
= cortex_m3_target_create
,
2310 .init_target
= cortex_m3_init_target
,
2311 .examine
= cortex_m3_examine
,
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