Matt Hsu <matt@0xlab.org> cortex-a8: Copy some more registers from the documentation
[openocd.git] / src / target / cortex_a8.h
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
29 #ifndef CORTEX_A8_H
30 #define CORTEX_A8_H
31
32 #include "register.h"
33 #include "target.h"
34 #include "armv7a.h"
35 #include "arm7_9_common.h"
36
37 extern char* cortex_a8_state_strings[];
38
39 #define CORTEX_A8_COMMON_MAGIC 0x411fc082
40
41 #define CPUID 0x54011D00
42 /* Debug Control Block */
43 #define CPUDBG_DIDR 0x000
44 #define CPUDBG_WFAR 0x018
45 #define CPUDBG_VCR 0x01C
46 #define CPUDBG_DSCCR 0x028
47 #define CPUDBG_DTRRX 0x080
48 #define CPUDBG_ITR 0x084
49 #define CPUDBG_DSCR 0x088
50 #define CPUDBG_DTRTX 0x08c
51 #define CPUDBG_DRCR 0x090
52 #define CPUDBG_BVR_BASE 0x100
53 #define CPUDBG_BCR_BASE 0x140
54 #define CPUDBG_WVR_BASE 0x180
55
56 #define CPUDBG_OSLAR 0x300
57 #define CPUDBG_OSLSR 0x304
58 #define CPUDBG_OSSRR 0x308
59
60 #define CPUDBG_PRCR 0x310
61 #define CPUDBG_PRSR 0x314
62
63 #define CPUDBG_CPUID 0xD00
64 #define CPUDBG_CTYPR 0xD04
65 #define CPUDBG_TTYPR 0xD0C
66
67 #define BRP_NORMAL 0
68 #define BRP_CONTEXT 1
69
70 typedef struct cortex_a8_brp_s
71 {
72 int used;
73 int type;
74 uint32_t value;
75 uint32_t control;
76 uint8_t BRPn;
77 } cortex_a8_brp_t;
78
79 typedef struct cortex_a8_wrp_s
80 {
81 int used;
82 int type;
83 uint32_t value;
84 uint32_t control;
85 uint8_t WRPn;
86 } cortex_a8_wrp_t;
87
88 typedef struct cortex_a8_common_s
89 {
90 int common_magic;
91 arm_jtag_t jtag_info;
92
93 /* Core Debug Unit */
94 uint32_t debug_base;
95 uint8_t debug_ap;
96 uint8_t memory_ap;
97
98 /* Context information */
99 uint32_t cpudbg_dscr;
100 uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
101 uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
102
103 /* Saved cp15 registers */
104 uint32_t cp15_control_reg;
105 uint32_t cp15_aux_control_reg;
106
107 /* Breakpoint register pairs */
108 int brp_num_context;
109 int brp_num;
110 int brp_num_available;
111 // int brp_enabled;
112 cortex_a8_brp_t *brp_list;
113
114 /* Watchpoint register pairs */
115 int wrp_num;
116 int wrp_num_available;
117 cortex_a8_wrp_t *wrp_list;
118
119 /* Interrupts */
120 int intlinesnum;
121 uint32_t *intsetenable;
122
123 /* Use cortex_a8_read_regs_through_mem for fast register reads */
124 int fast_reg_read;
125
126 armv7a_common_t armv7a_common;
127 void *arch_info;
128 } cortex_a8_common_t;
129
130 extern int cortex_a8_init_arch_info(target_t *target, cortex_a8_common_t *cortex_a8, jtag_tap_t *tap);
131 int cortex_a8_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
132 int cortex_a8_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
133
134 #endif /* CORTEX_A8_H */