1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
34 extern char* cortex_a8_state_strings
[];
36 #define CORTEX_A8_COMMON_MAGIC 0x411fc082
38 #define CPUID 0x54011D00
39 /* Debug Control Block */
40 #define CPUDBG_DIDR 0x000
41 #define CPUDBG_WFAR 0x018
42 #define CPUDBG_VCR 0x01C
43 #define CPUDBG_ECR 0x024
44 #define CPUDBG_DSCCR 0x028
45 #define CPUDBG_DTRRX 0x080
46 #define CPUDBG_ITR 0x084
47 #define CPUDBG_DSCR 0x088
48 #define CPUDBG_DTRTX 0x08c
49 #define CPUDBG_DRCR 0x090
50 #define CPUDBG_BVR_BASE 0x100
51 #define CPUDBG_BCR_BASE 0x140
52 #define CPUDBG_WVR_BASE 0x180
53 #define CPUDBG_WCR_BASE 0x1C0
55 #define CPUDBG_OSLAR 0x300
56 #define CPUDBG_OSLSR 0x304
57 #define CPUDBG_OSSRR 0x308
59 #define CPUDBG_PRCR 0x310
60 #define CPUDBG_PRSR 0x314
62 #define CPUDBG_CPUID 0xD00
63 #define CPUDBG_CTYPR 0xD04
64 #define CPUDBG_TTYPR 0xD0C
65 #define CPUDBG_LOCKACCESS 0xFB0
66 #define CPUDBG_LOCKSTATUS 0xFB4
67 #define CPUDBG_AUTHSTATUS 0xFB8
73 #define DSCR_CORE_HALTED 0
74 #define DSCR_CORE_RESTARTED 1
75 #define DSCR_EXT_INT_EN 13
76 #define DSCR_HALT_DBG_MODE 14
77 #define DSCR_MON_DBG_MODE 15
78 #define DSCR_INSTR_COMP 24
79 #define DSCR_DTR_TX_FULL 29
80 #define DSCR_DTR_RX_FULL 30
100 struct cortex_a8_common
103 struct arm_jtag jtag_info
;
105 /* Context information */
106 uint32_t cpudbg_dscr
;
107 uint32_t nvic_dfsr
; /* Debug Fault Status Register - shows reason for debug halt */
108 uint32_t nvic_icsr
; /* Interrupt Control State Register - shows active and pending IRQ */
110 /* Saved cp15 registers */
111 uint32_t cp15_control_reg
;
112 uint32_t cp15_aux_control_reg
;
114 /* Breakpoint register pairs */
117 int brp_num_available
;
119 struct cortex_a8_brp
*brp_list
;
121 /* Watchpoint register pairs */
123 int wrp_num_available
;
124 struct cortex_a8_wrp
*wrp_list
;
128 uint32_t *intsetenable
;
130 /* Use cortex_a8_read_regs_through_mem for fast register reads */
133 struct armv7a_common armv7a_common
;
136 static inline struct cortex_a8_common
*
137 target_to_cortex_a8(struct target
*target
)
139 return container_of(target
->arch_info
, struct cortex_a8_common
,
140 armv7a_common
.armv4_5_common
);
143 #endif /* CORTEX_A8_H */
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