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target: factor target_init() into pieces
[openocd.git] / src / target / cortex_a8.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 * *
29 * Cortex-A8(tm) TRM, ARM DDI 0344H *
30 * *
31 ***************************************************************************/
32 #ifdef HAVE_CONFIG_H
33 #include "config.h"
34 #endif
35
36 #include "breakpoints.h"
37 #include "cortex_a8.h"
38 #include "register.h"
39 #include "target_request.h"
40 #include "target_type.h"
41
42 static int cortex_a8_poll(struct target *target);
43 static int cortex_a8_debug_entry(struct target *target);
44 static int cortex_a8_restore_context(struct target *target, bool bpwp);
45 static int cortex_a8_set_breakpoint(struct target *target,
46 struct breakpoint *breakpoint, uint8_t matchmode);
47 static int cortex_a8_unset_breakpoint(struct target *target,
48 struct breakpoint *breakpoint);
49 static int cortex_a8_dap_read_coreregister_u32(struct target *target,
50 uint32_t *value, int regnum);
51 static int cortex_a8_dap_write_coreregister_u32(struct target *target,
52 uint32_t value, int regnum);
53 /*
54 * FIXME do topology discovery using the ROM; don't
55 * assume this is an OMAP3.
56 */
57 #define swjdp_memoryap 0
58 #define swjdp_debugap 1
59 #define OMAP3530_DEBUG_BASE 0x54011000
60
61 /*
62 * Cortex-A8 Basic debug access, very low level assumes state is saved
63 */
64 static int cortex_a8_init_debug_access(struct target *target)
65 {
66 struct armv7a_common *armv7a = target_to_armv7a(target);
67 struct swjdp_common *swjdp = &armv7a->swjdp_info;
68
69 int retval;
70 uint32_t dummy;
71
72 LOG_DEBUG(" ");
73
74 /* Unlocking the debug registers for modification */
75 /* The debugport might be uninitialised so try twice */
76 retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
77 if (retval != ERROR_OK)
78 mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
79 /* Clear Sticky Power Down status Bit in PRSR to enable access to
80 the registers in the Core Power Domain */
81 retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
82 /* Enabling of instruction execution in debug mode is done in debug_entry code */
83
84 /* Resync breakpoint registers */
85
86 /* Since this is likley called from init or reset, update targtet state information*/
87 cortex_a8_poll(target);
88
89 return retval;
90 }
91
92 /* To reduce needless round-trips, pass in a pointer to the current
93 * DSCR value. Initialize it to zero if you just need to know the
94 * value on return from this function; or (1 << DSCR_INSTR_COMP) if
95 * you happen to know that no instruction is pending.
96 */
97 static int cortex_a8_exec_opcode(struct target *target,
98 uint32_t opcode, uint32_t *dscr_p)
99 {
100 uint32_t dscr;
101 int retval;
102 struct armv7a_common *armv7a = target_to_armv7a(target);
103 struct swjdp_common *swjdp = &armv7a->swjdp_info;
104
105 dscr = dscr_p ? *dscr_p : 0;
106
107 LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
108
109 /* Wait for InstrCompl bit to be set */
110 while ((dscr & (1 << DSCR_INSTR_COMP)) == 0)
111 {
112 retval = mem_ap_read_atomic_u32(swjdp,
113 armv7a->debug_base + CPUDBG_DSCR, &dscr);
114 if (retval != ERROR_OK)
115 {
116 LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
117 return retval;
118 }
119 }
120
121 mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
122
123 do
124 {
125 retval = mem_ap_read_atomic_u32(swjdp,
126 armv7a->debug_base + CPUDBG_DSCR, &dscr);
127 if (retval != ERROR_OK)
128 {
129 LOG_ERROR("Could not read DSCR register");
130 return retval;
131 }
132 }
133 while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
134
135 if (dscr_p)
136 *dscr_p = dscr;
137
138 return retval;
139 }
140
141 /**************************************************************************
142 Read core register with very few exec_opcode, fast but needs work_area.
143 This can cause problems with MMU active.
144 **************************************************************************/
145 static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address,
146 uint32_t * regfile)
147 {
148 int retval = ERROR_OK;
149 struct armv7a_common *armv7a = target_to_armv7a(target);
150 struct swjdp_common *swjdp = &armv7a->swjdp_info;
151
152 cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
153 cortex_a8_dap_write_coreregister_u32(target, address, 0);
154 cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
155 dap_ap_select(swjdp, swjdp_memoryap);
156 mem_ap_read_buf_u32(swjdp, (uint8_t *)(&regfile[1]), 4*15, address);
157 dap_ap_select(swjdp, swjdp_debugap);
158
159 return retval;
160 }
161
162 static int cortex_a8_dap_read_coreregister_u32(struct target *target,
163 uint32_t *value, int regnum)
164 {
165 int retval = ERROR_OK;
166 uint8_t reg = regnum&0xFF;
167 uint32_t dscr = 0;
168 struct armv7a_common *armv7a = target_to_armv7a(target);
169 struct swjdp_common *swjdp = &armv7a->swjdp_info;
170
171 if (reg > 17)
172 return retval;
173
174 if (reg < 15)
175 {
176 /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
177 cortex_a8_exec_opcode(target,
178 ARMV4_5_MCR(14, 0, reg, 0, 5, 0),
179 &dscr);
180 }
181 else if (reg == 15)
182 {
183 /* "MOV r0, r15"; then move r0 to DCCTX */
184 cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr);
185 cortex_a8_exec_opcode(target,
186 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
187 &dscr);
188 }
189 else
190 {
191 /* "MRS r0, CPSR" or "MRS r0, SPSR"
192 * then move r0 to DCCTX
193 */
194 cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
195 cortex_a8_exec_opcode(target,
196 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
197 &dscr);
198 }
199
200 /* Wait for DTRRXfull then read DTRRTX */
201 while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0)
202 {
203 retval = mem_ap_read_atomic_u32(swjdp,
204 armv7a->debug_base + CPUDBG_DSCR, &dscr);
205 }
206
207 retval = mem_ap_read_atomic_u32(swjdp,
208 armv7a->debug_base + CPUDBG_DTRTX, value);
209 LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
210
211 return retval;
212 }
213
214 static int cortex_a8_dap_write_coreregister_u32(struct target *target,
215 uint32_t value, int regnum)
216 {
217 int retval = ERROR_OK;
218 uint8_t Rd = regnum&0xFF;
219 uint32_t dscr;
220 struct armv7a_common *armv7a = target_to_armv7a(target);
221 struct swjdp_common *swjdp = &armv7a->swjdp_info;
222
223 LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
224
225 /* Check that DCCRX is not full */
226 retval = mem_ap_read_atomic_u32(swjdp,
227 armv7a->debug_base + CPUDBG_DSCR, &dscr);
228 if (dscr & (1 << DSCR_DTR_RX_FULL))
229 {
230 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
231 /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
232 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
233 &dscr);
234 }
235
236 if (Rd > 17)
237 return retval;
238
239 /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
240 LOG_DEBUG("write DCC 0x%08" PRIx32, value);
241 retval = mem_ap_write_u32(swjdp,
242 armv7a->debug_base + CPUDBG_DTRRX, value);
243
244 if (Rd < 15)
245 {
246 /* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */
247 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
248 &dscr);
249 }
250 else if (Rd == 15)
251 {
252 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
253 * then "mov r15, r0"
254 */
255 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
256 &dscr);
257 cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr);
258 }
259 else
260 {
261 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
262 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
263 */
264 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
265 &dscr);
266 cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
267 &dscr);
268
269 /* "Prefetch flush" after modifying execution status in CPSR */
270 if (Rd == 16)
271 cortex_a8_exec_opcode(target,
272 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
273 &dscr);
274 }
275
276 return retval;
277 }
278
279 /* Write to memory mapped registers directly with no cache or mmu handling */
280 static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_t address, uint32_t value)
281 {
282 int retval;
283 struct armv7a_common *armv7a = target_to_armv7a(target);
284 struct swjdp_common *swjdp = &armv7a->swjdp_info;
285
286 retval = mem_ap_write_atomic_u32(swjdp, address, value);
287
288 return retval;
289 }
290
291 /*
292 * Cortex-A8 implementation of Debug Programmer's Model
293 *
294 * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
295 * so there's no need to poll for it before executing an instruction.
296 *
297 * NOTE that in several of these cases the "stall" mode might be useful.
298 * It'd let us queue a few operations together... prepare/finish might
299 * be the places to enable/disable that mode.
300 */
301
302 static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm)
303 {
304 return container_of(dpm, struct cortex_a8_common, armv7a_common.dpm);
305 }
306
307 static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
308 {
309 LOG_DEBUG("write DCC 0x%08" PRIx32, data);
310 return mem_ap_write_u32(&a8->armv7a_common.swjdp_info,
311 a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
312 }
313
314 static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
315 uint32_t *dscr_p)
316 {
317 struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
318 uint32_t dscr = 1 << DSCR_INSTR_COMP;
319 int retval;
320
321 if (dscr_p)
322 dscr = *dscr_p;
323
324 /* Wait for DTRRXfull */
325 while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0) {
326 retval = mem_ap_read_atomic_u32(swjdp,
327 a8->armv7a_common.debug_base + CPUDBG_DSCR,
328 &dscr);
329 }
330
331 retval = mem_ap_read_atomic_u32(swjdp,
332 a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
333 //LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
334
335 if (dscr_p)
336 *dscr_p = dscr;
337
338 return retval;
339 }
340
341 static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
342 {
343 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
344 struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
345 uint32_t dscr;
346 int retval;
347
348 /* set up invariant: INSTR_COMP is set after ever DPM operation */
349 do {
350 retval = mem_ap_read_atomic_u32(swjdp,
351 a8->armv7a_common.debug_base + CPUDBG_DSCR,
352 &dscr);
353 } while ((dscr & (1 << DSCR_INSTR_COMP)) == 0);
354
355 /* this "should never happen" ... */
356 if (dscr & (1 << DSCR_DTR_RX_FULL)) {
357 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
358 /* Clear DCCRX */
359 retval = cortex_a8_exec_opcode(
360 a8->armv7a_common.armv4_5_common.target,
361 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
362 &dscr);
363 }
364
365 return retval;
366 }
367
368 static int cortex_a8_dpm_finish(struct arm_dpm *dpm)
369 {
370 /* REVISIT what could be done here? */
371 return ERROR_OK;
372 }
373
374 static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
375 uint32_t opcode, uint32_t data)
376 {
377 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
378 int retval;
379 uint32_t dscr = 1 << DSCR_INSTR_COMP;
380
381 retval = cortex_a8_write_dcc(a8, data);
382
383 return cortex_a8_exec_opcode(
384 a8->armv7a_common.armv4_5_common.target,
385 opcode,
386 &dscr);
387 }
388
389 static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
390 uint32_t opcode, uint32_t data)
391 {
392 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
393 uint32_t dscr = 1 << DSCR_INSTR_COMP;
394 int retval;
395
396 retval = cortex_a8_write_dcc(a8, data);
397
398 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
399 retval = cortex_a8_exec_opcode(
400 a8->armv7a_common.armv4_5_common.target,
401 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
402 &dscr);
403
404 /* then the opcode, taking data from R0 */
405 retval = cortex_a8_exec_opcode(
406 a8->armv7a_common.armv4_5_common.target,
407 opcode,
408 &dscr);
409
410 return retval;
411 }
412
413 static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm)
414 {
415 struct target *target = dpm->arm->target;
416 uint32_t dscr = 1 << DSCR_INSTR_COMP;
417
418 /* "Prefetch flush" after modifying execution status in CPSR */
419 return cortex_a8_exec_opcode(target,
420 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
421 &dscr);
422 }
423
424 static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
425 uint32_t opcode, uint32_t *data)
426 {
427 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
428 int retval;
429 uint32_t dscr = 1 << DSCR_INSTR_COMP;
430
431 /* the opcode, writing data to DCC */
432 retval = cortex_a8_exec_opcode(
433 a8->armv7a_common.armv4_5_common.target,
434 opcode,
435 &dscr);
436
437 return cortex_a8_read_dcc(a8, data, &dscr);
438 }
439
440
441 static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
442 uint32_t opcode, uint32_t *data)
443 {
444 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
445 uint32_t dscr = 1 << DSCR_INSTR_COMP;
446 int retval;
447
448 /* the opcode, writing data to R0 */
449 retval = cortex_a8_exec_opcode(
450 a8->armv7a_common.armv4_5_common.target,
451 opcode,
452 &dscr);
453
454 /* write R0 to DCC */
455 retval = cortex_a8_exec_opcode(
456 a8->armv7a_common.armv4_5_common.target,
457 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
458 &dscr);
459
460 return cortex_a8_read_dcc(a8, data, &dscr);
461 }
462
463 static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index,
464 uint32_t addr, uint32_t control)
465 {
466 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
467 uint32_t vr = a8->armv7a_common.debug_base;
468 uint32_t cr = a8->armv7a_common.debug_base;
469 int retval;
470
471 switch (index) {
472 case 0 ... 15: /* breakpoints */
473 vr += CPUDBG_BVR_BASE;
474 cr += CPUDBG_BCR_BASE;
475 break;
476 case 16 ... 31: /* watchpoints */
477 vr += CPUDBG_WVR_BASE;
478 cr += CPUDBG_WCR_BASE;
479 index -= 16;
480 break;
481 default:
482 return ERROR_FAIL;
483 }
484 vr += 4 * index;
485 cr += 4 * index;
486
487 LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
488 (unsigned) vr, (unsigned) cr);
489
490 retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
491 vr, addr);
492 if (retval != ERROR_OK)
493 return retval;
494 retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
495 cr, control);
496 return retval;
497 }
498
499 static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index)
500 {
501 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
502 uint32_t cr;
503
504 switch (index) {
505 case 0 ... 15:
506 cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE;
507 break;
508 case 16 ... 31:
509 cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE;
510 index -= 16;
511 break;
512 default:
513 return ERROR_FAIL;
514 }
515 cr += 4 * index;
516
517 LOG_DEBUG("A8: bpwp disable, cr %08x", (unsigned) cr);
518
519 /* clear control register */
520 return cortex_a8_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
521 }
522
523 static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
524 {
525 struct arm_dpm *dpm = &a8->armv7a_common.dpm;
526
527 dpm->arm = &a8->armv7a_common.armv4_5_common;
528 dpm->didr = didr;
529
530 dpm->prepare = cortex_a8_dpm_prepare;
531 dpm->finish = cortex_a8_dpm_finish;
532
533 dpm->instr_write_data_dcc = cortex_a8_instr_write_data_dcc;
534 dpm->instr_write_data_r0 = cortex_a8_instr_write_data_r0;
535 dpm->instr_cpsr_sync = cortex_a8_instr_cpsr_sync;
536
537 dpm->instr_read_data_dcc = cortex_a8_instr_read_data_dcc;
538 dpm->instr_read_data_r0 = cortex_a8_instr_read_data_r0;
539
540 dpm->bpwp_enable = cortex_a8_bpwp_enable;
541 dpm->bpwp_disable = cortex_a8_bpwp_disable;
542
543 return arm_dpm_setup(dpm);
544 }
545
546
547 /*
548 * Cortex-A8 Run control
549 */
550
551 static int cortex_a8_poll(struct target *target)
552 {
553 int retval = ERROR_OK;
554 uint32_t dscr;
555 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
556 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
557 struct swjdp_common *swjdp = &armv7a->swjdp_info;
558 enum target_state prev_target_state = target->state;
559 uint8_t saved_apsel = dap_ap_get_select(swjdp);
560
561 dap_ap_select(swjdp, swjdp_debugap);
562 retval = mem_ap_read_atomic_u32(swjdp,
563 armv7a->debug_base + CPUDBG_DSCR, &dscr);
564 if (retval != ERROR_OK)
565 {
566 dap_ap_select(swjdp, saved_apsel);
567 return retval;
568 }
569 cortex_a8->cpudbg_dscr = dscr;
570
571 if ((dscr & 0x3) == 0x3)
572 {
573 if (prev_target_state != TARGET_HALTED)
574 {
575 /* We have a halting debug event */
576 LOG_DEBUG("Target halted");
577 target->state = TARGET_HALTED;
578 if ((prev_target_state == TARGET_RUNNING)
579 || (prev_target_state == TARGET_RESET))
580 {
581 retval = cortex_a8_debug_entry(target);
582 if (retval != ERROR_OK)
583 return retval;
584
585 target_call_event_callbacks(target,
586 TARGET_EVENT_HALTED);
587 }
588 if (prev_target_state == TARGET_DEBUG_RUNNING)
589 {
590 LOG_DEBUG(" ");
591
592 retval = cortex_a8_debug_entry(target);
593 if (retval != ERROR_OK)
594 return retval;
595
596 target_call_event_callbacks(target,
597 TARGET_EVENT_DEBUG_HALTED);
598 }
599 }
600 }
601 else if ((dscr & 0x3) == 0x2)
602 {
603 target->state = TARGET_RUNNING;
604 }
605 else
606 {
607 LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32, dscr);
608 target->state = TARGET_UNKNOWN;
609 }
610
611 dap_ap_select(swjdp, saved_apsel);
612
613 return retval;
614 }
615
616 static int cortex_a8_halt(struct target *target)
617 {
618 int retval = ERROR_OK;
619 uint32_t dscr;
620 struct armv7a_common *armv7a = target_to_armv7a(target);
621 struct swjdp_common *swjdp = &armv7a->swjdp_info;
622 uint8_t saved_apsel = dap_ap_get_select(swjdp);
623 dap_ap_select(swjdp, swjdp_debugap);
624
625 /*
626 * Tell the core to be halted by writing DRCR with 0x1
627 * and then wait for the core to be halted.
628 */
629 retval = mem_ap_write_atomic_u32(swjdp,
630 armv7a->debug_base + CPUDBG_DRCR, 0x1);
631
632 /*
633 * enter halting debug mode
634 */
635 mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr);
636 retval = mem_ap_write_atomic_u32(swjdp,
637 armv7a->debug_base + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE));
638
639 if (retval != ERROR_OK)
640 goto out;
641
642 do {
643 mem_ap_read_atomic_u32(swjdp,
644 armv7a->debug_base + CPUDBG_DSCR, &dscr);
645 } while ((dscr & (1 << DSCR_CORE_HALTED)) == 0);
646
647 target->debug_reason = DBG_REASON_DBGRQ;
648
649 out:
650 dap_ap_select(swjdp, saved_apsel);
651 return retval;
652 }
653
654 static int cortex_a8_resume(struct target *target, int current,
655 uint32_t address, int handle_breakpoints, int debug_execution)
656 {
657 struct armv7a_common *armv7a = target_to_armv7a(target);
658 struct arm *armv4_5 = &armv7a->armv4_5_common;
659 struct swjdp_common *swjdp = &armv7a->swjdp_info;
660
661 // struct breakpoint *breakpoint = NULL;
662 uint32_t resume_pc, dscr;
663
664 uint8_t saved_apsel = dap_ap_get_select(swjdp);
665 dap_ap_select(swjdp, swjdp_debugap);
666
667 if (!debug_execution)
668 target_free_all_working_areas(target);
669
670 #if 0
671 if (debug_execution)
672 {
673 /* Disable interrupts */
674 /* We disable interrupts in the PRIMASK register instead of
675 * masking with C_MASKINTS,
676 * This is probably the same issue as Cortex-M3 Errata 377493:
677 * C_MASKINTS in parallel with disabled interrupts can cause
678 * local faults to not be taken. */
679 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
680 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
681 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
682
683 /* Make sure we are in Thumb mode */
684 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
685 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
686 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
687 armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
688 }
689 #endif
690
691 /* current = 1: continue on current pc, otherwise continue at <address> */
692 resume_pc = buf_get_u32(
693 armv4_5->core_cache->reg_list[15].value,
694 0, 32);
695 if (!current)
696 resume_pc = address;
697
698 /* Make sure that the Armv7 gdb thumb fixups does not
699 * kill the return address
700 */
701 switch (armv4_5->core_state)
702 {
703 case ARMV4_5_STATE_ARM:
704 resume_pc &= 0xFFFFFFFC;
705 break;
706 case ARMV4_5_STATE_THUMB:
707 case ARM_STATE_THUMB_EE:
708 /* When the return address is loaded into PC
709 * bit 0 must be 1 to stay in Thumb state
710 */
711 resume_pc |= 0x1;
712 break;
713 case ARMV4_5_STATE_JAZELLE:
714 LOG_ERROR("How do I resume into Jazelle state??");
715 return ERROR_FAIL;
716 }
717 LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
718 buf_set_u32(armv4_5->core_cache->reg_list[15].value,
719 0, 32, resume_pc);
720 armv4_5->core_cache->reg_list[15].dirty = 1;
721 armv4_5->core_cache->reg_list[15].valid = 1;
722
723 cortex_a8_restore_context(target, handle_breakpoints);
724
725 #if 0
726 /* the front-end may request us not to handle breakpoints */
727 if (handle_breakpoints)
728 {
729 /* Single step past breakpoint at current address */
730 if ((breakpoint = breakpoint_find(target, resume_pc)))
731 {
732 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
733 cortex_m3_unset_breakpoint(target, breakpoint);
734 cortex_m3_single_step_core(target);
735 cortex_m3_set_breakpoint(target, breakpoint);
736 }
737 }
738
739 #endif
740 /* Restart core and wait for it to be started */
741 mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2);
742
743 do {
744 mem_ap_read_atomic_u32(swjdp,
745 armv7a->debug_base + CPUDBG_DSCR, &dscr);
746 } while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0);
747
748 target->debug_reason = DBG_REASON_NOTHALTED;
749 target->state = TARGET_RUNNING;
750
751 /* registers are now invalid */
752 register_cache_invalidate(armv4_5->core_cache);
753
754 if (!debug_execution)
755 {
756 target->state = TARGET_RUNNING;
757 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
758 LOG_DEBUG("target resumed at 0x%" PRIx32, resume_pc);
759 }
760 else
761 {
762 target->state = TARGET_DEBUG_RUNNING;
763 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
764 LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc);
765 }
766
767 dap_ap_select(swjdp, saved_apsel);
768
769 return ERROR_OK;
770 }
771
772 static int cortex_a8_debug_entry(struct target *target)
773 {
774 int i;
775 uint32_t regfile[16], wfar, cpsr, dscr;
776 int retval = ERROR_OK;
777 struct working_area *regfile_working_area = NULL;
778 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
779 struct armv7a_common *armv7a = target_to_armv7a(target);
780 struct arm *armv4_5 = &armv7a->armv4_5_common;
781 struct swjdp_common *swjdp = &armv7a->swjdp_info;
782 struct reg *reg;
783
784 LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
785
786 /* Enable the ITR execution once we are in debug mode */
787 mem_ap_read_atomic_u32(swjdp,
788 armv7a->debug_base + CPUDBG_DSCR, &dscr);
789
790 /* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
791 * imprecise data aborts get discarded by issuing a Data
792 * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
793 */
794
795 dscr |= (1 << DSCR_EXT_INT_EN);
796 retval = mem_ap_write_atomic_u32(swjdp,
797 armv7a->debug_base + CPUDBG_DSCR, dscr);
798
799 /* Examine debug reason */
800 switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
801 {
802 case 0: /* DRCR[0] write */
803 case 4: /* EDBGRQ */
804 target->debug_reason = DBG_REASON_DBGRQ;
805 break;
806 case 1: /* HW breakpoint */
807 case 3: /* SW BKPT */
808 case 5: /* vector catch */
809 target->debug_reason = DBG_REASON_BREAKPOINT;
810 break;
811 case 2: /* asynch watchpoint */
812 case 10: /* precise watchpoint */
813 target->debug_reason = DBG_REASON_WATCHPOINT;
814
815 /* save address of faulting instruction */
816 retval = mem_ap_read_atomic_u32(swjdp,
817 armv7a->debug_base + CPUDBG_WFAR,
818 &wfar);
819 arm_dpm_report_wfar(&armv7a->dpm, wfar);
820 break;
821 default:
822 target->debug_reason = DBG_REASON_UNDEFINED;
823 break;
824 }
825
826 /* REVISIT fast_reg_read is never set ... */
827
828 /* Examine target state and mode */
829 if (cortex_a8->fast_reg_read)
830 target_alloc_working_area(target, 64, &regfile_working_area);
831
832 /* First load register acessible through core debug port*/
833 if (!regfile_working_area)
834 {
835 retval = arm_dpm_read_current_registers(&armv7a->dpm);
836 }
837 else
838 {
839 dap_ap_select(swjdp, swjdp_memoryap);
840 cortex_a8_read_regs_through_mem(target,
841 regfile_working_area->address, regfile);
842 dap_ap_select(swjdp, swjdp_memoryap);
843 target_free_working_area(target, regfile_working_area);
844
845 /* read Current PSR */
846 cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
847 dap_ap_select(swjdp, swjdp_debugap);
848 LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
849
850 arm_set_cpsr(armv4_5, cpsr);
851
852 /* update cache */
853 for (i = 0; i <= ARM_PC; i++)
854 {
855 reg = arm_reg_current(armv4_5, i);
856
857 buf_set_u32(reg->value, 0, 32, regfile[i]);
858 reg->valid = 1;
859 reg->dirty = 0;
860 }
861
862 /* Fixup PC Resume Address */
863 if (cpsr & (1 << 5))
864 {
865 // T bit set for Thumb or ThumbEE state
866 regfile[ARM_PC] -= 4;
867 }
868 else
869 {
870 // ARM state
871 regfile[ARM_PC] -= 8;
872 }
873
874 reg = armv4_5->core_cache->reg_list + 15;
875 buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
876 reg->dirty = reg->valid;
877 }
878
879 #if 0
880 /* TODO, Move this */
881 uint32_t cp15_control_register, cp15_cacr, cp15_nacr;
882 cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
883 LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register);
884
885 cortex_a8_read_cp(target, &cp15_cacr, 15, 0, 1, 0, 2);
886 LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr);
887
888 cortex_a8_read_cp(target, &cp15_nacr, 15, 0, 1, 1, 2);
889 LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr);
890 #endif
891
892 /* Are we in an exception handler */
893 // armv4_5->exception_number = 0;
894 if (armv7a->post_debug_entry)
895 armv7a->post_debug_entry(target);
896
897 return retval;
898 }
899
900 static void cortex_a8_post_debug_entry(struct target *target)
901 {
902 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
903 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
904 int retval;
905
906 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
907 retval = armv7a->armv4_5_common.mrc(target, 15,
908 0, 0, /* op1, op2 */
909 1, 0, /* CRn, CRm */
910 &cortex_a8->cp15_control_reg);
911 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg);
912
913 if (armv7a->armv4_5_mmu.armv4_5_cache.ctype == -1)
914 {
915 uint32_t cache_type_reg;
916
917 /* MRC p15,0,<Rt>,c0,c0,1 ; Read CP15 Cache Type Register */
918 retval = armv7a->armv4_5_common.mrc(target, 15,
919 0, 1, /* op1, op2 */
920 0, 0, /* CRn, CRm */
921 &cache_type_reg);
922 LOG_DEBUG("cp15 cache type: %8.8x", (unsigned) cache_type_reg);
923
924 /* FIXME the armv4_4 cache info DOES NOT APPLY to Cortex-A8 */
925 armv4_5_identify_cache(cache_type_reg,
926 &armv7a->armv4_5_mmu.armv4_5_cache);
927 }
928
929 armv7a->armv4_5_mmu.mmu_enabled =
930 (cortex_a8->cp15_control_reg & 0x1U) ? 1 : 0;
931 armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
932 (cortex_a8->cp15_control_reg & 0x4U) ? 1 : 0;
933 armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
934 (cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0;
935
936
937 }
938
939 static int cortex_a8_step(struct target *target, int current, uint32_t address,
940 int handle_breakpoints)
941 {
942 struct armv7a_common *armv7a = target_to_armv7a(target);
943 struct arm *armv4_5 = &armv7a->armv4_5_common;
944 struct breakpoint *breakpoint = NULL;
945 struct breakpoint stepbreakpoint;
946 struct reg *r;
947
948 int timeout = 100;
949
950 if (target->state != TARGET_HALTED)
951 {
952 LOG_WARNING("target not halted");
953 return ERROR_TARGET_NOT_HALTED;
954 }
955
956 /* current = 1: continue on current pc, otherwise continue at <address> */
957 r = armv4_5->core_cache->reg_list + 15;
958 if (!current)
959 {
960 buf_set_u32(r->value, 0, 32, address);
961 }
962 else
963 {
964 address = buf_get_u32(r->value, 0, 32);
965 }
966
967 /* The front-end may request us not to handle breakpoints.
968 * But since Cortex-A8 uses breakpoint for single step,
969 * we MUST handle breakpoints.
970 */
971 handle_breakpoints = 1;
972 if (handle_breakpoints) {
973 breakpoint = breakpoint_find(target, address);
974 if (breakpoint)
975 cortex_a8_unset_breakpoint(target, breakpoint);
976 }
977
978 /* Setup single step breakpoint */
979 stepbreakpoint.address = address;
980 stepbreakpoint.length = (armv4_5->core_state == ARMV4_5_STATE_THUMB)
981 ? 2 : 4;
982 stepbreakpoint.type = BKPT_HARD;
983 stepbreakpoint.set = 0;
984
985 /* Break on IVA mismatch */
986 cortex_a8_set_breakpoint(target, &stepbreakpoint, 0x04);
987
988 target->debug_reason = DBG_REASON_SINGLESTEP;
989
990 cortex_a8_resume(target, 1, address, 0, 0);
991
992 while (target->state != TARGET_HALTED)
993 {
994 cortex_a8_poll(target);
995 if (--timeout == 0)
996 {
997 LOG_WARNING("timeout waiting for target halt");
998 break;
999 }
1000 }
1001
1002 cortex_a8_unset_breakpoint(target, &stepbreakpoint);
1003 if (timeout > 0) target->debug_reason = DBG_REASON_BREAKPOINT;
1004
1005 if (breakpoint)
1006 cortex_a8_set_breakpoint(target, breakpoint, 0);
1007
1008 if (target->state != TARGET_HALTED)
1009 LOG_DEBUG("target stepped");
1010
1011 return ERROR_OK;
1012 }
1013
1014 static int cortex_a8_restore_context(struct target *target, bool bpwp)
1015 {
1016 struct armv7a_common *armv7a = target_to_armv7a(target);
1017
1018 LOG_DEBUG(" ");
1019
1020 if (armv7a->pre_restore_context)
1021 armv7a->pre_restore_context(target);
1022
1023 arm_dpm_write_dirty_registers(&armv7a->dpm, bpwp);
1024
1025 if (armv7a->post_restore_context)
1026 armv7a->post_restore_context(target);
1027
1028 return ERROR_OK;
1029 }
1030
1031
1032 /*
1033 * Cortex-A8 Breakpoint and watchpoint fuctions
1034 */
1035
1036 /* Setup hardware Breakpoint Register Pair */
1037 static int cortex_a8_set_breakpoint(struct target *target,
1038 struct breakpoint *breakpoint, uint8_t matchmode)
1039 {
1040 int retval;
1041 int brp_i=0;
1042 uint32_t control;
1043 uint8_t byte_addr_select = 0x0F;
1044 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1045 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1046 struct cortex_a8_brp * brp_list = cortex_a8->brp_list;
1047
1048 if (breakpoint->set)
1049 {
1050 LOG_WARNING("breakpoint already set");
1051 return ERROR_OK;
1052 }
1053
1054 if (breakpoint->type == BKPT_HARD)
1055 {
1056 while (brp_list[brp_i].used && (brp_i < cortex_a8->brp_num))
1057 brp_i++ ;
1058 if (brp_i >= cortex_a8->brp_num)
1059 {
1060 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1061 return ERROR_FAIL;
1062 }
1063 breakpoint->set = brp_i + 1;
1064 if (breakpoint->length == 2)
1065 {
1066 byte_addr_select = (3 << (breakpoint->address & 0x02));
1067 }
1068 control = ((matchmode & 0x7) << 20)
1069 | (byte_addr_select << 5)
1070 | (3 << 1) | 1;
1071 brp_list[brp_i].used = 1;
1072 brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
1073 brp_list[brp_i].control = control;
1074 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1075 + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1076 brp_list[brp_i].value);
1077 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1078 + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1079 brp_list[brp_i].control);
1080 LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1081 brp_list[brp_i].control,
1082 brp_list[brp_i].value);
1083 }
1084 else if (breakpoint->type == BKPT_SOFT)
1085 {
1086 uint8_t code[4];
1087 if (breakpoint->length == 2)
1088 {
1089 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1090 }
1091 else
1092 {
1093 buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
1094 }
1095 retval = target->type->read_memory(target,
1096 breakpoint->address & 0xFFFFFFFE,
1097 breakpoint->length, 1,
1098 breakpoint->orig_instr);
1099 if (retval != ERROR_OK)
1100 return retval;
1101 retval = target->type->write_memory(target,
1102 breakpoint->address & 0xFFFFFFFE,
1103 breakpoint->length, 1, code);
1104 if (retval != ERROR_OK)
1105 return retval;
1106 breakpoint->set = 0x11; /* Any nice value but 0 */
1107 }
1108
1109 return ERROR_OK;
1110 }
1111
1112 static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1113 {
1114 int retval;
1115 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1116 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1117 struct cortex_a8_brp * brp_list = cortex_a8->brp_list;
1118
1119 if (!breakpoint->set)
1120 {
1121 LOG_WARNING("breakpoint not set");
1122 return ERROR_OK;
1123 }
1124
1125 if (breakpoint->type == BKPT_HARD)
1126 {
1127 int brp_i = breakpoint->set - 1;
1128 if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num))
1129 {
1130 LOG_DEBUG("Invalid BRP number in breakpoint");
1131 return ERROR_OK;
1132 }
1133 LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1134 brp_list[brp_i].control, brp_list[brp_i].value);
1135 brp_list[brp_i].used = 0;
1136 brp_list[brp_i].value = 0;
1137 brp_list[brp_i].control = 0;
1138 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1139 + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1140 brp_list[brp_i].control);
1141 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1142 + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1143 brp_list[brp_i].value);
1144 }
1145 else
1146 {
1147 /* restore original instruction (kept in target endianness) */
1148 if (breakpoint->length == 4)
1149 {
1150 retval = target->type->write_memory(target,
1151 breakpoint->address & 0xFFFFFFFE,
1152 4, 1, breakpoint->orig_instr);
1153 if (retval != ERROR_OK)
1154 return retval;
1155 }
1156 else
1157 {
1158 retval = target->type->write_memory(target,
1159 breakpoint->address & 0xFFFFFFFE,
1160 2, 1, breakpoint->orig_instr);
1161 if (retval != ERROR_OK)
1162 return retval;
1163 }
1164 }
1165 breakpoint->set = 0;
1166
1167 return ERROR_OK;
1168 }
1169
1170 static int cortex_a8_add_breakpoint(struct target *target,
1171 struct breakpoint *breakpoint)
1172 {
1173 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1174
1175 if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1))
1176 {
1177 LOG_INFO("no hardware breakpoint available");
1178 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1179 }
1180
1181 if (breakpoint->type == BKPT_HARD)
1182 cortex_a8->brp_num_available--;
1183 cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */
1184
1185 return ERROR_OK;
1186 }
1187
1188 static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1189 {
1190 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1191
1192 #if 0
1193 /* It is perfectly possible to remove brakpoints while the taget is running */
1194 if (target->state != TARGET_HALTED)
1195 {
1196 LOG_WARNING("target not halted");
1197 return ERROR_TARGET_NOT_HALTED;
1198 }
1199 #endif
1200
1201 if (breakpoint->set)
1202 {
1203 cortex_a8_unset_breakpoint(target, breakpoint);
1204 if (breakpoint->type == BKPT_HARD)
1205 cortex_a8->brp_num_available++ ;
1206 }
1207
1208
1209 return ERROR_OK;
1210 }
1211
1212
1213
1214 /*
1215 * Cortex-A8 Reset fuctions
1216 */
1217
1218 static int cortex_a8_assert_reset(struct target *target)
1219 {
1220 struct armv7a_common *armv7a = target_to_armv7a(target);
1221
1222 LOG_DEBUG(" ");
1223
1224 /* FIXME when halt is requested, make it work somehow... */
1225
1226 /* Issue some kind of warm reset. */
1227 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1228 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1229 } else if (jtag_get_reset_config() & RESET_HAS_SRST) {
1230 /* REVISIT handle "pulls" cases, if there's
1231 * hardware that needs them to work.
1232 */
1233 jtag_add_reset(0, 1);
1234 } else {
1235 LOG_ERROR("%s: how to reset?", target_name(target));
1236 return ERROR_FAIL;
1237 }
1238
1239 /* registers are now invalid */
1240 register_cache_invalidate(armv7a->armv4_5_common.core_cache);
1241
1242 target->state = TARGET_RESET;
1243
1244 return ERROR_OK;
1245 }
1246
1247 static int cortex_a8_deassert_reset(struct target *target)
1248 {
1249 int retval;
1250
1251 LOG_DEBUG(" ");
1252
1253 /* be certain SRST is off */
1254 jtag_add_reset(0, 0);
1255
1256 retval = cortex_a8_poll(target);
1257
1258 if (target->reset_halt) {
1259 if (target->state != TARGET_HALTED) {
1260 LOG_WARNING("%s: ran after reset and before halt ...",
1261 target_name(target));
1262 if ((retval = target_halt(target)) != ERROR_OK)
1263 return retval;
1264 }
1265 }
1266
1267 return ERROR_OK;
1268 }
1269
1270 /*
1271 * Cortex-A8 Memory access
1272 *
1273 * This is same Cortex M3 but we must also use the correct
1274 * ap number for every access.
1275 */
1276
1277 static int cortex_a8_read_memory(struct target *target, uint32_t address,
1278 uint32_t size, uint32_t count, uint8_t *buffer)
1279 {
1280 struct armv7a_common *armv7a = target_to_armv7a(target);
1281 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1282 int retval = ERROR_INVALID_ARGUMENTS;
1283
1284 /* cortex_a8 handles unaligned memory access */
1285
1286 // ??? dap_ap_select(swjdp, swjdp_memoryap);
1287
1288 if (count && buffer) {
1289 switch (size) {
1290 case 4:
1291 retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1292 break;
1293 case 2:
1294 retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1295 break;
1296 case 1:
1297 retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1298 break;
1299 }
1300 }
1301
1302 return retval;
1303 }
1304
1305 static int cortex_a8_write_memory(struct target *target, uint32_t address,
1306 uint32_t size, uint32_t count, uint8_t *buffer)
1307 {
1308 struct armv7a_common *armv7a = target_to_armv7a(target);
1309 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1310 int retval = ERROR_INVALID_ARGUMENTS;
1311
1312 // ??? dap_ap_select(swjdp, swjdp_memoryap);
1313
1314 if (count && buffer) {
1315 switch (size) {
1316 case 4:
1317 retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1318 break;
1319 case 2:
1320 retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1321 break;
1322 case 1:
1323 retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1324 break;
1325 }
1326 }
1327
1328 /* REVISIT this op is generic ARMv7-A/R stuff */
1329 if (retval == ERROR_OK && target->state == TARGET_HALTED)
1330 {
1331 struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
1332
1333 retval = dpm->prepare(dpm);
1334 if (retval != ERROR_OK)
1335 return retval;
1336
1337 /* The Cache handling will NOT work with MMU active, the
1338 * wrong addresses will be invalidated!
1339 *
1340 * For both ICache and DCache, walk all cache lines in the
1341 * address range. Cortex-A8 has fixed 64 byte line length.
1342 *
1343 * REVISIT per ARMv7, these may trigger watchpoints ...
1344 */
1345
1346 /* invalidate I-Cache */
1347 if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
1348 {
1349 /* ICIMVAU - Invalidate Cache single entry
1350 * with MVA to PoU
1351 * MCR p15, 0, r0, c7, c5, 1
1352 */
1353 for (uint32_t cacheline = address;
1354 cacheline < address + size * count;
1355 cacheline += 64) {
1356 retval = dpm->instr_write_data_r0(dpm,
1357 ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
1358 cacheline);
1359 }
1360 }
1361
1362 /* invalidate D-Cache */
1363 if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
1364 {
1365 /* DCIMVAC - Invalidate data Cache line
1366 * with MVA to PoC
1367 * MCR p15, 0, r0, c7, c6, 1
1368 */
1369 for (uint32_t cacheline = address;
1370 cacheline < address + size * count;
1371 cacheline += 64) {
1372 retval = dpm->instr_write_data_r0(dpm,
1373 ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
1374 cacheline);
1375 }
1376 }
1377
1378 /* (void) */ dpm->finish(dpm);
1379 }
1380
1381 return retval;
1382 }
1383
1384 static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address,
1385 uint32_t count, uint8_t *buffer)
1386 {
1387 return cortex_a8_write_memory(target, address, 4, count, buffer);
1388 }
1389
1390
1391 static int cortex_a8_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
1392 {
1393 #if 0
1394 u16 dcrdr;
1395
1396 mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1397 *ctrl = (uint8_t)dcrdr;
1398 *value = (uint8_t)(dcrdr >> 8);
1399
1400 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1401
1402 /* write ack back to software dcc register
1403 * signify we have read data */
1404 if (dcrdr & (1 << 0))
1405 {
1406 dcrdr = 0;
1407 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1408 }
1409 #endif
1410 return ERROR_OK;
1411 }
1412
1413
1414 static int cortex_a8_handle_target_request(void *priv)
1415 {
1416 struct target *target = priv;
1417 struct armv7a_common *armv7a = target_to_armv7a(target);
1418 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1419
1420 if (!target_was_examined(target))
1421 return ERROR_OK;
1422 if (!target->dbg_msg_enabled)
1423 return ERROR_OK;
1424
1425 if (target->state == TARGET_RUNNING)
1426 {
1427 uint8_t data = 0;
1428 uint8_t ctrl = 0;
1429
1430 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1431
1432 /* check if we have data */
1433 if (ctrl & (1 << 0))
1434 {
1435 uint32_t request;
1436
1437 /* we assume target is quick enough */
1438 request = data;
1439 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1440 request |= (data << 8);
1441 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1442 request |= (data << 16);
1443 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1444 request |= (data << 24);
1445 target_request(target, request);
1446 }
1447 }
1448
1449 return ERROR_OK;
1450 }
1451
1452 /*
1453 * Cortex-A8 target information and configuration
1454 */
1455
1456 static int cortex_a8_examine_first(struct target *target)
1457 {
1458 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1459 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1460 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1461 int i;
1462 int retval = ERROR_OK;
1463 uint32_t didr, ctypr, ttypr, cpuid;
1464
1465 LOG_DEBUG("TODO");
1466
1467 /* Here we shall insert a proper ROM Table scan */
1468 armv7a->debug_base = OMAP3530_DEBUG_BASE;
1469
1470 /* We do one extra read to ensure DAP is configured,
1471 * we call ahbap_debugport_init(swjdp) instead
1472 */
1473 ahbap_debugport_init(swjdp);
1474 mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CPUID, &cpuid);
1475 if ((retval = mem_ap_read_atomic_u32(swjdp,
1476 armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
1477 {
1478 LOG_DEBUG("Examine failed");
1479 return retval;
1480 }
1481
1482 if ((retval = mem_ap_read_atomic_u32(swjdp,
1483 armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
1484 {
1485 LOG_DEBUG("Examine failed");
1486 return retval;
1487 }
1488
1489 if ((retval = mem_ap_read_atomic_u32(swjdp,
1490 armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
1491 {
1492 LOG_DEBUG("Examine failed");
1493 return retval;
1494 }
1495
1496 if ((retval = mem_ap_read_atomic_u32(swjdp,
1497 armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK)
1498 {
1499 LOG_DEBUG("Examine failed");
1500 return retval;
1501 }
1502
1503 LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
1504 LOG_DEBUG("ctypr = 0x%08" PRIx32, ctypr);
1505 LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr);
1506 LOG_DEBUG("didr = 0x%08" PRIx32, didr);
1507
1508 armv7a->armv4_5_common.core_type = ARM_MODE_MON;
1509 cortex_a8_dpm_setup(cortex_a8, didr);
1510
1511 /* Setup Breakpoint Register Pairs */
1512 cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1;
1513 cortex_a8->brp_num_context = ((didr >> 20) & 0x0F) + 1;
1514 cortex_a8->brp_num_available = cortex_a8->brp_num;
1515 cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(struct cortex_a8_brp));
1516 // cortex_a8->brb_enabled = ????;
1517 for (i = 0; i < cortex_a8->brp_num; i++)
1518 {
1519 cortex_a8->brp_list[i].used = 0;
1520 if (i < (cortex_a8->brp_num-cortex_a8->brp_num_context))
1521 cortex_a8->brp_list[i].type = BRP_NORMAL;
1522 else
1523 cortex_a8->brp_list[i].type = BRP_CONTEXT;
1524 cortex_a8->brp_list[i].value = 0;
1525 cortex_a8->brp_list[i].control = 0;
1526 cortex_a8->brp_list[i].BRPn = i;
1527 }
1528
1529 LOG_DEBUG("Configured %i hw breakpoints", cortex_a8->brp_num);
1530
1531 target_set_examined(target);
1532 return ERROR_OK;
1533 }
1534
1535 static int cortex_a8_examine(struct target *target)
1536 {
1537 int retval = ERROR_OK;
1538
1539 /* don't re-probe hardware after each reset */
1540 if (!target_was_examined(target))
1541 retval = cortex_a8_examine_first(target);
1542
1543 /* Configure core debug access */
1544 if (retval == ERROR_OK)
1545 retval = cortex_a8_init_debug_access(target);
1546
1547 return retval;
1548 }
1549
1550 /*
1551 * Cortex-A8 target creation and initialization
1552 */
1553
1554 static int cortex_a8_init_target(struct command_context *cmd_ctx,
1555 struct target *target)
1556 {
1557 /* examine_first() does a bunch of this */
1558 return ERROR_OK;
1559 }
1560
1561 static int cortex_a8_init_arch_info(struct target *target,
1562 struct cortex_a8_common *cortex_a8, struct jtag_tap *tap)
1563 {
1564 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1565 struct arm *armv4_5 = &armv7a->armv4_5_common;
1566 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1567
1568 /* Setup struct cortex_a8_common */
1569 cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
1570 armv4_5->arch_info = armv7a;
1571
1572 /* prepare JTAG information for the new target */
1573 cortex_a8->jtag_info.tap = tap;
1574 cortex_a8->jtag_info.scann_size = 4;
1575
1576 swjdp->dp_select_value = -1;
1577 swjdp->ap_csw_value = -1;
1578 swjdp->ap_tar_value = -1;
1579 swjdp->jtag_info = &cortex_a8->jtag_info;
1580 swjdp->memaccess_tck = 80;
1581
1582 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
1583 swjdp->tar_autoincr_block = (1 << 10);
1584
1585 cortex_a8->fast_reg_read = 0;
1586
1587 /* register arch-specific functions */
1588 armv7a->examine_debug_reason = NULL;
1589
1590 armv7a->post_debug_entry = cortex_a8_post_debug_entry;
1591
1592 armv7a->pre_restore_context = NULL;
1593 armv7a->post_restore_context = NULL;
1594 armv7a->armv4_5_mmu.armv4_5_cache.ctype = -1;
1595 // armv7a->armv4_5_mmu.get_ttb = armv7a_get_ttb;
1596 armv7a->armv4_5_mmu.read_memory = cortex_a8_read_memory;
1597 armv7a->armv4_5_mmu.write_memory = cortex_a8_write_memory;
1598 // armv7a->armv4_5_mmu.disable_mmu_caches = armv7a_disable_mmu_caches;
1599 // armv7a->armv4_5_mmu.enable_mmu_caches = armv7a_enable_mmu_caches;
1600 armv7a->armv4_5_mmu.has_tiny_pages = 1;
1601 armv7a->armv4_5_mmu.mmu_enabled = 0;
1602
1603
1604 // arm7_9->handle_target_request = cortex_a8_handle_target_request;
1605
1606 /* REVISIT v7a setup should be in a v7a-specific routine */
1607 armv4_5_init_arch_info(target, armv4_5);
1608 armv7a->common_magic = ARMV7_COMMON_MAGIC;
1609
1610 target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
1611
1612 return ERROR_OK;
1613 }
1614
1615 static int cortex_a8_target_create(struct target *target, Jim_Interp *interp)
1616 {
1617 struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common));
1618
1619 cortex_a8_init_arch_info(target, cortex_a8, target->tap);
1620
1621 return ERROR_OK;
1622 }
1623
1624 COMMAND_HANDLER(cortex_a8_handle_cache_info_command)
1625 {
1626 struct target *target = get_current_target(CMD_CTX);
1627 struct armv7a_common *armv7a = target_to_armv7a(target);
1628
1629 return armv4_5_handle_cache_info_command(CMD_CTX,
1630 &armv7a->armv4_5_mmu.armv4_5_cache);
1631 }
1632
1633
1634 COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
1635 {
1636 struct target *target = get_current_target(CMD_CTX);
1637
1638 cortex_a8_init_debug_access(target);
1639
1640 return ERROR_OK;
1641 }
1642
1643 static const struct command_registration cortex_a8_exec_command_handlers[] = {
1644 {
1645 .name = "cache_info",
1646 .handler = &cortex_a8_handle_cache_info_command,
1647 .mode = COMMAND_EXEC,
1648 .help = "display information about target caches",
1649 },
1650 {
1651 .name = "dbginit",
1652 .handler = &cortex_a8_handle_dbginit_command,
1653 .mode = COMMAND_EXEC,
1654 .help = "Initialize core debug",
1655 },
1656 COMMAND_REGISTRATION_DONE
1657 };
1658 static const struct command_registration cortex_a8_command_handlers[] = {
1659 {
1660 .chain = arm_command_handlers,
1661 },
1662 {
1663 .chain = armv7a_command_handlers,
1664 },
1665 {
1666 .name = "cortex_a8",
1667 .mode = COMMAND_ANY,
1668 .help = "Cortex-A8 command group",
1669 .chain = cortex_a8_exec_command_handlers,
1670 },
1671 COMMAND_REGISTRATION_DONE
1672 };
1673
1674 struct target_type cortexa8_target = {
1675 .name = "cortex_a8",
1676
1677 .poll = cortex_a8_poll,
1678 .arch_state = armv7a_arch_state,
1679
1680 .target_request_data = NULL,
1681
1682 .halt = cortex_a8_halt,
1683 .resume = cortex_a8_resume,
1684 .step = cortex_a8_step,
1685
1686 .assert_reset = cortex_a8_assert_reset,
1687 .deassert_reset = cortex_a8_deassert_reset,
1688 .soft_reset_halt = NULL,
1689
1690 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
1691
1692 .read_memory = cortex_a8_read_memory,
1693 .write_memory = cortex_a8_write_memory,
1694 .bulk_write_memory = cortex_a8_bulk_write_memory,
1695
1696 .checksum_memory = arm_checksum_memory,
1697 .blank_check_memory = arm_blank_check_memory,
1698
1699 .run_algorithm = armv4_5_run_algorithm,
1700
1701 .add_breakpoint = cortex_a8_add_breakpoint,
1702 .remove_breakpoint = cortex_a8_remove_breakpoint,
1703 .add_watchpoint = NULL,
1704 .remove_watchpoint = NULL,
1705
1706 .commands = cortex_a8_command_handlers,
1707 .target_create = cortex_a8_target_create,
1708 .init_target = cortex_a8_init_target,
1709 .examine = cortex_a8_examine,
1710 };
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