1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
29 * Cortex-A8(tm) TRM, ARM DDI 0344H *
31 ***************************************************************************/
36 #include "cortex_a8.h"
37 #include "target_request.h"
41 int cortex_a8_register_commands(struct command_context_s
*cmd_ctx
);
43 /* forward declarations */
44 int cortex_a8_target_create(struct target_s
*target
, Jim_Interp
*interp
);
46 target_type_t cortexa8_target
=
51 .arch_state
= armv7m_arch_state
,
53 .target_request_data
= NULL
,
60 .deassert_reset
= NULL
,
61 .soft_reset_halt
= NULL
,
63 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
65 .read_memory
= cortex_a8_read_memory
,
66 .write_memory
= cortex_a8_write_memory
,
67 .bulk_write_memory
= NULL
,
68 .checksum_memory
= NULL
,
69 .blank_check_memory
= NULL
,
71 .run_algorithm
= armv7m_run_algorithm
,
73 .add_breakpoint
= NULL
,
74 .remove_breakpoint
= NULL
,
75 .add_watchpoint
= NULL
,
76 .remove_watchpoint
= NULL
,
78 .register_commands
= cortex_a8_register_commands
,
79 .target_create
= cortex_a8_target_create
,
85 int cortex_a8_dcc_read(swjdp_common_t
*swjdp
, u8
*value
, u8
*ctrl
)
89 mem_ap_read_buf_u16( swjdp
, (u8
*)&dcrdr
, 1, DCB_DCRDR
);
91 *value
= (u8
)(dcrdr
>> 8);
93 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
95 /* write ack back to software dcc register
96 * signify we have read data */
100 mem_ap_write_buf_u16( swjdp
, (u8
*)&dcrdr
, 1, DCB_DCRDR
);
106 int cortex_a8_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
108 /* get pointers to arch-specific information */
109 armv7m_common_t
*armv7m
= target
->arch_info
;
110 swjdp_common_t
*swjdp
= &armv7m
->swjdp_info
;
113 /* sanitize arguments */
114 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
115 return ERROR_INVALID_ARGUMENTS
;
117 /* cortex_a8 handles unaligned memory access */
122 retval
= mem_ap_read_buf_u32(swjdp
, buffer
, 4 * count
, address
);
125 retval
= mem_ap_read_buf_u16(swjdp
, buffer
, 2 * count
, address
);
128 retval
= mem_ap_read_buf_u8(swjdp
, buffer
, count
, address
);
131 LOG_ERROR("BUG: we shouldn't get here");
138 int cortex_a8_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
140 /* get pointers to arch-specific information */
141 armv7m_common_t
*armv7m
= target
->arch_info
;
142 swjdp_common_t
*swjdp
= &armv7m
->swjdp_info
;
145 /* sanitize arguments */
146 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
147 return ERROR_INVALID_ARGUMENTS
;
152 retval
= mem_ap_write_buf_u32(swjdp
, buffer
, 4 * count
, address
);
155 retval
= mem_ap_write_buf_u16(swjdp
, buffer
, 2 * count
, address
);
158 retval
= mem_ap_write_buf_u8(swjdp
, buffer
, count
, address
);
161 LOG_ERROR("BUG: we shouldn't get here");
168 int cortex_a8_handle_target_request(void *priv
)
170 target_t
*target
= priv
;
171 if (!target
->type
->examined
)
173 armv7m_common_t
*armv7m
= target
->arch_info
;
174 swjdp_common_t
*swjdp
= &armv7m
->swjdp_info
;
176 if (!target
->dbg_msg_enabled
)
179 if (target
->state
== TARGET_RUNNING
)
184 cortex_a8_dcc_read(swjdp
, &data
, &ctrl
);
186 /* check if we have data */
191 /* we assume target is quick enough */
193 cortex_a8_dcc_read(swjdp
, &data
, &ctrl
);
194 request
|= (data
<< 8);
195 cortex_a8_dcc_read(swjdp
, &data
, &ctrl
);
196 request
|= (data
<< 16);
197 cortex_a8_dcc_read(swjdp
, &data
, &ctrl
);
198 request
|= (data
<< 24);
199 target_request(target
, request
);
206 int cortex_a8_init_arch_info(target_t
*target
, cortex_a8_common_t
*cortex_a8
, jtag_tap_t
*tap
)
208 armv7m_common_t
*armv7m
;
209 armv7m
= &cortex_a8
->armv7m
;
211 /* prepare JTAG information for the new target */
212 cortex_a8
->jtag_info
.tap
= tap
;
213 cortex_a8
->jtag_info
.scann_size
= 4;
215 armv7m
->swjdp_info
.dp_select_value
= -1;
216 armv7m
->swjdp_info
.ap_csw_value
= -1;
217 armv7m
->swjdp_info
.ap_tar_value
= -1;
218 armv7m
->swjdp_info
.jtag_info
= &cortex_a8
->jtag_info
;
220 /* initialize arch-specific breakpoint handling */
222 cortex_a8
->common_magic
= CORTEX_A8_COMMON_MAGIC
;
223 cortex_a8
->arch_info
= NULL
;
225 /* register arch-specific functions */
226 armv7m
->examine_debug_reason
= NULL
;
228 armv7m
->pre_debug_entry
= NULL
;
229 armv7m
->post_debug_entry
= NULL
;
231 armv7m
->pre_restore_context
= NULL
;
232 armv7m
->post_restore_context
= NULL
;
234 armv7m_init_arch_info(target
, armv7m
);
235 armv7m
->arch_info
= cortex_a8
;
236 armv7m
->load_core_reg_u32
= NULL
;
237 armv7m
->store_core_reg_u32
= NULL
;
239 target_register_timer_callback(cortex_a8_handle_target_request
, 1, 1, target
);
244 int cortex_a8_target_create(struct target_s
*target
, Jim_Interp
*interp
)
246 cortex_a8_common_t
*cortex_a8
= calloc(1,sizeof(cortex_a8_common_t
));
248 cortex_a8_init_arch_info(target
, cortex_a8
, target
->tap
);
253 int cortex_a8_register_commands(struct command_context_s
*cmd_ctx
)
257 retval
= armv7m_register_commands(cmd_ctx
);
259 register_command(cmd_ctx
, NULL
, "cortex_a8", NULL
, COMMAND_ANY
, "cortex_a8 specific commands");
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)