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target: generic ARM CTI function wrapper
[openocd.git] / src / target / armv8_dpm.c
1 /*
2 * Copyright (C) 2009 by David Brownell
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16 #ifdef HAVE_CONFIG_H
17 #include "config.h"
18 #endif
19
20 #include "arm.h"
21 #include "armv8.h"
22 #include "armv8_dpm.h"
23 #include <jtag/jtag.h>
24 #include "register.h"
25 #include "breakpoints.h"
26 #include "target_type.h"
27 #include "armv8_opcodes.h"
28
29 #include "helper/time_support.h"
30
31 /* T32 ITR format */
32 #define T32_FMTITR(instr) (((instr & 0x0000FFFF) << 16) | ((instr & 0xFFFF0000) >> 16))
33
34 /**
35 * @file
36 * Implements various ARM DPM operations using architectural debug registers.
37 * These routines layer over core-specific communication methods to cope with
38 * implementation differences between cores like ARM1136 and Cortex-A8.
39 *
40 * The "Debug Programmers' Model" (DPM) for ARMv6 and ARMv7 is defined by
41 * Part C (Debug Architecture) of the ARM Architecture Reference Manual,
42 * ARMv7-A and ARMv7-R edition (ARM DDI 0406B). In OpenOCD, DPM operations
43 * are abstracted through internal programming interfaces to share code and
44 * to minimize needless differences in debug behavior between cores.
45 */
46
47 /**
48 * Get core state from EDSCR, without necessity to retrieve CPSR
49 */
50 enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm)
51 {
52 int el = (dpm->dscr >> 8) & 0x3;
53 int rw = (dpm->dscr >> 10) & 0xF;
54
55 dpm->last_el = el;
56
57 /* In Debug state, each bit gives the current Execution state of each EL */
58 if ((rw >> el) & 0b1)
59 return ARM_STATE_AARCH64;
60
61 return ARM_STATE_ARM;
62 }
63
64 /*----------------------------------------------------------------------*/
65
66 static int dpmv8_write_dcc(struct armv8_common *armv8, uint32_t data)
67 {
68 return mem_ap_write_u32(armv8->debug_ap,
69 armv8->debug_base + CPUV8_DBG_DTRRX, data);
70 }
71
72 static int dpmv8_write_dcc_64(struct armv8_common *armv8, uint64_t data)
73 {
74 int ret;
75 ret = mem_ap_write_u32(armv8->debug_ap,
76 armv8->debug_base + CPUV8_DBG_DTRRX, data);
77 if (ret == ERROR_OK)
78 ret = mem_ap_write_u32(armv8->debug_ap,
79 armv8->debug_base + CPUV8_DBG_DTRTX, data >> 32);
80 return ret;
81 }
82
83 static int dpmv8_read_dcc(struct armv8_common *armv8, uint32_t *data,
84 uint32_t *dscr_p)
85 {
86 uint32_t dscr = DSCR_ITE;
87 int retval;
88
89 if (dscr_p)
90 dscr = *dscr_p;
91
92 /* Wait for DTRRXfull */
93 long long then = timeval_ms();
94 while ((dscr & DSCR_DTR_TX_FULL) == 0) {
95 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
96 armv8->debug_base + CPUV8_DBG_DSCR,
97 &dscr);
98 if (retval != ERROR_OK)
99 return retval;
100 if (timeval_ms() > then + 1000) {
101 LOG_ERROR("Timeout waiting for read dcc");
102 return ERROR_FAIL;
103 }
104 }
105
106 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
107 armv8->debug_base + CPUV8_DBG_DTRTX,
108 data);
109 if (retval != ERROR_OK)
110 return retval;
111
112 if (dscr_p)
113 *dscr_p = dscr;
114
115 return retval;
116 }
117
118 static int dpmv8_read_dcc_64(struct armv8_common *armv8, uint64_t *data,
119 uint32_t *dscr_p)
120 {
121 uint32_t dscr = DSCR_ITE;
122 uint32_t higher;
123 int retval;
124
125 if (dscr_p)
126 dscr = *dscr_p;
127
128 /* Wait for DTRRXfull */
129 long long then = timeval_ms();
130 while ((dscr & DSCR_DTR_TX_FULL) == 0) {
131 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
132 armv8->debug_base + CPUV8_DBG_DSCR,
133 &dscr);
134 if (retval != ERROR_OK)
135 return retval;
136 if (timeval_ms() > then + 1000) {
137 LOG_ERROR("Timeout waiting for DTR_TX_FULL, dscr = 0x%08" PRIx32, dscr);
138 return ERROR_FAIL;
139 }
140 }
141
142 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
143 armv8->debug_base + CPUV8_DBG_DTRTX,
144 (uint32_t *)data);
145 if (retval != ERROR_OK)
146 return retval;
147
148 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
149 armv8->debug_base + CPUV8_DBG_DTRRX,
150 &higher);
151 if (retval != ERROR_OK)
152 return retval;
153
154 *data = *(uint32_t *)data | (uint64_t)higher << 32;
155
156 if (dscr_p)
157 *dscr_p = dscr;
158
159 return retval;
160 }
161
162 static int dpmv8_dpm_prepare(struct arm_dpm *dpm)
163 {
164 struct armv8_common *armv8 = dpm->arm->arch_info;
165 uint32_t dscr;
166 int retval;
167
168 /* set up invariant: ITE is set after ever DPM operation */
169 long long then = timeval_ms();
170 for (;; ) {
171 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
172 armv8->debug_base + CPUV8_DBG_DSCR,
173 &dscr);
174 if (retval != ERROR_OK)
175 return retval;
176 if ((dscr & DSCR_ITE) != 0)
177 break;
178 if (timeval_ms() > then + 1000) {
179 LOG_ERROR("Timeout waiting for dpm prepare");
180 return ERROR_FAIL;
181 }
182 }
183
184 /* update the stored copy of dscr */
185 dpm->dscr = dscr;
186
187 /* this "should never happen" ... */
188 if (dscr & DSCR_DTR_RX_FULL) {
189 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
190 /* Clear DCCRX */
191 retval = mem_ap_read_u32(armv8->debug_ap,
192 armv8->debug_base + CPUV8_DBG_DTRRX, &dscr);
193 if (retval != ERROR_OK)
194 return retval;
195 }
196
197 return retval;
198 }
199
200 static int dpmv8_dpm_finish(struct arm_dpm *dpm)
201 {
202 /* REVISIT what could be done here? */
203 return ERROR_OK;
204 }
205
206 static int dpmv8_exec_opcode(struct arm_dpm *dpm,
207 uint32_t opcode, uint32_t *p_dscr)
208 {
209 struct armv8_common *armv8 = dpm->arm->arch_info;
210 uint32_t dscr = dpm->dscr;
211 int retval;
212
213 if (p_dscr)
214 dscr = *p_dscr;
215
216 /* Wait for InstrCompl bit to be set */
217 long long then = timeval_ms();
218 while ((dscr & DSCR_ITE) == 0) {
219 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
220 armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
221 if (retval != ERROR_OK) {
222 LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
223 return retval;
224 }
225 if (timeval_ms() > then + 1000) {
226 LOG_ERROR("Timeout waiting for aarch64_exec_opcode");
227 return ERROR_FAIL;
228 }
229 }
230
231 if (armv8_dpm_get_core_state(dpm) != ARM_STATE_AARCH64)
232 opcode = T32_FMTITR(opcode);
233
234 retval = mem_ap_write_u32(armv8->debug_ap,
235 armv8->debug_base + CPUV8_DBG_ITR, opcode);
236 if (retval != ERROR_OK)
237 return retval;
238
239 then = timeval_ms();
240 do {
241 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
242 armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
243 if (retval != ERROR_OK) {
244 LOG_ERROR("Could not read DSCR register");
245 return retval;
246 }
247 if (timeval_ms() > then + 1000) {
248 LOG_ERROR("Timeout waiting for aarch64_exec_opcode");
249 return ERROR_FAIL;
250 }
251 } while ((dscr & DSCR_ITE) == 0); /* Wait for InstrCompl bit to be set */
252
253 /* update dscr and el after each command execution */
254 dpm->dscr = dscr;
255 if (dpm->last_el != ((dscr >> 8) & 3))
256 LOG_DEBUG("EL %i -> %i", dpm->last_el, (dscr >> 8) & 3);
257 dpm->last_el = (dscr >> 8) & 3;
258
259 if (dscr & DSCR_ERR) {
260 LOG_ERROR("Opcode 0x%08"PRIx32", DSCR.ERR=1, DSCR.EL=%i", opcode, dpm->last_el);
261 armv8_dpm_handle_exception(dpm);
262 retval = ERROR_FAIL;
263 }
264
265 if (p_dscr)
266 *p_dscr = dscr;
267
268 return retval;
269 }
270
271 static int dpmv8_instr_execute(struct arm_dpm *dpm, uint32_t opcode)
272 {
273 return dpmv8_exec_opcode(dpm, opcode, NULL);
274 }
275
276 static int dpmv8_instr_write_data_dcc(struct arm_dpm *dpm,
277 uint32_t opcode, uint32_t data)
278 {
279 struct armv8_common *armv8 = dpm->arm->arch_info;
280 int retval;
281
282 retval = dpmv8_write_dcc(armv8, data);
283 if (retval != ERROR_OK)
284 return retval;
285
286 return dpmv8_exec_opcode(dpm, opcode, 0);
287 }
288
289 static int dpmv8_instr_write_data_dcc_64(struct arm_dpm *dpm,
290 uint32_t opcode, uint64_t data)
291 {
292 struct armv8_common *armv8 = dpm->arm->arch_info;
293 int retval;
294
295 retval = dpmv8_write_dcc_64(armv8, data);
296 if (retval != ERROR_OK)
297 return retval;
298
299 return dpmv8_exec_opcode(dpm, opcode, 0);
300 }
301
302 static int dpmv8_instr_write_data_r0(struct arm_dpm *dpm,
303 uint32_t opcode, uint32_t data)
304 {
305 struct armv8_common *armv8 = dpm->arm->arch_info;
306 uint32_t dscr = DSCR_ITE;
307 int retval;
308
309 retval = dpmv8_write_dcc(armv8, data);
310 if (retval != ERROR_OK)
311 return retval;
312
313 retval = dpmv8_exec_opcode(dpm, armv8_opcode(armv8, READ_REG_DTRRX), &dscr);
314 if (retval != ERROR_OK)
315 return retval;
316
317 /* then the opcode, taking data from R0 */
318 return dpmv8_exec_opcode(dpm, opcode, &dscr);
319 }
320
321 static int dpmv8_instr_write_data_r0_64(struct arm_dpm *dpm,
322 uint32_t opcode, uint64_t data)
323 {
324 struct armv8_common *armv8 = dpm->arm->arch_info;
325 int retval;
326
327 if (dpm->arm->core_state != ARM_STATE_AARCH64)
328 return dpmv8_instr_write_data_r0(dpm, opcode, data);
329
330 /* transfer data from DCC to R0 */
331 retval = dpmv8_write_dcc_64(armv8, data);
332 if (retval == ERROR_OK)
333 retval = dpmv8_exec_opcode(dpm, ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), &dpm->dscr);
334
335 /* then the opcode, taking data from R0 */
336 if (retval == ERROR_OK)
337 retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
338
339 return retval;
340 }
341
342 static int dpmv8_instr_cpsr_sync(struct arm_dpm *dpm)
343 {
344 int retval;
345 struct armv8_common *armv8 = dpm->arm->arch_info;
346
347 /* "Prefetch flush" after modifying execution status in CPSR */
348 retval = dpmv8_exec_opcode(dpm, armv8_opcode(armv8, ARMV8_OPC_DSB_SY), &dpm->dscr);
349 if (retval == ERROR_OK)
350 dpmv8_exec_opcode(dpm, armv8_opcode(armv8, ARMV8_OPC_ISB_SY), &dpm->dscr);
351 return retval;
352 }
353
354 static int dpmv8_instr_read_data_dcc(struct arm_dpm *dpm,
355 uint32_t opcode, uint32_t *data)
356 {
357 struct armv8_common *armv8 = dpm->arm->arch_info;
358 int retval;
359
360 /* the opcode, writing data to DCC */
361 retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
362 if (retval != ERROR_OK)
363 return retval;
364
365 return dpmv8_read_dcc(armv8, data, &dpm->dscr);
366 }
367
368 static int dpmv8_instr_read_data_dcc_64(struct arm_dpm *dpm,
369 uint32_t opcode, uint64_t *data)
370 {
371 struct armv8_common *armv8 = dpm->arm->arch_info;
372 int retval;
373
374 /* the opcode, writing data to DCC */
375 retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
376 if (retval != ERROR_OK)
377 return retval;
378
379 return dpmv8_read_dcc_64(armv8, data, &dpm->dscr);
380 }
381
382 static int dpmv8_instr_read_data_r0(struct arm_dpm *dpm,
383 uint32_t opcode, uint32_t *data)
384 {
385 struct armv8_common *armv8 = dpm->arm->arch_info;
386 int retval;
387
388 /* the opcode, writing data to R0 */
389 retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
390 if (retval != ERROR_OK)
391 return retval;
392
393 /* write R0 to DCC */
394 retval = dpmv8_exec_opcode(dpm, armv8_opcode(armv8, WRITE_REG_DTRTX), &dpm->dscr);
395 if (retval != ERROR_OK)
396 return retval;
397
398 return dpmv8_read_dcc(armv8, data, &dpm->dscr);
399 }
400
401 static int dpmv8_instr_read_data_r0_64(struct arm_dpm *dpm,
402 uint32_t opcode, uint64_t *data)
403 {
404 struct armv8_common *armv8 = dpm->arm->arch_info;
405 int retval;
406
407 if (dpm->arm->core_state != ARM_STATE_AARCH64) {
408 uint32_t tmp;
409 retval = dpmv8_instr_read_data_r0(dpm, opcode, &tmp);
410 if (retval == ERROR_OK)
411 *data = tmp;
412 return retval;
413 }
414
415 /* the opcode, writing data to R0 */
416 retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
417 if (retval != ERROR_OK)
418 return retval;
419
420 /* write R0 to DCC */
421 retval = dpmv8_exec_opcode(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0), &dpm->dscr);
422 if (retval != ERROR_OK)
423 return retval;
424
425 return dpmv8_read_dcc_64(armv8, data, &dpm->dscr);
426 }
427
428 #if 0
429 static int dpmv8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
430 target_addr_t addr, uint32_t control)
431 {
432 struct armv8_common *armv8 = dpm->arm->arch_info;
433 uint32_t vr = armv8->debug_base;
434 uint32_t cr = armv8->debug_base;
435 int retval;
436
437 switch (index_t) {
438 case 0 ... 15: /* breakpoints */
439 vr += CPUV8_DBG_BVR_BASE;
440 cr += CPUV8_DBG_BCR_BASE;
441 break;
442 case 16 ... 31: /* watchpoints */
443 vr += CPUV8_DBG_WVR_BASE;
444 cr += CPUV8_DBG_WCR_BASE;
445 index_t -= 16;
446 break;
447 default:
448 return ERROR_FAIL;
449 }
450 vr += 16 * index_t;
451 cr += 16 * index_t;
452
453 LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
454 (unsigned) vr, (unsigned) cr);
455
456 retval = mem_ap_write_atomic_u32(armv8->debug_ap, vr, addr);
457 if (retval != ERROR_OK)
458 return retval;
459 return mem_ap_write_atomic_u32(armv8->debug_ap, cr, control);
460 }
461 #endif
462
463 static int dpmv8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
464 {
465 struct armv8_common *armv8 = dpm->arm->arch_info;
466 uint32_t cr;
467
468 switch (index_t) {
469 case 0 ... 15:
470 cr = armv8->debug_base + CPUV8_DBG_BCR_BASE;
471 break;
472 case 16 ... 31:
473 cr = armv8->debug_base + CPUV8_DBG_WCR_BASE;
474 index_t -= 16;
475 break;
476 default:
477 return ERROR_FAIL;
478 }
479 cr += 16 * index_t;
480
481 LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr);
482
483 /* clear control register */
484 return mem_ap_write_atomic_u32(armv8->debug_ap, cr, 0);
485 }
486
487 /*
488 * Coprocessor support
489 */
490
491 /* Read coprocessor */
492 static int dpmv8_mrc(struct target *target, int cpnum,
493 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
494 uint32_t *value)
495 {
496 struct arm *arm = target_to_arm(target);
497 struct arm_dpm *dpm = arm->dpm;
498 int retval;
499
500 retval = dpm->prepare(dpm);
501 if (retval != ERROR_OK)
502 return retval;
503
504 LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
505 (int) op1, (int) CRn,
506 (int) CRm, (int) op2);
507
508 /* read coprocessor register into R0; return via DCC */
509 retval = dpm->instr_read_data_r0(dpm,
510 ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
511 value);
512
513 /* (void) */ dpm->finish(dpm);
514 return retval;
515 }
516
517 static int dpmv8_mcr(struct target *target, int cpnum,
518 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
519 uint32_t value)
520 {
521 struct arm *arm = target_to_arm(target);
522 struct arm_dpm *dpm = arm->dpm;
523 int retval;
524
525 retval = dpm->prepare(dpm);
526 if (retval != ERROR_OK)
527 return retval;
528
529 LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
530 (int) op1, (int) CRn,
531 (int) CRm, (int) op2);
532
533 /* read DCC into r0; then write coprocessor register from R0 */
534 retval = dpm->instr_write_data_r0(dpm,
535 ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
536 value);
537
538 /* (void) */ dpm->finish(dpm);
539 return retval;
540 }
541
542 /*----------------------------------------------------------------------*/
543
544 /*
545 * Register access utilities
546 */
547
548 int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
549 {
550 struct armv8_common *armv8 = (struct armv8_common *)dpm->arm->arch_info;
551 int retval = ERROR_OK;
552 unsigned int target_el;
553 enum arm_state core_state;
554 uint32_t cpsr;
555
556 /* restore previous mode */
557 if (mode == ARM_MODE_ANY) {
558 cpsr = buf_get_u32(dpm->arm->cpsr->value, 0, 32);
559
560 LOG_DEBUG("restoring mode, cpsr = 0x%08"PRIx32, cpsr);
561
562 } else {
563 LOG_DEBUG("setting mode 0x%"PRIx32, mode);
564
565 /* else force to the specified mode */
566 if (is_arm_mode(mode))
567 cpsr = mode;
568 else
569 cpsr = mode >> 4;
570 }
571
572 switch (cpsr & 0x1f) {
573 /* aarch32 modes */
574 case ARM_MODE_USR:
575 target_el = 0;
576 break;
577 case ARM_MODE_SVC:
578 case ARM_MODE_ABT:
579 case ARM_MODE_IRQ:
580 case ARM_MODE_FIQ:
581 target_el = 1;
582 break;
583 /*
584 * TODO: handle ARM_MODE_HYP
585 * case ARM_MODE_HYP:
586 * target_el = 2;
587 * break;
588 */
589 case ARM_MODE_MON:
590 target_el = 3;
591 break;
592 /* aarch64 modes */
593 default:
594 target_el = (cpsr >> 2) & 3;
595 }
596
597 if (target_el > SYSTEM_CUREL_EL3) {
598 LOG_ERROR("%s: Invalid target exception level %i", __func__, target_el);
599 return ERROR_FAIL;
600 }
601
602 LOG_DEBUG("target_el = %i, last_el = %i", target_el, dpm->last_el);
603 if (target_el > dpm->last_el) {
604 retval = dpm->instr_execute(dpm,
605 armv8_opcode(armv8, ARMV8_OPC_DCPS) | target_el);
606
607 /* DCPS clobbers registers just like an exception taken */
608 armv8_dpm_handle_exception(dpm);
609 } else {
610 core_state = armv8_dpm_get_core_state(dpm);
611 if (core_state != ARM_STATE_AARCH64) {
612 /* cannot do DRPS/ERET when already in EL0 */
613 if (dpm->last_el != 0) {
614 /* load SPSR with the desired mode and execute DRPS */
615 LOG_DEBUG("SPSR = 0x%08"PRIx32, cpsr);
616 retval = dpm->instr_write_data_r0(dpm,
617 ARMV8_MSR_GP_xPSR_T1(1, 0, 15), cpsr);
618 if (retval == ERROR_OK)
619 retval = dpm->instr_execute(dpm, armv8_opcode(armv8, ARMV8_OPC_DRPS));
620 }
621 } else {
622 /*
623 * need to execute multiple DRPS instructions until target_el
624 * is reached
625 */
626 while (retval == ERROR_OK && dpm->last_el != target_el) {
627 unsigned int cur_el = dpm->last_el;
628 retval = dpm->instr_execute(dpm, armv8_opcode(armv8, ARMV8_OPC_DRPS));
629 if (cur_el == dpm->last_el) {
630 LOG_INFO("Cannot reach EL %i, SPSR corrupted?", target_el);
631 break;
632 }
633 }
634 }
635
636 /* On executing DRPS, DSPSR and DLR become UNKNOWN, mark them as dirty */
637 dpm->arm->cpsr->dirty = true;
638 dpm->arm->pc->dirty = true;
639
640 /*
641 * re-evaluate the core state, we might be in Aarch32 state now
642 * we rely on dpm->dscr being up-to-date
643 */
644 core_state = armv8_dpm_get_core_state(dpm);
645 armv8_select_opcodes(armv8, core_state == ARM_STATE_AARCH64);
646 armv8_select_reg_access(armv8, core_state == ARM_STATE_AARCH64);
647 }
648
649 return retval;
650 }
651
652 /*
653 * Common register read, relies on armv8_select_reg_access() having been called.
654 */
655 static int dpmv8_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
656 {
657 struct armv8_common *armv8 = dpm->arm->arch_info;
658 uint64_t value_64;
659 int retval;
660
661 retval = armv8->read_reg_u64(armv8, regnum, &value_64);
662
663 if (retval == ERROR_OK) {
664 r->valid = true;
665 r->dirty = false;
666 buf_set_u64(r->value, 0, r->size, value_64);
667 if (r->size == 64)
668 LOG_DEBUG("READ: %s, %16.8llx", r->name, (unsigned long long) value_64);
669 else
670 LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned int) value_64);
671 }
672 return ERROR_OK;
673 }
674
675 /*
676 * Common register write, relies on armv8_select_reg_access() having been called.
677 */
678 static int dpmv8_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
679 {
680 struct armv8_common *armv8 = dpm->arm->arch_info;
681 int retval = ERROR_FAIL;
682 uint64_t value_64;
683
684 value_64 = buf_get_u64(r->value, 0, r->size);
685
686 retval = armv8->write_reg_u64(armv8, regnum, value_64);
687 if (retval == ERROR_OK) {
688 r->dirty = false;
689 if (r->size == 64)
690 LOG_DEBUG("WRITE: %s, %16.8llx", r->name, (unsigned long long)value_64);
691 else
692 LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned int)value_64);
693 }
694
695 return ERROR_OK;
696 }
697
698 /**
699 * Read basic registers of the the current context: R0 to R15, and CPSR;
700 * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
701 * In normal operation this is called on entry to halting debug state,
702 * possibly after some other operations supporting restore of debug state
703 * or making sure the CPU is fully idle (drain write buffer, etc).
704 */
705 int armv8_dpm_read_current_registers(struct arm_dpm *dpm)
706 {
707 struct arm *arm = dpm->arm;
708 struct armv8_common *armv8 = (struct armv8_common *)arm->arch_info;
709 struct reg_cache *cache;
710 struct reg *r;
711 uint32_t cpsr;
712 int retval;
713
714 retval = dpm->prepare(dpm);
715 if (retval != ERROR_OK)
716 return retval;
717
718 cache = arm->core_cache;
719
720 /* read R0 first (it's used for scratch), then CPSR */
721 r = cache->reg_list + 0;
722 if (!r->valid) {
723 retval = dpmv8_read_reg(dpm, r, 0);
724 if (retval != ERROR_OK)
725 goto fail;
726 }
727 r->dirty = true;
728
729 /* read cpsr to r0 and get it back */
730 retval = dpm->instr_read_data_r0(dpm,
731 armv8_opcode(armv8, READ_REG_DSPSR), &cpsr);
732 if (retval != ERROR_OK)
733 goto fail;
734
735 /* update core mode and state */
736 armv8_set_cpsr(arm, cpsr);
737
738 for (unsigned int i = 1; i < cache->num_regs ; i++) {
739 struct arm_reg *arm_reg;
740
741 r = armv8_reg_current(arm, i);
742 if (r->valid)
743 continue;
744
745 /*
746 * Only read registers that are available from the
747 * current EL (or core mode).
748 */
749 arm_reg = r->arch_info;
750 if (arm_reg->mode != ARM_MODE_ANY &&
751 dpm->last_el != armv8_curel_from_core_mode(arm_reg->mode))
752 continue;
753
754 retval = dpmv8_read_reg(dpm, r, i);
755 if (retval != ERROR_OK)
756 goto fail;
757
758 }
759
760 fail:
761 dpm->finish(dpm);
762 return retval;
763 }
764
765 /* Avoid needless I/O ... leave breakpoints and watchpoints alone
766 * unless they're removed, or need updating because of single-stepping
767 * or running debugger code.
768 */
769 static int dpmv8_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp,
770 struct dpm_bpwp *xp, int *set_p)
771 {
772 int retval = ERROR_OK;
773 bool disable;
774
775 if (!set_p) {
776 if (!xp->dirty)
777 goto done;
778 xp->dirty = false;
779 /* removed or startup; we must disable it */
780 disable = true;
781 } else if (bpwp) {
782 if (!xp->dirty)
783 goto done;
784 /* disabled, but we must set it */
785 xp->dirty = disable = false;
786 *set_p = true;
787 } else {
788 if (!*set_p)
789 goto done;
790 /* set, but we must temporarily disable it */
791 xp->dirty = disable = true;
792 *set_p = false;
793 }
794
795 if (disable)
796 retval = dpm->bpwp_disable(dpm, xp->number);
797 else
798 retval = dpm->bpwp_enable(dpm, xp->number,
799 xp->address, xp->control);
800
801 if (retval != ERROR_OK)
802 LOG_ERROR("%s: can't %s HW %spoint %d",
803 disable ? "disable" : "enable",
804 target_name(dpm->arm->target),
805 (xp->number < 16) ? "break" : "watch",
806 xp->number & 0xf);
807 done:
808 return retval;
809 }
810
811 static int dpmv8_add_breakpoint(struct target *target, struct breakpoint *bp);
812
813 /**
814 * Writes all modified core registers for all processor modes. In normal
815 * operation this is called on exit from halting debug state.
816 *
817 * @param dpm: represents the processor
818 * @param bpwp: true ensures breakpoints and watchpoints are set,
819 * false ensures they are cleared
820 */
821 int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
822 {
823 struct arm *arm = dpm->arm;
824 struct reg_cache *cache = arm->core_cache;
825 int retval;
826
827 retval = dpm->prepare(dpm);
828 if (retval != ERROR_OK)
829 goto done;
830
831 /* If we're managing hardware breakpoints for this core, enable
832 * or disable them as requested.
833 *
834 * REVISIT We don't yet manage them for ANY cores. Eventually
835 * we should be able to assume we handle them; but until then,
836 * cope with the hand-crafted breakpoint code.
837 */
838 if (arm->target->type->add_breakpoint == dpmv8_add_breakpoint) {
839 for (unsigned i = 0; i < dpm->nbp; i++) {
840 struct dpm_bp *dbp = dpm->dbp + i;
841 struct breakpoint *bp = dbp->bp;
842
843 retval = dpmv8_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp,
844 bp ? &bp->set : NULL);
845 if (retval != ERROR_OK)
846 goto done;
847 }
848 }
849
850 /* enable/disable watchpoints */
851 for (unsigned i = 0; i < dpm->nwp; i++) {
852 struct dpm_wp *dwp = dpm->dwp + i;
853 struct watchpoint *wp = dwp->wp;
854
855 retval = dpmv8_maybe_update_bpwp(dpm, bpwp, &dwp->bpwp,
856 wp ? &wp->set : NULL);
857 if (retval != ERROR_OK)
858 goto done;
859 }
860
861 /* NOTE: writes to breakpoint and watchpoint registers might
862 * be queued, and need (efficient/batched) flushing later.
863 */
864
865 /* Restore original core mode and state */
866 retval = armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
867 if (retval != ERROR_OK)
868 goto done;
869
870 /* check everything except our scratch register R0 */
871 for (unsigned i = 1; i < cache->num_regs; i++) {
872 struct arm_reg *r;
873
874 /* skip PC and CPSR */
875 if (i == ARMV8_PC || i == ARMV8_xPSR)
876 continue;
877 /* skip invalid */
878 if (!cache->reg_list[i].valid)
879 continue;
880 /* skip non-dirty */
881 if (!cache->reg_list[i].dirty)
882 continue;
883
884 /* skip all registers not on the current EL */
885 r = cache->reg_list[i].arch_info;
886 if (r->mode != ARM_MODE_ANY &&
887 dpm->last_el != armv8_curel_from_core_mode(r->mode))
888 continue;
889
890 retval = dpmv8_write_reg(dpm, &cache->reg_list[i], i);
891 if (retval != ERROR_OK)
892 break;
893 }
894
895 /* flush CPSR and PC */
896 if (retval == ERROR_OK)
897 retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_xPSR], ARMV8_xPSR);
898 if (retval == ERROR_OK)
899 retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_PC], ARMV8_PC);
900 /* flush R0 -- it's *very* dirty by now */
901 if (retval == ERROR_OK)
902 retval = dpmv8_write_reg(dpm, &cache->reg_list[0], 0);
903 if (retval == ERROR_OK)
904 dpm->instr_cpsr_sync(dpm);
905 done:
906 dpm->finish(dpm);
907 return retval;
908 }
909
910 /*
911 * Standard ARM register accessors ... there are three methods
912 * in "struct arm", to support individual read/write and bulk read
913 * of registers.
914 */
915
916 static int armv8_dpm_read_core_reg(struct target *target, struct reg *r,
917 int regnum, enum arm_mode mode)
918 {
919 struct arm *arm = target_to_arm(target);
920 struct arm_dpm *dpm = target_to_arm(target)->dpm;
921 int retval;
922 int max = arm->core_cache->num_regs;
923
924 if (regnum < 0 || regnum >= max)
925 return ERROR_COMMAND_SYNTAX_ERROR;
926
927 /*
928 * REVISIT what happens if we try to read SPSR in a core mode
929 * which has no such register?
930 */
931 retval = dpm->prepare(dpm);
932 if (retval != ERROR_OK)
933 return retval;
934
935 retval = dpmv8_read_reg(dpm, r, regnum);
936 if (retval != ERROR_OK)
937 goto fail;
938
939 fail:
940 /* (void) */ dpm->finish(dpm);
941 return retval;
942 }
943
944 static int armv8_dpm_write_core_reg(struct target *target, struct reg *r,
945 int regnum, enum arm_mode mode, uint8_t *value)
946 {
947 struct arm *arm = target_to_arm(target);
948 struct arm_dpm *dpm = target_to_arm(target)->dpm;
949 int retval;
950 int max = arm->core_cache->num_regs;
951
952 if (regnum < 0 || regnum > max)
953 return ERROR_COMMAND_SYNTAX_ERROR;
954
955 /* REVISIT what happens if we try to write SPSR in a core mode
956 * which has no such register?
957 */
958
959 retval = dpm->prepare(dpm);
960 if (retval != ERROR_OK)
961 return retval;
962
963 retval = dpmv8_write_reg(dpm, r, regnum);
964
965 /* always clean up, regardless of error */
966 dpm->finish(dpm);
967
968 return retval;
969 }
970
971 static int armv8_dpm_full_context(struct target *target)
972 {
973 struct arm *arm = target_to_arm(target);
974 struct arm_dpm *dpm = arm->dpm;
975 struct reg_cache *cache = arm->core_cache;
976 int retval;
977 bool did_read;
978
979 retval = dpm->prepare(dpm);
980 if (retval != ERROR_OK)
981 goto done;
982
983 do {
984 enum arm_mode mode = ARM_MODE_ANY;
985
986 did_read = false;
987
988 /* We "know" arm_dpm_read_current_registers() was called so
989 * the unmapped registers (R0..R7, PC, AND CPSR) and some
990 * view of R8..R14 are current. We also "know" oddities of
991 * register mapping: special cases for R8..R12 and SPSR.
992 *
993 * Pick some mode with unread registers and read them all.
994 * Repeat until done.
995 */
996 for (unsigned i = 0; i < cache->num_regs; i++) {
997 struct arm_reg *r;
998
999 if (cache->reg_list[i].valid)
1000 continue;
1001 r = cache->reg_list[i].arch_info;
1002
1003 /* may need to pick a mode and set CPSR */
1004 if (!did_read) {
1005 did_read = true;
1006 mode = r->mode;
1007
1008 /* For regular (ARM_MODE_ANY) R8..R12
1009 * in case we've entered debug state
1010 * in FIQ mode we need to patch mode.
1011 */
1012 if (mode != ARM_MODE_ANY)
1013 retval = armv8_dpm_modeswitch(dpm, mode);
1014 else
1015 retval = armv8_dpm_modeswitch(dpm, ARM_MODE_USR);
1016
1017 if (retval != ERROR_OK)
1018 goto done;
1019 }
1020 if (r->mode != mode)
1021 continue;
1022
1023 /* CPSR was read, so "R16" must mean SPSR */
1024 retval = dpmv8_read_reg(dpm,
1025 &cache->reg_list[i],
1026 (r->num == 16) ? 17 : r->num);
1027 if (retval != ERROR_OK)
1028 goto done;
1029 }
1030
1031 } while (did_read);
1032
1033 retval = armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
1034 /* (void) */ dpm->finish(dpm);
1035 done:
1036 return retval;
1037 }
1038
1039
1040 /*----------------------------------------------------------------------*/
1041
1042 /*
1043 * Breakpoint and Watchpoint support.
1044 *
1045 * Hardware {break,watch}points are usually left active, to minimize
1046 * debug entry/exit costs. When they are set or cleared, it's done in
1047 * batches. Also, DPM-conformant hardware can update debug registers
1048 * regardless of whether the CPU is running or halted ... though that
1049 * fact isn't currently leveraged.
1050 */
1051
1052 static int dpmv8_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp,
1053 uint32_t addr, uint32_t length)
1054 {
1055 uint32_t control;
1056
1057 control = (1 << 0) /* enable */
1058 | (3 << 1); /* both user and privileged access */
1059
1060 /* Match 1, 2, or all 4 byte addresses in this word.
1061 *
1062 * FIXME: v7 hardware allows lengths up to 2 GB for BP and WP.
1063 * Support larger length, when addr is suitably aligned. In
1064 * particular, allow watchpoints on 8 byte "double" values.
1065 *
1066 * REVISIT allow watchpoints on unaligned 2-bit values; and on
1067 * v7 hardware, unaligned 4-byte ones too.
1068 */
1069 switch (length) {
1070 case 1:
1071 control |= (1 << (addr & 3)) << 5;
1072 break;
1073 case 2:
1074 /* require 2-byte alignment */
1075 if (!(addr & 1)) {
1076 control |= (3 << (addr & 2)) << 5;
1077 break;
1078 }
1079 /* FALL THROUGH */
1080 case 4:
1081 /* require 4-byte alignment */
1082 if (!(addr & 3)) {
1083 control |= 0xf << 5;
1084 break;
1085 }
1086 /* FALL THROUGH */
1087 default:
1088 LOG_ERROR("unsupported {break,watch}point length/alignment");
1089 return ERROR_COMMAND_SYNTAX_ERROR;
1090 }
1091
1092 /* other shared control bits:
1093 * bits 15:14 == 0 ... both secure and nonsecure states (v6.1+ only)
1094 * bit 20 == 0 ... not linked to a context ID
1095 * bit 28:24 == 0 ... not ignoring N LSBs (v7 only)
1096 */
1097
1098 xp->address = addr & ~3;
1099 xp->control = control;
1100 xp->dirty = true;
1101
1102 LOG_DEBUG("BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d",
1103 xp->address, control, xp->number);
1104
1105 /* hardware is updated in write_dirty_registers() */
1106 return ERROR_OK;
1107 }
1108
1109 static int dpmv8_add_breakpoint(struct target *target, struct breakpoint *bp)
1110 {
1111 struct arm *arm = target_to_arm(target);
1112 struct arm_dpm *dpm = arm->dpm;
1113 int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1114
1115 if (bp->length < 2)
1116 return ERROR_COMMAND_SYNTAX_ERROR;
1117 if (!dpm->bpwp_enable)
1118 return retval;
1119
1120 /* FIXME we need a generic solution for software breakpoints. */
1121 if (bp->type == BKPT_SOFT)
1122 LOG_DEBUG("using HW bkpt, not SW...");
1123
1124 for (unsigned i = 0; i < dpm->nbp; i++) {
1125 if (!dpm->dbp[i].bp) {
1126 retval = dpmv8_bpwp_setup(dpm, &dpm->dbp[i].bpwp,
1127 bp->address, bp->length);
1128 if (retval == ERROR_OK)
1129 dpm->dbp[i].bp = bp;
1130 break;
1131 }
1132 }
1133
1134 return retval;
1135 }
1136
1137 static int dpmv8_remove_breakpoint(struct target *target, struct breakpoint *bp)
1138 {
1139 struct arm *arm = target_to_arm(target);
1140 struct arm_dpm *dpm = arm->dpm;
1141 int retval = ERROR_COMMAND_SYNTAX_ERROR;
1142
1143 for (unsigned i = 0; i < dpm->nbp; i++) {
1144 if (dpm->dbp[i].bp == bp) {
1145 dpm->dbp[i].bp = NULL;
1146 dpm->dbp[i].bpwp.dirty = true;
1147
1148 /* hardware is updated in write_dirty_registers() */
1149 retval = ERROR_OK;
1150 break;
1151 }
1152 }
1153
1154 return retval;
1155 }
1156
1157 static int dpmv8_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t,
1158 struct watchpoint *wp)
1159 {
1160 int retval;
1161 struct dpm_wp *dwp = dpm->dwp + index_t;
1162 uint32_t control;
1163
1164 /* this hardware doesn't support data value matching or masking */
1165 if (wp->value || wp->mask != ~(uint32_t)0) {
1166 LOG_DEBUG("watchpoint values and masking not supported");
1167 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1168 }
1169
1170 retval = dpmv8_bpwp_setup(dpm, &dwp->bpwp, wp->address, wp->length);
1171 if (retval != ERROR_OK)
1172 return retval;
1173
1174 control = dwp->bpwp.control;
1175 switch (wp->rw) {
1176 case WPT_READ:
1177 control |= 1 << 3;
1178 break;
1179 case WPT_WRITE:
1180 control |= 2 << 3;
1181 break;
1182 case WPT_ACCESS:
1183 control |= 3 << 3;
1184 break;
1185 }
1186 dwp->bpwp.control = control;
1187
1188 dpm->dwp[index_t].wp = wp;
1189
1190 return retval;
1191 }
1192
1193 static int dpmv8_add_watchpoint(struct target *target, struct watchpoint *wp)
1194 {
1195 struct arm *arm = target_to_arm(target);
1196 struct arm_dpm *dpm = arm->dpm;
1197 int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1198
1199 if (dpm->bpwp_enable) {
1200 for (unsigned i = 0; i < dpm->nwp; i++) {
1201 if (!dpm->dwp[i].wp) {
1202 retval = dpmv8_watchpoint_setup(dpm, i, wp);
1203 break;
1204 }
1205 }
1206 }
1207
1208 return retval;
1209 }
1210
1211 static int dpmv8_remove_watchpoint(struct target *target, struct watchpoint *wp)
1212 {
1213 struct arm *arm = target_to_arm(target);
1214 struct arm_dpm *dpm = arm->dpm;
1215 int retval = ERROR_COMMAND_SYNTAX_ERROR;
1216
1217 for (unsigned i = 0; i < dpm->nwp; i++) {
1218 if (dpm->dwp[i].wp == wp) {
1219 dpm->dwp[i].wp = NULL;
1220 dpm->dwp[i].bpwp.dirty = true;
1221
1222 /* hardware is updated in write_dirty_registers() */
1223 retval = ERROR_OK;
1224 break;
1225 }
1226 }
1227
1228 return retval;
1229 }
1230
1231 void armv8_dpm_report_wfar(struct arm_dpm *dpm, uint64_t addr)
1232 {
1233 switch (dpm->arm->core_state) {
1234 case ARM_STATE_ARM:
1235 case ARM_STATE_AARCH64:
1236 addr -= 8;
1237 break;
1238 case ARM_STATE_THUMB:
1239 case ARM_STATE_THUMB_EE:
1240 addr -= 4;
1241 break;
1242 case ARM_STATE_JAZELLE:
1243 /* ?? */
1244 break;
1245 default:
1246 LOG_DEBUG("Unknown core_state");
1247 break;
1248 }
1249 dpm->wp_pc = addr;
1250 }
1251
1252 /*
1253 * Handle exceptions taken in debug state. This happens mostly for memory
1254 * accesses that violated a MMU policy. Taking an exception while in debug
1255 * state clobbers certain state registers on the target exception level.
1256 * Just mark those registers dirty so that they get restored on resume.
1257 * This works both for Aarch32 and Aarch64 states.
1258 *
1259 * This function must not perform any actions that trigger another exception
1260 * or a recursion will happen.
1261 */
1262 void armv8_dpm_handle_exception(struct arm_dpm *dpm)
1263 {
1264 struct armv8_common *armv8 = dpm->arm->arch_info;
1265 struct reg_cache *cache = dpm->arm->core_cache;
1266 enum arm_state core_state;
1267 uint64_t dlr;
1268 uint32_t dspsr;
1269 unsigned int el;
1270
1271 static const int clobbered_regs_by_el[3][5] = {
1272 { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL1, ARMV8_ESR_EL1, ARMV8_SPSR_EL1 },
1273 { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL2, ARMV8_ESR_EL2, ARMV8_SPSR_EL2 },
1274 { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL3, ARMV8_ESR_EL3, ARMV8_SPSR_EL3 },
1275 };
1276
1277 el = (dpm->dscr >> 8) & 3;
1278
1279 /* safety check, must not happen since EL0 cannot be a target for an exception */
1280 if (el < SYSTEM_CUREL_EL1 || el > SYSTEM_CUREL_EL3) {
1281 LOG_ERROR("%s: EL %i is invalid, DSCR corrupted?", __func__, el);
1282 return;
1283 }
1284
1285 /* Clear sticky error */
1286 mem_ap_write_u32(armv8->debug_ap,
1287 armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
1288
1289 armv8->read_reg_u64(armv8, ARMV8_xPSR, &dlr);
1290 dspsr = dlr;
1291 armv8->read_reg_u64(armv8, ARMV8_PC, &dlr);
1292
1293 LOG_DEBUG("Exception taken to EL %i, DLR=0x%016"PRIx64" DSPSR=0x%08"PRIx32,
1294 el, dlr, dspsr);
1295
1296 /* mark all clobbered registers as dirty */
1297 for (int i = 0; i < 5; i++)
1298 cache->reg_list[clobbered_regs_by_el[el-1][i]].dirty = true;
1299
1300 /*
1301 * re-evaluate the core state, we might be in Aarch64 state now
1302 * we rely on dpm->dscr being up-to-date
1303 */
1304 core_state = armv8_dpm_get_core_state(dpm);
1305 armv8_select_opcodes(armv8, core_state == ARM_STATE_AARCH64);
1306 armv8_select_reg_access(armv8, core_state == ARM_STATE_AARCH64);
1307 }
1308
1309 /*----------------------------------------------------------------------*/
1310
1311 /*
1312 * Other debug and support utilities
1313 */
1314
1315 void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
1316 {
1317 struct target *target = dpm->arm->target;
1318
1319 dpm->dscr = dscr;
1320 dpm->last_el = (dscr >> 8) & 3;
1321
1322 /* Examine debug reason */
1323 switch (DSCR_ENTRY(dscr)) {
1324 /* FALL THROUGH -- assume a v6 core in abort mode */
1325 case DSCRV8_ENTRY_EXT_DEBUG: /* EDBGRQ */
1326 target->debug_reason = DBG_REASON_DBGRQ;
1327 break;
1328 case DSCRV8_ENTRY_HALT_STEP_EXECLU: /* HALT step */
1329 case DSCRV8_ENTRY_HALT_STEP_NORMAL: /* Halt step*/
1330 case DSCRV8_ENTRY_HALT_STEP:
1331 target->debug_reason = DBG_REASON_SINGLESTEP;
1332 break;
1333 case DSCRV8_ENTRY_HLT: /* HLT instruction (software breakpoint) */
1334 case DSCRV8_ENTRY_BKPT: /* SW BKPT (?) */
1335 case DSCRV8_ENTRY_RESET_CATCH: /* Reset catch */
1336 case DSCRV8_ENTRY_OS_UNLOCK: /*OS unlock catch*/
1337 case DSCRV8_ENTRY_EXCEPTION_CATCH: /*exception catch*/
1338 case DSCRV8_ENTRY_SW_ACCESS_DBG: /*SW access dbg register*/
1339 target->debug_reason = DBG_REASON_BREAKPOINT;
1340 break;
1341 case DSCRV8_ENTRY_WATCHPOINT: /* asynch watchpoint */
1342 target->debug_reason = DBG_REASON_WATCHPOINT;
1343 break;
1344 default:
1345 target->debug_reason = DBG_REASON_UNDEFINED;
1346 break;
1347 }
1348
1349 }
1350
1351 /*----------------------------------------------------------------------*/
1352
1353 /*
1354 * Setup and management support.
1355 */
1356
1357 /**
1358 * Hooks up this DPM to its associated target; call only once.
1359 * Initially this only covers the register cache.
1360 *
1361 * Oh, and watchpoints. Yeah.
1362 */
1363 int armv8_dpm_setup(struct arm_dpm *dpm)
1364 {
1365 struct arm *arm = dpm->arm;
1366 struct target *target = arm->target;
1367 struct reg_cache *cache;
1368 arm->dpm = dpm;
1369
1370 /* register access setup */
1371 arm->full_context = armv8_dpm_full_context;
1372 arm->read_core_reg = armv8_dpm_read_core_reg;
1373 arm->write_core_reg = armv8_dpm_write_core_reg;
1374
1375 if (arm->core_cache == NULL) {
1376 cache = armv8_build_reg_cache(target);
1377 if (!cache)
1378 return ERROR_FAIL;
1379 }
1380
1381 /* coprocessor access setup */
1382 arm->mrc = dpmv8_mrc;
1383 arm->mcr = dpmv8_mcr;
1384
1385 dpm->prepare = dpmv8_dpm_prepare;
1386 dpm->finish = dpmv8_dpm_finish;
1387
1388 dpm->instr_execute = dpmv8_instr_execute;
1389 dpm->instr_write_data_dcc = dpmv8_instr_write_data_dcc;
1390 dpm->instr_write_data_dcc_64 = dpmv8_instr_write_data_dcc_64;
1391 dpm->instr_write_data_r0 = dpmv8_instr_write_data_r0;
1392 dpm->instr_write_data_r0_64 = dpmv8_instr_write_data_r0_64;
1393 dpm->instr_cpsr_sync = dpmv8_instr_cpsr_sync;
1394
1395 dpm->instr_read_data_dcc = dpmv8_instr_read_data_dcc;
1396 dpm->instr_read_data_dcc_64 = dpmv8_instr_read_data_dcc_64;
1397 dpm->instr_read_data_r0 = dpmv8_instr_read_data_r0;
1398 dpm->instr_read_data_r0_64 = dpmv8_instr_read_data_r0_64;
1399
1400 dpm->arm_reg_current = armv8_reg_current;
1401
1402 /* dpm->bpwp_enable = dpmv8_bpwp_enable; */
1403 dpm->bpwp_disable = dpmv8_bpwp_disable;
1404
1405 /* breakpoint setup -- optional until it works everywhere */
1406 if (!target->type->add_breakpoint) {
1407 target->type->add_breakpoint = dpmv8_add_breakpoint;
1408 target->type->remove_breakpoint = dpmv8_remove_breakpoint;
1409 }
1410
1411 /* watchpoint setup */
1412 target->type->add_watchpoint = dpmv8_add_watchpoint;
1413 target->type->remove_watchpoint = dpmv8_remove_watchpoint;
1414
1415 /* FIXME add vector catch support */
1416
1417 dpm->nbp = 1 + ((dpm->didr >> 12) & 0xf);
1418 dpm->dbp = calloc(dpm->nbp, sizeof *dpm->dbp);
1419
1420 dpm->nwp = 1 + ((dpm->didr >> 20) & 0xf);
1421 dpm->dwp = calloc(dpm->nwp, sizeof *dpm->dwp);
1422
1423 if (!dpm->dbp || !dpm->dwp) {
1424 free(dpm->dbp);
1425 free(dpm->dwp);
1426 return ERROR_FAIL;
1427 }
1428
1429 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1430 target_name(target), dpm->nbp, dpm->nwp);
1431
1432 /* REVISIT ... and some of those breakpoints could match
1433 * execution context IDs...
1434 */
1435
1436 return ERROR_OK;
1437 }
1438
1439 /**
1440 * Reinitializes DPM state at the beginning of a new debug session
1441 * or after a reset which may have affected the debug module.
1442 */
1443 int armv8_dpm_initialize(struct arm_dpm *dpm)
1444 {
1445 /* Disable all breakpoints and watchpoints at startup. */
1446 if (dpm->bpwp_disable) {
1447 unsigned i;
1448
1449 for (i = 0; i < dpm->nbp; i++) {
1450 dpm->dbp[i].bpwp.number = i;
1451 (void) dpm->bpwp_disable(dpm, i);
1452 }
1453 for (i = 0; i < dpm->nwp; i++) {
1454 dpm->dwp[i].bpwp.number = 16 + i;
1455 (void) dpm->bpwp_disable(dpm, 16 + i);
1456 }
1457 } else
1458 LOG_WARNING("%s: can't disable breakpoints and watchpoints",
1459 target_name(dpm->arm->target));
1460
1461 return ERROR_OK;
1462 }
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