1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
25 #ifndef OPENOCD_TARGET_ARMV7M_H
26 #define OPENOCD_TARGET_ARMV7M_H
28 #include "arm_adi_v5.h"
30 #include "armv7m_trace.h"
32 extern const int armv7m_psp_reg_map
[];
33 extern const int armv7m_msp_reg_map
[];
35 const char *armv7m_exception_string(int number
);
37 /* Cortex-M DCRSR.REGSEL selectors */
57 ARMV7M_REGSEL_PC
= 15,
59 ARMV7M_REGSEL_xPSR
= 16,
63 ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL
= 0x14,
64 ARMV7M_REGSEL_FPSCR
= 0x21,
66 /* 32bit Floating-point registers */
67 ARMV7M_REGSEL_S0
= 0x40,
101 /* offsets into armv7m core register cache */
103 /* for convenience, the first set of indices match
104 * the Cortex-M DCRSR.REGSEL selectors
106 ARMV7M_R0
= ARMV7M_REGSEL_R0
,
107 ARMV7M_R1
= ARMV7M_REGSEL_R1
,
108 ARMV7M_R2
= ARMV7M_REGSEL_R2
,
109 ARMV7M_R3
= ARMV7M_REGSEL_R3
,
111 ARMV7M_R4
= ARMV7M_REGSEL_R4
,
112 ARMV7M_R5
= ARMV7M_REGSEL_R5
,
113 ARMV7M_R6
= ARMV7M_REGSEL_R6
,
114 ARMV7M_R7
= ARMV7M_REGSEL_R7
,
116 ARMV7M_R8
= ARMV7M_REGSEL_R8
,
117 ARMV7M_R9
= ARMV7M_REGSEL_R9
,
118 ARMV7M_R10
= ARMV7M_REGSEL_R10
,
119 ARMV7M_R11
= ARMV7M_REGSEL_R11
,
121 ARMV7M_R12
= ARMV7M_REGSEL_R12
,
122 ARMV7M_R13
= ARMV7M_REGSEL_R13
,
123 ARMV7M_R14
= ARMV7M_REGSEL_R14
,
124 ARMV7M_PC
= ARMV7M_REGSEL_PC
,
126 ARMV7M_xPSR
= ARMV7M_REGSEL_xPSR
,
127 ARMV7M_MSP
= ARMV7M_REGSEL_MSP
,
128 ARMV7M_PSP
= ARMV7M_REGSEL_PSP
,
130 /* following indices are arbitrary, do not match DCRSR.REGSEL selectors */
132 /* working register for packing/unpacking special regs, hidden from gdb */
133 ARMV7M_PMSK_BPRI_FLTMSK_CTRL
,
135 /* WARNING: If you use armv7m_write_core_reg() on one of 4 following
136 * special registers, the new data go to ARMV7M_PMSK_BPRI_FLTMSK_CTRL
137 * cache only and are not flushed to CPU HW register.
138 * To trigger write to CPU HW register, add
139 * armv7m_write_core_reg(,,ARMV7M_PMSK_BPRI_FLTMSK_CTRL,);
146 /* 64bit Floating-point registers */
164 /* Floating-point status register */
177 #define ARMV7M_NUM_CORE_REGS (ARMV7M_xPSR + 1)
178 #define ARMV7M_NUM_CORE_REGS_NOFP (ARMV7M_CONTROL + 1)
180 #define ARMV7M_COMMON_MAGIC 0x2A452A45
182 struct armv7m_common
{
186 int exception_number
;
188 /* AP this processor is connected to in the DAP */
189 struct adiv5_ap
*debug_ap
;
194 /* stlink is a high level adapter, does not support all functions */
197 struct armv7m_trace_config trace_config
;
199 /* Direct processor core register read and writes */
200 int (*load_core_reg_u32
)(struct target
*target
, uint32_t regsel
, uint32_t *value
);
201 int (*store_core_reg_u32
)(struct target
*target
, uint32_t regsel
, uint32_t value
);
203 int (*examine_debug_reason
)(struct target
*target
);
204 int (*post_debug_entry
)(struct target
*target
);
206 void (*pre_restore_context
)(struct target
*target
);
209 static inline struct armv7m_common
*
210 target_to_armv7m(struct target
*target
)
212 return container_of(target
->arch_info
, struct armv7m_common
, arm
);
215 static inline bool is_armv7m(const struct armv7m_common
*armv7m
)
217 return armv7m
->common_magic
== ARMV7M_COMMON_MAGIC
;
220 struct armv7m_algorithm
{
223 enum arm_mode core_mode
;
225 uint32_t context
[ARMV7M_LAST_REG
]; /* ARMV7M_NUM_REGS */
228 struct reg_cache
*armv7m_build_reg_cache(struct target
*target
);
229 void armv7m_free_reg_cache(struct target
*target
);
231 enum armv7m_mode
armv7m_number_to_mode(int number
);
232 int armv7m_mode_to_number(enum armv7m_mode mode
);
234 int armv7m_arch_state(struct target
*target
);
235 int armv7m_get_gdb_reg_list(struct target
*target
,
236 struct reg
**reg_list
[], int *reg_list_size
,
237 enum target_register_class reg_class
);
239 int armv7m_init_arch_info(struct target
*target
, struct armv7m_common
*armv7m
);
241 int armv7m_run_algorithm(struct target
*target
,
242 int num_mem_params
, struct mem_param
*mem_params
,
243 int num_reg_params
, struct reg_param
*reg_params
,
244 target_addr_t entry_point
, target_addr_t exit_point
,
245 int timeout_ms
, void *arch_info
);
247 int armv7m_start_algorithm(struct target
*target
,
248 int num_mem_params
, struct mem_param
*mem_params
,
249 int num_reg_params
, struct reg_param
*reg_params
,
250 target_addr_t entry_point
, target_addr_t exit_point
,
253 int armv7m_wait_algorithm(struct target
*target
,
254 int num_mem_params
, struct mem_param
*mem_params
,
255 int num_reg_params
, struct reg_param
*reg_params
,
256 target_addr_t exit_point
, int timeout_ms
,
259 int armv7m_invalidate_core_regs(struct target
*target
);
261 int armv7m_restore_context(struct target
*target
);
263 int armv7m_checksum_memory(struct target
*target
,
264 target_addr_t address
, uint32_t count
, uint32_t *checksum
);
265 int armv7m_blank_check_memory(struct target
*target
,
266 struct target_memory_check_block
*blocks
, int num_blocks
, uint8_t erased_value
);
268 int armv7m_maybe_skip_bkpt_inst(struct target
*target
, bool *inst_found
);
270 extern const struct command_registration armv7m_command_handlers
[];
272 #endif /* OPENOCD_TARGET_ARMV7M_H */
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