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armv7a: fix handling of inner caches
[openocd.git] / src / target / armv7a_cache_l2x.c
1 /***************************************************************************
2 * Copyright (C) 2015 by Oleksij Rempel *
3 * linux@rempel-privat.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 ***************************************************************************/
15
16 #ifdef HAVE_CONFIG_H
17 #include "config.h"
18 #endif
19
20 #include "jtag/interface.h"
21 #include "arm.h"
22 #include "armv7a.h"
23 #include "armv7a_cache.h"
24 #include <helper/time_support.h>
25 #include "target.h"
26 #include "target_type.h"
27
28 static int arm7a_l2x_sanity_check(struct target *target)
29 {
30 struct armv7a_common *armv7a = target_to_armv7a(target);
31 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
32 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
33
34 if (target->state != TARGET_HALTED) {
35 LOG_ERROR("%s: target not halted", __func__);
36 return ERROR_TARGET_NOT_HALTED;
37 }
38
39 if (!l2x_cache || !l2x_cache->base) {
40 LOG_DEBUG("l2x is not configured!");
41 return ERROR_FAIL;
42 }
43
44 return ERROR_OK;
45 }
46 /*
47 * clean and invalidate complete l2x cache
48 */
49 int arm7a_l2x_flush_all_data(struct target *target)
50 {
51 struct armv7a_common *armv7a = target_to_armv7a(target);
52 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
53 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
54 uint32_t l2_way_val;
55 int retval;
56
57 retval = arm7a_l2x_sanity_check(target);
58 if (retval)
59 return retval;
60
61 l2_way_val = (1 << l2x_cache->way) - 1;
62
63 return target_write_phys_memory(target,
64 l2x_cache->base + L2X0_CLEAN_INV_WAY,
65 4, 1, (uint8_t *)&l2_way_val);
66 }
67
68 int armv7a_l2x_cache_flush_virt(struct target *target, uint32_t virt,
69 uint32_t size)
70 {
71 struct armv7a_common *armv7a = target_to_armv7a(target);
72 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
73 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
74 /* FIXME: different controllers have different linelen? */
75 uint32_t i, linelen = 32;
76 int retval;
77
78 retval = arm7a_l2x_sanity_check(target);
79 if (retval)
80 return retval;
81
82 for (i = 0; i < size; i += linelen) {
83 uint32_t pa, offs = virt + i;
84
85 /* FIXME: use less verbose virt2phys? */
86 retval = target->type->virt2phys(target, offs, &pa);
87 if (retval != ERROR_OK)
88 goto done;
89
90 retval = target_write_phys_memory(target,
91 l2x_cache->base + L2X0_CLEAN_INV_LINE_PA,
92 4, 1, (uint8_t *)&pa);
93 if (retval != ERROR_OK)
94 goto done;
95 }
96 return retval;
97
98 done:
99 LOG_ERROR("d-cache invalidate failed");
100
101 return retval;
102 }
103
104 static int armv7a_l2x_cache_inval_virt(struct target *target, uint32_t virt,
105 uint32_t size)
106 {
107 struct armv7a_common *armv7a = target_to_armv7a(target);
108 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
109 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
110 /* FIXME: different controllers have different linelen */
111 uint32_t i, linelen = 32;
112 int retval;
113
114 retval = arm7a_l2x_sanity_check(target);
115 if (retval)
116 return retval;
117
118 for (i = 0; i < size; i += linelen) {
119 uint32_t pa, offs = virt + i;
120
121 /* FIXME: use less verbose virt2phys? */
122 retval = target->type->virt2phys(target, offs, &pa);
123 if (retval != ERROR_OK)
124 goto done;
125
126 retval = target_write_phys_memory(target,
127 l2x_cache->base + L2X0_INV_LINE_PA,
128 4, 1, (uint8_t *)&pa);
129 if (retval != ERROR_OK)
130 goto done;
131 }
132 return retval;
133
134 done:
135 LOG_ERROR("d-cache invalidate failed");
136
137 return retval;
138 }
139
140 static int armv7a_l2x_cache_clean_virt(struct target *target, uint32_t virt,
141 unsigned int size)
142 {
143 struct armv7a_common *armv7a = target_to_armv7a(target);
144 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
145 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
146 /* FIXME: different controllers have different linelen */
147 uint32_t i, linelen = 32;
148 int retval;
149
150 retval = arm7a_l2x_sanity_check(target);
151 if (retval)
152 return retval;
153
154 for (i = 0; i < size; i += linelen) {
155 uint32_t pa, offs = virt + i;
156
157 /* FIXME: use less verbose virt2phys? */
158 retval = target->type->virt2phys(target, offs, &pa);
159 if (retval != ERROR_OK)
160 goto done;
161
162 retval = target_write_phys_memory(target,
163 l2x_cache->base + L2X0_CLEAN_LINE_PA,
164 4, 1, (uint8_t *)&pa);
165 if (retval != ERROR_OK)
166 goto done;
167 }
168 return retval;
169
170 done:
171 LOG_ERROR("d-cache invalidate failed");
172
173 return retval;
174 }
175
176 static int arm7a_handle_l2x_cache_info_command(struct command_context *cmd_ctx,
177 struct armv7a_cache_common *armv7a_cache)
178 {
179 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
180 (armv7a_cache->outer_cache);
181
182 if (armv7a_cache->info == -1) {
183 command_print(cmd_ctx, "cache not yet identified");
184 return ERROR_OK;
185 }
186
187 command_print(cmd_ctx,
188 "L2 unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
189 l2x_cache->base, l2x_cache->way);
190
191 return ERROR_OK;
192 }
193
194 static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t way)
195 {
196 struct armv7a_l2x_cache *l2x_cache;
197 struct target_list *head = target->head;
198 struct target *curr;
199
200 struct armv7a_common *armv7a = target_to_armv7a(target);
201 if (armv7a->armv7a_mmu.armv7a_cache.outer_cache) {
202 LOG_ERROR("L2 cache was already initialised\n");
203 return ERROR_FAIL;
204 }
205
206 l2x_cache = calloc(1, sizeof(struct armv7a_l2x_cache));
207 l2x_cache->base = base;
208 l2x_cache->way = way;
209 armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache;
210
211 /* initialize all targets in this cluster (smp target)
212 * l2 cache must be configured after smp declaration */
213 while (head != (struct target_list *)NULL) {
214 curr = head->target;
215 if (curr != target) {
216 armv7a = target_to_armv7a(curr);
217 if (armv7a->armv7a_mmu.armv7a_cache.outer_cache) {
218 LOG_ERROR("smp target : cache l2 already initialized\n");
219 return ERROR_FAIL;
220 }
221 armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache;
222 }
223 head = head->next;
224 }
225 return ERROR_OK;
226 }
227
228 COMMAND_HANDLER(arm7a_l2x_cache_info_command)
229 {
230 struct target *target = get_current_target(CMD_CTX);
231 struct armv7a_common *armv7a = target_to_armv7a(target);
232 int retval;
233
234 retval = arm7a_l2x_sanity_check(target);
235 if (retval)
236 return retval;
237
238 return arm7a_handle_l2x_cache_info_command(CMD_CTX,
239 &armv7a->armv7a_mmu.armv7a_cache);
240 }
241
242 COMMAND_HANDLER(arm7a_l2x_cache_flush_all_command)
243 {
244 struct target *target = get_current_target(CMD_CTX);
245
246 return arm7a_l2x_flush_all_data(target);
247 }
248
249 COMMAND_HANDLER(arm7a_l2x_cache_flush_virt_cmd)
250 {
251 struct target *target = get_current_target(CMD_CTX);
252 uint32_t virt, size;
253
254 if (CMD_ARGC == 0 || CMD_ARGC > 2)
255 return ERROR_COMMAND_SYNTAX_ERROR;
256
257 if (CMD_ARGC == 2)
258 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
259 else
260 size = 1;
261
262 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], virt);
263
264 return armv7a_l2x_cache_flush_virt(target, virt, size);
265 }
266
267 COMMAND_HANDLER(arm7a_l2x_cache_inval_virt_cmd)
268 {
269 struct target *target = get_current_target(CMD_CTX);
270 uint32_t virt, size;
271
272 if (CMD_ARGC == 0 || CMD_ARGC > 2)
273 return ERROR_COMMAND_SYNTAX_ERROR;
274
275 if (CMD_ARGC == 2)
276 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
277 else
278 size = 1;
279
280 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], virt);
281
282 return armv7a_l2x_cache_inval_virt(target, virt, size);
283 }
284
285 COMMAND_HANDLER(arm7a_l2x_cache_clean_virt_cmd)
286 {
287 struct target *target = get_current_target(CMD_CTX);
288 uint32_t virt, size;
289
290 if (CMD_ARGC == 0 || CMD_ARGC > 2)
291 return ERROR_COMMAND_SYNTAX_ERROR;
292
293 if (CMD_ARGC == 2)
294 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
295 else
296 size = 1;
297
298 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], virt);
299
300 return armv7a_l2x_cache_clean_virt(target, virt, size);
301 }
302
303 /* FIXME: should we configure way size? or controller type? */
304 COMMAND_HANDLER(armv7a_l2x_cache_conf_cmd)
305 {
306 struct target *target = get_current_target(CMD_CTX);
307 uint32_t base, way;
308
309 if (CMD_ARGC != 2)
310 return ERROR_COMMAND_SYNTAX_ERROR;
311
312 /* command_print(CMD_CTX, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */
313 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], base);
314 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], way);
315
316 /* AP address is in bits 31:24 of DP_SELECT */
317 return armv7a_l2x_cache_init(target, base, way);
318 }
319
320 static const struct command_registration arm7a_l2x_cache_commands[] = {
321 {
322 .name = "conf",
323 .handler = armv7a_l2x_cache_conf_cmd,
324 .mode = COMMAND_ANY,
325 .help = "configure l2x cache ",
326 .usage = "<base_addr> <number_of_way>",
327 },
328 {
329 .name = "info",
330 .handler = arm7a_l2x_cache_info_command,
331 .mode = COMMAND_ANY,
332 .help = "print cache realted information",
333 .usage = "",
334 },
335 {
336 .name = "flush_all",
337 .handler = arm7a_l2x_cache_flush_all_command,
338 .mode = COMMAND_ANY,
339 .help = "flush complete l2x cache",
340 .usage = "",
341 },
342 {
343 .name = "flush",
344 .handler = arm7a_l2x_cache_flush_virt_cmd,
345 .mode = COMMAND_ANY,
346 .help = "flush (clean and invalidate) l2x cache by virtual address offset and range size",
347 .usage = "<virt_addr> [size]",
348 },
349 {
350 .name = "inval",
351 .handler = arm7a_l2x_cache_inval_virt_cmd,
352 .mode = COMMAND_ANY,
353 .help = "invalidate l2x cache by virtual address offset and range size",
354 .usage = "<virt_addr> [size]",
355 },
356 {
357 .name = "clean",
358 .handler = arm7a_l2x_cache_clean_virt_cmd,
359 .mode = COMMAND_ANY,
360 .help = "clean l2x cache by virtual address address offset and range size",
361 .usage = "<virt_addr> [size]",
362 },
363 COMMAND_REGISTRATION_DONE
364 };
365
366 const struct command_registration arm7a_l2x_cache_command_handler[] = {
367 {
368 .name = "l2x",
369 .mode = COMMAND_ANY,
370 .help = "l2x cache command group",
371 .usage = "",
372 .chain = arm7a_l2x_cache_commands,
373 },
374 COMMAND_REGISTRATION_DONE
375 };
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