e181f268da98562503931948cc4105f1a79763d0
[openocd.git] / src / target / armv7a_cache_l2x.c
1 /***************************************************************************
2 * Copyright (C) 2015 by Oleksij Rempel *
3 * linux@rempel-privat.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18
19 #ifdef HAVE_CONFIG_H
20 #include "config.h"
21 #endif
22
23 #include "jtag/interface.h"
24 #include "arm.h"
25 #include "armv7a.h"
26 #include "armv7a_cache.h"
27 #include <helper/time_support.h>
28 #include "target.h"
29 #include "target_type.h"
30
31 static int arm7a_l2x_sanity_check(struct target *target)
32 {
33 struct armv7a_common *armv7a = target_to_armv7a(target);
34 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
35 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
36
37 if (target->state != TARGET_HALTED) {
38 LOG_ERROR("%s: target not halted", __func__);
39 return ERROR_TARGET_NOT_HALTED;
40 }
41
42 if (!l2x_cache || !l2x_cache->base) {
43 LOG_DEBUG("l2x is not configured!");
44 return ERROR_FAIL;
45 }
46
47 return ERROR_OK;
48 }
49 /*
50 * clean and invalidate complete l2x cache
51 */
52 int arm7a_l2x_flush_all_data(struct target *target)
53 {
54 struct armv7a_common *armv7a = target_to_armv7a(target);
55 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
56 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
57 uint32_t l2_way_val;
58 int retval;
59
60 retval = arm7a_l2x_sanity_check(target);
61 if (retval)
62 return retval;
63
64 l2_way_val = (1 << l2x_cache->way) - 1;
65
66 return target_write_phys_u32(target,
67 l2x_cache->base + L2X0_CLEAN_INV_WAY,
68 l2_way_val);
69 }
70
71 int armv7a_l2x_cache_flush_virt(struct target *target, target_addr_t virt,
72 uint32_t size)
73 {
74 struct armv7a_common *armv7a = target_to_armv7a(target);
75 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
76 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
77 /* FIXME: different controllers have different linelen? */
78 uint32_t i, linelen = 32;
79 int retval;
80
81 retval = arm7a_l2x_sanity_check(target);
82 if (retval)
83 return retval;
84
85 for (i = 0; i < size; i += linelen) {
86 target_addr_t pa, offs = virt + i;
87
88 /* FIXME: use less verbose virt2phys? */
89 retval = target->type->virt2phys(target, offs, &pa);
90 if (retval != ERROR_OK)
91 goto done;
92
93 retval = target_write_phys_u32(target,
94 l2x_cache->base + L2X0_CLEAN_INV_LINE_PA, pa);
95 if (retval != ERROR_OK)
96 goto done;
97 }
98 return retval;
99
100 done:
101 LOG_ERROR("d-cache invalidate failed");
102
103 return retval;
104 }
105
106 static int armv7a_l2x_cache_inval_virt(struct target *target, target_addr_t virt,
107 uint32_t size)
108 {
109 struct armv7a_common *armv7a = target_to_armv7a(target);
110 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
111 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
112 /* FIXME: different controllers have different linelen */
113 uint32_t i, linelen = 32;
114 int retval;
115
116 retval = arm7a_l2x_sanity_check(target);
117 if (retval)
118 return retval;
119
120 for (i = 0; i < size; i += linelen) {
121 target_addr_t pa, offs = virt + i;
122
123 /* FIXME: use less verbose virt2phys? */
124 retval = target->type->virt2phys(target, offs, &pa);
125 if (retval != ERROR_OK)
126 goto done;
127
128 retval = target_write_phys_u32(target,
129 l2x_cache->base + L2X0_INV_LINE_PA, pa);
130 if (retval != ERROR_OK)
131 goto done;
132 }
133 return retval;
134
135 done:
136 LOG_ERROR("d-cache invalidate failed");
137
138 return retval;
139 }
140
141 static int armv7a_l2x_cache_clean_virt(struct target *target, target_addr_t virt,
142 unsigned int size)
143 {
144 struct armv7a_common *armv7a = target_to_armv7a(target);
145 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
146 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
147 /* FIXME: different controllers have different linelen */
148 uint32_t i, linelen = 32;
149 int retval;
150
151 retval = arm7a_l2x_sanity_check(target);
152 if (retval)
153 return retval;
154
155 for (i = 0; i < size; i += linelen) {
156 target_addr_t pa, offs = virt + i;
157
158 /* FIXME: use less verbose virt2phys? */
159 retval = target->type->virt2phys(target, offs, &pa);
160 if (retval != ERROR_OK)
161 goto done;
162
163 retval = target_write_phys_u32(target,
164 l2x_cache->base + L2X0_CLEAN_LINE_PA, pa);
165 if (retval != ERROR_OK)
166 goto done;
167 }
168 return retval;
169
170 done:
171 LOG_ERROR("d-cache invalidate failed");
172
173 return retval;
174 }
175
176 static int arm7a_handle_l2x_cache_info_command(struct command_context *cmd_ctx,
177 struct armv7a_cache_common *armv7a_cache)
178 {
179 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
180 (armv7a_cache->outer_cache);
181
182 if (armv7a_cache->info == -1) {
183 command_print(cmd_ctx, "cache not yet identified");
184 return ERROR_OK;
185 }
186
187 command_print(cmd_ctx,
188 "L2 unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
189 l2x_cache->base, l2x_cache->way);
190
191 return ERROR_OK;
192 }
193
194 static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t way)
195 {
196 struct armv7a_l2x_cache *l2x_cache;
197 struct target_list *head = target->head;
198 struct target *curr;
199
200 struct armv7a_common *armv7a = target_to_armv7a(target);
201 if (armv7a->armv7a_mmu.armv7a_cache.outer_cache) {
202 LOG_ERROR("L2 cache was already initialised\n");
203 return ERROR_FAIL;
204 }
205
206 l2x_cache = calloc(1, sizeof(struct armv7a_l2x_cache));
207 l2x_cache->base = base;
208 l2x_cache->way = way;
209 armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache;
210
211 /* initialize all targets in this cluster (smp target)
212 * l2 cache must be configured after smp declaration */
213 while (head != (struct target_list *)NULL) {
214 curr = head->target;
215 if (curr != target) {
216 armv7a = target_to_armv7a(curr);
217 if (armv7a->armv7a_mmu.armv7a_cache.outer_cache) {
218 LOG_ERROR("smp target : cache l2 already initialized\n");
219 return ERROR_FAIL;
220 }
221 armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache;
222 }
223 head = head->next;
224 }
225 return ERROR_OK;
226 }
227
228 COMMAND_HANDLER(arm7a_l2x_cache_info_command)
229 {
230 struct target *target = get_current_target(CMD_CTX);
231 struct armv7a_common *armv7a = target_to_armv7a(target);
232 int retval;
233
234 retval = arm7a_l2x_sanity_check(target);
235 if (retval)
236 return retval;
237
238 return arm7a_handle_l2x_cache_info_command(CMD_CTX,
239 &armv7a->armv7a_mmu.armv7a_cache);
240 }
241
242 COMMAND_HANDLER(arm7a_l2x_cache_flush_all_command)
243 {
244 struct target *target = get_current_target(CMD_CTX);
245
246 return arm7a_l2x_flush_all_data(target);
247 }
248
249 COMMAND_HANDLER(arm7a_l2x_cache_flush_virt_cmd)
250 {
251 struct target *target = get_current_target(CMD_CTX);
252 target_addr_t virt;
253 uint32_t size;
254
255 if (CMD_ARGC == 0 || CMD_ARGC > 2)
256 return ERROR_COMMAND_SYNTAX_ERROR;
257
258 if (CMD_ARGC == 2)
259 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
260 else
261 size = 1;
262
263 COMMAND_PARSE_ADDRESS(CMD_ARGV[0], virt);
264
265 return armv7a_l2x_cache_flush_virt(target, virt, size);
266 }
267
268 COMMAND_HANDLER(arm7a_l2x_cache_inval_virt_cmd)
269 {
270 struct target *target = get_current_target(CMD_CTX);
271 target_addr_t virt;
272 uint32_t size;
273
274 if (CMD_ARGC == 0 || CMD_ARGC > 2)
275 return ERROR_COMMAND_SYNTAX_ERROR;
276
277 if (CMD_ARGC == 2)
278 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
279 else
280 size = 1;
281
282 COMMAND_PARSE_ADDRESS(CMD_ARGV[0], virt);
283
284 return armv7a_l2x_cache_inval_virt(target, virt, size);
285 }
286
287 COMMAND_HANDLER(arm7a_l2x_cache_clean_virt_cmd)
288 {
289 struct target *target = get_current_target(CMD_CTX);
290 target_addr_t virt;
291 uint32_t size;
292
293 if (CMD_ARGC == 0 || CMD_ARGC > 2)
294 return ERROR_COMMAND_SYNTAX_ERROR;
295
296 if (CMD_ARGC == 2)
297 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
298 else
299 size = 1;
300
301 COMMAND_PARSE_ADDRESS(CMD_ARGV[0], virt);
302
303 return armv7a_l2x_cache_clean_virt(target, virt, size);
304 }
305
306 /* FIXME: should we configure way size? or controller type? */
307 COMMAND_HANDLER(armv7a_l2x_cache_conf_cmd)
308 {
309 struct target *target = get_current_target(CMD_CTX);
310 uint32_t base, way;
311
312 if (CMD_ARGC != 2)
313 return ERROR_COMMAND_SYNTAX_ERROR;
314
315 /* command_print(CMD_CTX, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */
316 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], base);
317 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], way);
318
319 /* AP address is in bits 31:24 of DP_SELECT */
320 return armv7a_l2x_cache_init(target, base, way);
321 }
322
323 static const struct command_registration arm7a_l2x_cache_commands[] = {
324 {
325 .name = "conf",
326 .handler = armv7a_l2x_cache_conf_cmd,
327 .mode = COMMAND_ANY,
328 .help = "configure l2x cache ",
329 .usage = "<base_addr> <number_of_way>",
330 },
331 {
332 .name = "info",
333 .handler = arm7a_l2x_cache_info_command,
334 .mode = COMMAND_ANY,
335 .help = "print cache realted information",
336 .usage = "",
337 },
338 {
339 .name = "flush_all",
340 .handler = arm7a_l2x_cache_flush_all_command,
341 .mode = COMMAND_ANY,
342 .help = "flush complete l2x cache",
343 .usage = "",
344 },
345 {
346 .name = "flush",
347 .handler = arm7a_l2x_cache_flush_virt_cmd,
348 .mode = COMMAND_ANY,
349 .help = "flush (clean and invalidate) l2x cache by virtual address offset and range size",
350 .usage = "<virt_addr> [size]",
351 },
352 {
353 .name = "inval",
354 .handler = arm7a_l2x_cache_inval_virt_cmd,
355 .mode = COMMAND_ANY,
356 .help = "invalidate l2x cache by virtual address offset and range size",
357 .usage = "<virt_addr> [size]",
358 },
359 {
360 .name = "clean",
361 .handler = arm7a_l2x_cache_clean_virt_cmd,
362 .mode = COMMAND_ANY,
363 .help = "clean l2x cache by virtual address address offset and range size",
364 .usage = "<virt_addr> [size]",
365 },
366 COMMAND_REGISTRATION_DONE
367 };
368
369 const struct command_registration arm7a_l2x_cache_command_handler[] = {
370 {
371 .name = "l2x",
372 .mode = COMMAND_ANY,
373 .help = "l2x cache command group",
374 .usage = "",
375 .chain = arm7a_l2x_cache_commands,
376 },
377 COMMAND_REGISTRATION_DONE
378 };