1 /***************************************************************************
2 * Copyright (C) 2015 by Oleksij Rempel *
3 * linux@rempel-privat.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 ***************************************************************************/
20 #include "jtag/interface.h"
23 #include "armv7a_cache.h"
24 #include <helper/time_support.h>
25 #include "arm_opcodes.h"
27 static int armv7a_l1_d_cache_sanity_check(struct target
*target
)
29 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
31 if (target
->state
!= TARGET_HALTED
) {
32 LOG_ERROR("%s: target not halted", __func__
);
33 return ERROR_TARGET_NOT_HALTED
;
36 /* check that cache data is on at target halt */
37 if (!armv7a
->armv7a_mmu
.armv7a_cache
.d_u_cache_enabled
) {
38 LOG_DEBUG("data cache is not enabled");
39 return ERROR_TARGET_INVALID
;
45 static int armv7a_l1_i_cache_sanity_check(struct target
*target
)
47 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
49 if (target
->state
!= TARGET_HALTED
) {
50 LOG_ERROR("%s: target not halted", __func__
);
51 return ERROR_TARGET_NOT_HALTED
;
54 /* check that cache data is on at target halt */
55 if (!armv7a
->armv7a_mmu
.armv7a_cache
.i_cache_enabled
) {
56 LOG_DEBUG("instruction cache is not enabled");
57 return ERROR_TARGET_INVALID
;
63 static int armv7a_l1_d_cache_flush_level(struct arm_dpm
*dpm
, struct armv7a_cachesize
*size
, int cl
)
65 int retval
= ERROR_OK
;
66 int32_t c_way
, c_index
= size
->index
;
68 LOG_DEBUG("cl %" PRId32
, cl
);
72 uint32_t value
= (c_index
<< size
->index_shift
)
73 | (c_way
<< size
->way_shift
) | (cl
<< 1);
75 * DCCISW - Clean and invalidate data cache
78 retval
= dpm
->instr_write_data_r0(dpm
,
79 ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
81 if (retval
!= ERROR_OK
)
86 } while (c_index
>= 0);
92 static int armv7a_l1_d_cache_clean_inval_all(struct target
*target
)
94 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
95 struct armv7a_cache_common
*cache
= &(armv7a
->armv7a_mmu
.armv7a_cache
);
96 struct arm_dpm
*dpm
= armv7a
->arm
.dpm
;
100 retval
= armv7a_l1_d_cache_sanity_check(target
);
101 if (retval
!= ERROR_OK
)
104 retval
= dpm
->prepare(dpm
);
105 if (retval
!= ERROR_OK
)
108 for (cl
= 0; cl
< cache
->loc
; cl
++) {
109 /* skip i-only caches */
110 if (cache
->arch
[cl
].ctype
< CACHE_LEVEL_HAS_D_CACHE
)
113 armv7a_l1_d_cache_flush_level(dpm
, &cache
->arch
[cl
].d_u_size
, cl
);
116 retval
= dpm
->finish(dpm
);
120 LOG_ERROR("clean invalidate failed");
126 int armv7a_cache_auto_flush_all_data(struct target
*target
)
128 int retval
= ERROR_FAIL
;
129 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
131 if (!armv7a
->armv7a_mmu
.armv7a_cache
.auto_cache_enabled
)
135 struct target_list
*head
;
138 while (head
!= (struct target_list
*)NULL
) {
140 if (curr
->state
== TARGET_HALTED
)
141 retval
= armv7a_l1_d_cache_clean_inval_all(curr
);
146 retval
= armv7a_l1_d_cache_clean_inval_all(target
);
148 /* do outer cache flushing after inner caches have been flushed */
149 retval
= arm7a_l2x_flush_all_data(target
);
155 int armv7a_l1_d_cache_inval_virt(struct target
*target
, uint32_t virt
,
158 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
159 struct arm_dpm
*dpm
= armv7a
->arm
.dpm
;
160 struct armv7a_cache_common
*armv7a_cache
= &armv7a
->armv7a_mmu
.armv7a_cache
;
161 uint32_t linelen
= armv7a_cache
->dminline
;
162 uint32_t va_line
, va_end
;
165 retval
= armv7a_l1_d_cache_sanity_check(target
);
166 if (retval
!= ERROR_OK
)
169 retval
= dpm
->prepare(dpm
);
170 if (retval
!= ERROR_OK
)
173 va_line
= virt
& (-linelen
);
174 va_end
= virt
+ size
;
176 /* handle unaligned start */
177 if (virt
!= va_line
) {
179 retval
= dpm
->instr_write_data_r0(dpm
,
180 ARMV4_5_MCR(15, 0, 0, 7, 14, 1), va_line
);
181 if (retval
!= ERROR_OK
)
186 /* handle unaligned end */
187 if ((va_end
& (linelen
-1)) != 0) {
188 va_end
&= (-linelen
);
190 retval
= dpm
->instr_write_data_r0(dpm
,
191 ARMV4_5_MCR(15, 0, 0, 7, 14, 1), va_end
);
192 if (retval
!= ERROR_OK
)
196 while (va_line
< va_end
) {
197 /* DCIMVAC - Invalidate data cache line by VA to PoC. */
198 retval
= dpm
->instr_write_data_r0(dpm
,
199 ARMV4_5_MCR(15, 0, 0, 7, 6, 1), va_line
);
200 if (retval
!= ERROR_OK
)
209 LOG_ERROR("d-cache invalidate failed");
215 int armv7a_l1_d_cache_clean_virt(struct target
*target
, uint32_t virt
,
218 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
219 struct arm_dpm
*dpm
= armv7a
->arm
.dpm
;
220 struct armv7a_cache_common
*armv7a_cache
= &armv7a
->armv7a_mmu
.armv7a_cache
;
221 uint32_t linelen
= armv7a_cache
->dminline
;
222 uint32_t va_line
, va_end
;
225 retval
= armv7a_l1_d_cache_sanity_check(target
);
226 if (retval
!= ERROR_OK
)
229 retval
= dpm
->prepare(dpm
);
230 if (retval
!= ERROR_OK
)
233 va_line
= virt
& (-linelen
);
234 va_end
= virt
+ size
;
236 while (va_line
< va_end
) {
237 /* DCCMVAC - Data Cache Clean by MVA to PoC */
238 retval
= dpm
->instr_write_data_r0(dpm
,
239 ARMV4_5_MCR(15, 0, 0, 7, 10, 1), va_line
);
240 if (retval
!= ERROR_OK
)
249 LOG_ERROR("d-cache invalidate failed");
255 int armv7a_l1_d_cache_flush_virt(struct target
*target
, uint32_t virt
,
258 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
259 struct arm_dpm
*dpm
= armv7a
->arm
.dpm
;
260 struct armv7a_cache_common
*armv7a_cache
= &armv7a
->armv7a_mmu
.armv7a_cache
;
261 uint32_t linelen
= armv7a_cache
->dminline
;
262 uint32_t va_line
, va_end
;
265 retval
= armv7a_l1_d_cache_sanity_check(target
);
266 if (retval
!= ERROR_OK
)
269 retval
= dpm
->prepare(dpm
);
270 if (retval
!= ERROR_OK
)
273 va_line
= virt
& (-linelen
);
274 va_end
= virt
+ size
;
276 while (va_line
< va_end
) {
278 retval
= dpm
->instr_write_data_r0(dpm
,
279 ARMV4_5_MCR(15, 0, 0, 7, 14, 1), va_line
);
280 if (retval
!= ERROR_OK
)
289 LOG_ERROR("d-cache invalidate failed");
295 int armv7a_l1_i_cache_inval_all(struct target
*target
)
297 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
298 struct arm_dpm
*dpm
= armv7a
->arm
.dpm
;
301 retval
= armv7a_l1_i_cache_sanity_check(target
);
302 if (retval
!= ERROR_OK
)
305 retval
= dpm
->prepare(dpm
);
306 if (retval
!= ERROR_OK
)
311 retval
= dpm
->instr_write_data_r0(dpm
,
312 ARMV4_5_MCR(15, 0, 0, 7, 1, 0), 0);
315 retval
= dpm
->instr_write_data_r0(dpm
,
316 ARMV4_5_MCR(15, 0, 0, 7, 5, 0), 0);
319 if (retval
!= ERROR_OK
)
326 LOG_ERROR("i-cache invalidate failed");
332 int armv7a_l1_i_cache_inval_virt(struct target
*target
, uint32_t virt
,
335 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
336 struct arm_dpm
*dpm
= armv7a
->arm
.dpm
;
337 struct armv7a_cache_common
*armv7a_cache
=
338 &armv7a
->armv7a_mmu
.armv7a_cache
;
339 uint32_t linelen
= armv7a_cache
->iminline
;
340 uint32_t va_line
, va_end
;
343 retval
= armv7a_l1_i_cache_sanity_check(target
);
344 if (retval
!= ERROR_OK
)
347 retval
= dpm
->prepare(dpm
);
348 if (retval
!= ERROR_OK
)
351 va_line
= virt
& (-linelen
);
352 va_end
= virt
+ size
;
354 while (va_line
< va_end
) {
355 /* ICIMVAU - Invalidate instruction cache by VA to PoU. */
356 retval
= dpm
->instr_write_data_r0(dpm
,
357 ARMV4_5_MCR(15, 0, 0, 7, 5, 1), va_line
);
358 if (retval
!= ERROR_OK
)
361 retval
= dpm
->instr_write_data_r0(dpm
,
362 ARMV4_5_MCR(15, 0, 0, 7, 5, 7), va_line
);
363 if (retval
!= ERROR_OK
)
370 LOG_ERROR("i-cache invalidate failed");
376 int armv7a_cache_flush_virt(struct target
*target
, uint32_t virt
,
379 armv7a_l1_d_cache_flush_virt(target
, virt
, size
);
380 armv7a_l2x_cache_flush_virt(target
, virt
, size
);
386 * We assume that target core was chosen correctly. It means if same data
387 * was handled by two cores, other core will loose the changes. Since it
388 * is impossible to know (FIXME) which core has correct data, keep in mind
389 * that some kind of data lost or korruption is possible.
391 * - core1 loaded and changed data on 0x12345678
392 * - we halted target and modified same data on core0
393 * - data on core1 will be lost.
395 int armv7a_cache_auto_flush_on_write(struct target
*target
, uint32_t virt
,
398 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
400 if (!armv7a
->armv7a_mmu
.armv7a_cache
.auto_cache_enabled
)
403 return armv7a_cache_flush_virt(target
, virt
, size
);
406 COMMAND_HANDLER(arm7a_l1_cache_info_cmd
)
408 struct target
*target
= get_current_target(CMD_CTX
);
409 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
411 return armv7a_handle_cache_info_command(CMD_CTX
,
412 &armv7a
->armv7a_mmu
.armv7a_cache
);
415 COMMAND_HANDLER(armv7a_l1_d_cache_clean_inval_all_cmd
)
417 struct target
*target
= get_current_target(CMD_CTX
);
419 armv7a_l1_d_cache_clean_inval_all(target
);
424 COMMAND_HANDLER(arm7a_l1_d_cache_inval_virt_cmd
)
426 struct target
*target
= get_current_target(CMD_CTX
);
429 if (CMD_ARGC
== 0 || CMD_ARGC
> 2)
430 return ERROR_COMMAND_SYNTAX_ERROR
;
433 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], size
);
437 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], virt
);
439 return armv7a_l1_d_cache_inval_virt(target
, virt
, size
);
442 COMMAND_HANDLER(arm7a_l1_d_cache_clean_virt_cmd
)
444 struct target
*target
= get_current_target(CMD_CTX
);
447 if (CMD_ARGC
== 0 || CMD_ARGC
> 2)
448 return ERROR_COMMAND_SYNTAX_ERROR
;
451 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], size
);
455 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], virt
);
457 return armv7a_l1_d_cache_clean_virt(target
, virt
, size
);
460 COMMAND_HANDLER(armv7a_i_cache_clean_inval_all_cmd
)
462 struct target
*target
= get_current_target(CMD_CTX
);
464 armv7a_l1_i_cache_inval_all(target
);
469 COMMAND_HANDLER(arm7a_l1_i_cache_inval_virt_cmd
)
471 struct target
*target
= get_current_target(CMD_CTX
);
474 if (CMD_ARGC
== 0 || CMD_ARGC
> 2)
475 return ERROR_COMMAND_SYNTAX_ERROR
;
478 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], size
);
482 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], virt
);
484 return armv7a_l1_i_cache_inval_virt(target
, virt
, size
);
487 COMMAND_HANDLER(arm7a_cache_disable_auto_cmd
)
489 struct target
*target
= get_current_target(CMD_CTX
);
490 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
493 command_print(CMD_CTX
, "auto cache is %s",
494 armv7a
->armv7a_mmu
.armv7a_cache
.auto_cache_enabled
? "enabled" : "disabled");
501 COMMAND_PARSE_ENABLE(CMD_ARGV
[0], set
);
502 armv7a
->armv7a_mmu
.armv7a_cache
.auto_cache_enabled
= !!set
;
506 return ERROR_COMMAND_SYNTAX_ERROR
;
509 static const struct command_registration arm7a_l1_d_cache_commands
[] = {
512 .handler
= armv7a_l1_d_cache_clean_inval_all_cmd
,
514 .help
= "flush (clean and invalidate) complete l1 d-cache",
519 .handler
= arm7a_l1_d_cache_inval_virt_cmd
,
521 .help
= "invalidate l1 d-cache by virtual address offset and range size",
522 .usage
= "<virt_addr> [size]",
526 .handler
= arm7a_l1_d_cache_clean_virt_cmd
,
528 .help
= "clean l1 d-cache by virtual address address offset and range size",
529 .usage
= "<virt_addr> [size]",
531 COMMAND_REGISTRATION_DONE
534 static const struct command_registration arm7a_l1_i_cache_commands
[] = {
537 .handler
= armv7a_i_cache_clean_inval_all_cmd
,
539 .help
= "invalidate complete l1 i-cache",
544 .handler
= arm7a_l1_i_cache_inval_virt_cmd
,
546 .help
= "invalidate l1 i-cache by virtual address offset and range size",
547 .usage
= "<virt_addr> [size]",
549 COMMAND_REGISTRATION_DONE
552 const struct command_registration arm7a_l1_di_cache_group_handlers
[] = {
555 .handler
= arm7a_l1_cache_info_cmd
,
557 .help
= "print cache realted information",
563 .help
= "l1 d-cache command group",
565 .chain
= arm7a_l1_d_cache_commands
,
570 .help
= "l1 i-cache command group",
572 .chain
= arm7a_l1_i_cache_commands
,
574 COMMAND_REGISTRATION_DONE
577 const struct command_registration arm7a_cache_group_handlers
[] = {
580 .handler
= arm7a_cache_disable_auto_cmd
,
582 .help
= "disable or enable automatic cache handling.",
588 .help
= "l1 cache command group",
590 .chain
= arm7a_l1_di_cache_group_handlers
,
593 .chain
= arm7a_l2x_cache_command_handler
,
595 COMMAND_REGISTRATION_DONE
598 const struct command_registration arm7a_cache_command_handlers
[] = {
602 .help
= "cache command group",
604 .chain
= arm7a_cache_group_handlers
,
606 COMMAND_REGISTRATION_DONE
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