c775d0c24debee287f4332c666e6352a5c5cd284
[openocd.git] / src / target / armv7a.h
1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19 #ifndef ARMV7A_H
20 #define ARMV7A_H
21
22 #include "register.h"
23 #include "target.h"
24 #include "log.h"
25 #include "arm_adi_v5.h"
26 #include "armv4_5.h"
27 #include "armv4_5_mmu.h"
28 #include "armv4_5_cache.h"
29
30 typedef enum armv7a_mode
31 {
32 ARMV7A_MODE_USR = 16,
33 ARMV7A_MODE_FIQ = 17,
34 ARMV7A_MODE_IRQ = 18,
35 ARMV7A_MODE_SVC = 19,
36 ARMV7A_MODE_ABT = 23,
37 ARMV7A_MODE_UND = 27,
38 ARMV7A_MODE_SYS = 31,
39 ARMV7A_MODE_MON = 22,
40 ARMV7A_MODE_ANY = -1
41 } armv7a_t;
42
43 extern char **armv7a_mode_strings;
44
45 typedef enum armv7a_state
46 {
47 ARMV7A_STATE_ARM,
48 ARMV7A_STATE_THUMB,
49 ARMV7A_STATE_JAZELLE,
50 ARMV7A_STATE_THUMBEE,
51 } armv7a_state_t;
52
53 extern char *armv7a_state_strings[];
54
55 extern int armv7a_core_reg_map[8][17];
56
57 #define ARMV7A_CORE_REG_MODE(cache, mode, num) \
58 cache->reg_list[armv7a_core_reg_map[armv7a_mode_to_number(mode)][num]]
59 #define ARMV7A_CORE_REG_MODENUM(cache, mode, num) \
60 cache->reg_list[armv7a_core_reg_map[mode][num]]
61
62 enum
63 {
64 ARM_PC = 15,
65 ARM_CPSR = 16
66 }
67 ;
68 /* offsets into armv4_5 core register cache */
69 enum
70 {
71 ARMV7A_CPSR = 31,
72 ARMV7A_SPSR_FIQ = 32,
73 ARMV7A_SPSR_IRQ = 33,
74 ARMV7A_SPSR_SVC = 34,
75 ARMV7A_SPSR_ABT = 35,
76 ARMV7A_SPSR_UND = 36
77 };
78
79 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
80 #define ARMV7_COMMON_MAGIC 0x0A450999
81
82 /* VA to PA translation operations opc2 values*/
83 #define V2PCWPR 0
84 #define V2PCWPW 1
85 #define V2PCWUR 2
86 #define V2PCWUW 3
87 #define V2POWPR 4
88 #define V2POWPW 5
89 #define V2POWUR 6
90 #define V2POWUW 7
91
92 struct armv7a_common
93 {
94 int common_magic;
95 struct reg_cache *core_cache;
96 enum armv7a_mode core_mode;
97 enum armv7a_state core_state;
98
99 /* arm adp debug port */
100 struct swjdp_common swjdp_info;
101
102 /* Core Debug Unit */
103 uint32_t debug_base;
104 uint8_t debug_ap;
105 uint8_t memory_ap;
106
107 /* Cache and Memory Management Unit */
108 struct armv4_5_mmu_common armv4_5_mmu;
109 struct arm armv4_5_common;
110
111 // int (*full_context)(struct target_s *target);
112 // int (*read_core_reg)(struct target_s *target, int num, enum armv7a_mode mode);
113 // int (*write_core_reg)(struct target_s *target, int num, enum armv7a_mode mode, u32 value);
114 int (*read_cp15)(struct target_s *target,
115 uint32_t op1, uint32_t op2,
116 uint32_t CRn, uint32_t CRm, uint32_t *value);
117 int (*write_cp15)(struct target_s *target,
118 uint32_t op1, uint32_t op2,
119 uint32_t CRn, uint32_t CRm, uint32_t value);
120
121 int (*examine_debug_reason)(target_t *target);
122 void (*post_debug_entry)(target_t *target);
123
124 void (*pre_restore_context)(target_t *target);
125 void (*post_restore_context)(target_t *target);
126
127 };
128
129 static inline struct armv7a_common *
130 target_to_armv7a(struct target_s *target)
131 {
132 return container_of(target->arch_info, struct armv7a_common,
133 armv4_5_common);
134 }
135
136 struct armv7a_algorithm
137 {
138 int common_magic;
139
140 enum armv7a_mode core_mode;
141 enum armv7a_state core_state;
142 };
143
144 struct armv7a_core_reg
145 {
146 int num;
147 enum armv7a_mode mode;
148 target_t *target;
149 struct armv7a_common *armv7a_common;
150 };
151
152 int armv7a_arch_state(struct target_s *target);
153 struct reg_cache *armv7a_build_reg_cache(target_t *target,
154 struct armv7a_common *armv7a_common);
155 int armv7a_register_commands(struct command_context_s *cmd_ctx);
156 int armv7a_init_arch_info(target_t *target, struct armv7a_common *armv7a);
157
158 /* map psr mode bits to linear number */
159 static inline int armv7a_mode_to_number(enum armv7a_mode mode)
160 {
161 switch (mode)
162 {
163 case ARMV7A_MODE_USR: return 0; break;
164 case ARMV7A_MODE_FIQ: return 1; break;
165 case ARMV7A_MODE_IRQ: return 2; break;
166 case ARMV7A_MODE_SVC: return 3; break;
167 case ARMV7A_MODE_ABT: return 4; break;
168 case ARMV7A_MODE_UND: return 5; break;
169 case ARMV7A_MODE_SYS: return 6; break;
170 case ARMV7A_MODE_MON: return 7; break;
171 case ARMV7A_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
172 default:
173 LOG_ERROR("invalid mode value encountered, val %d", mode);
174 return -1;
175 }
176 }
177
178 /* map linear number to mode bits */
179 static inline enum armv7a_mode armv7a_number_to_mode(int number)
180 {
181 switch(number)
182 {
183 case 0: return ARMV7A_MODE_USR; break;
184 case 1: return ARMV7A_MODE_FIQ; break;
185 case 2: return ARMV7A_MODE_IRQ; break;
186 case 3: return ARMV7A_MODE_SVC; break;
187 case 4: return ARMV7A_MODE_ABT; break;
188 case 5: return ARMV7A_MODE_UND; break;
189 case 6: return ARMV7A_MODE_SYS; break;
190 case 7: return ARMV7A_MODE_MON; break;
191 default:
192 LOG_ERROR("mode index out of bounds");
193 return ARMV7A_MODE_ANY;
194 }
195 };
196
197
198 #endif /* ARMV4_5_H */