6f54ce6b8eb564770a754427a787e0aef6012f64
[openocd.git] / src / target / armv7a.h
1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19 #ifndef ARMV7A_H
20 #define ARMV7A_H
21
22 #include "arm_adi_v5.h"
23 #include "arm.h"
24 #include "armv4_5_mmu.h"
25 #include "armv4_5_cache.h"
26 #include "arm_dpm.h"
27
28 enum
29 {
30 ARM_PC = 15,
31 ARM_CPSR = 16
32 }
33 ;
34
35 #define ARMV7_COMMON_MAGIC 0x0A450999
36
37 /* VA to PA translation operations opc2 values*/
38 #define V2PCWPR 0
39 #define V2PCWPW 1
40 #define V2PCWUR 2
41 #define V2PCWUW 3
42 #define V2POWPR 4
43 #define V2POWPW 5
44 #define V2POWUR 6
45 #define V2POWUW 7
46 /* L210/L220 cache controller support */
47 struct armv7a_l2x_cache {
48 uint32_t base;
49 uint32_t way;
50 };
51
52 struct armv7a_cachesize
53 {
54 uint32_t level_num;
55 /* cache dimensionning */
56 uint32_t linelen;
57 uint32_t associativity;
58 uint32_t nsets;
59 uint32_t cachesize;
60 /* info for set way operation on cache */
61 uint32_t index;
62 uint32_t index_shift;
63 uint32_t way;
64 uint32_t way_shift;
65 };
66
67
68 struct armv7a_cache_common
69 {
70 int ctype;
71 struct armv7a_cachesize d_u_size; /* data cache */
72 struct armv7a_cachesize i_size; /* instruction cache */
73 int i_cache_enabled;
74 int d_u_cache_enabled;
75 /* l2 external unified cache if some */
76 void *l2_cache;
77 int (*flush_all_data_cache)(struct target *target);
78 int (*display_cache_info)(struct command_context *cmd_ctx,
79 struct armv7a_cache_common *armv7a_cache);
80 };
81
82
83 struct armv7a_mmu_common
84 {
85 /* following field mmu working way */
86 int32_t ttbr1_used; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */
87 uint32_t ttbr0_mask;/* masked to be used */
88 uint32_t os_border;
89
90 int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
91 struct armv7a_cache_common armv7a_cache;
92 uint32_t mmu_enabled;
93 };
94
95
96
97 struct armv7a_common
98 {
99 struct arm armv4_5_common;
100 int common_magic;
101 struct reg_cache *core_cache;
102
103 struct adiv5_dap dap;
104
105 /* Core Debug Unit */
106 struct arm_dpm dpm;
107 uint32_t debug_base;
108 uint8_t debug_ap;
109 uint8_t memory_ap;
110 /* mdir */
111 uint8_t multi_processor_system;
112 uint8_t cluster_id;
113 uint8_t cpu_id;
114
115 /* cache specific to V7 Memory Management Unit compatible with v4_5*/
116 struct armv7a_mmu_common armv7a_mmu;
117
118 int (*examine_debug_reason)(struct target *target);
119 int (*post_debug_entry)(struct target *target);
120
121 void (*pre_restore_context)(struct target *target);
122 };
123
124 static inline struct armv7a_common *
125 target_to_armv7a(struct target *target)
126 {
127 return container_of(target->arch_info, struct armv7a_common,
128 armv4_5_common);
129 }
130
131 /* register offsets from armv7a.debug_base */
132
133 /* See ARMv7a arch spec section C10.2 */
134 #define CPUDBG_DIDR 0x000
135
136 /* See ARMv7a arch spec section C10.3 */
137 #define CPUDBG_WFAR 0x018
138 /* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
139 #define CPUDBG_DSCR 0x088
140 #define CPUDBG_DRCR 0x090
141 #define CPUDBG_PRCR 0x310
142 #define CPUDBG_PRSR 0x314
143
144 /* See ARMv7a arch spec section C10.4 */
145 #define CPUDBG_DTRRX 0x080
146 #define CPUDBG_ITR 0x084
147 #define CPUDBG_DTRTX 0x08c
148
149 /* See ARMv7a arch spec section C10.5 */
150 #define CPUDBG_BVR_BASE 0x100
151 #define CPUDBG_BCR_BASE 0x140
152 #define CPUDBG_WVR_BASE 0x180
153 #define CPUDBG_WCR_BASE 0x1C0
154 #define CPUDBG_VCR 0x01C
155
156 /* See ARMv7a arch spec section C10.6 */
157 #define CPUDBG_OSLAR 0x300
158 #define CPUDBG_OSLSR 0x304
159 #define CPUDBG_OSSRR 0x308
160 #define CPUDBG_ECR 0x024
161
162 /* See ARMv7a arch spec section C10.7 */
163 #define CPUDBG_DSCCR 0x028
164
165 /* See ARMv7a arch spec section C10.8 */
166 #define CPUDBG_AUTHSTATUS 0xFB8
167
168 int armv7a_arch_state(struct target *target);
169 int armv7a_identify_cache(struct target *target);
170 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
171 int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
172 uint32_t *val,int meminfo);
173 int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val);
174
175 int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
176 struct armv7a_cache_common *armv7a_cache);
177
178 extern const struct command_registration armv7a_command_handlers[];
179
180 #endif /* ARMV4_5_H */