4357c92ffd3f735b9afdab43efbff22e4a500f4b
[openocd.git] / src / target / armv4_5_mmu.h
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifndef ARMV4_5_MMU_H
21 #define ARMV4_5_MMU_H
22
23 #include "armv4_5_cache.h"
24 #include "target.h"
25
26 struct armv4_5_mmu_common
27 {
28 uint32_t (*get_ttb)(target_t *target);
29 int (*read_memory)(target_t *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
30 int (*write_memory)(target_t *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
31 void (*disable_mmu_caches)(target_t *target, int mmu, int d_u_cache, int i_cache);
32 void (*enable_mmu_caches)(target_t *target, int mmu, int d_u_cache, int i_cache);
33 struct armv4_5_cache_common armv4_5_cache;
34 int has_tiny_pages;
35 int mmu_enabled;
36 };
37
38 enum
39 {
40 ARMV4_5_SECTION, ARMV4_5_LARGE_PAGE, ARMV4_5_SMALL_PAGE, ARMV4_5_TINY_PAGE
41 };
42
43 extern char* armv4_5_page_type_names[];
44
45 uint32_t armv4_5_mmu_translate_va(target_t *target,
46 struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, int *type,
47 uint32_t *cb, int *domain, uint32_t *ap);
48
49 int armv4_5_mmu_read_physical(target_t *target,
50 struct armv4_5_mmu_common *armv4_5_mmu,
51 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
52
53 int armv4_5_mmu_write_physical(target_t *target,
54 struct armv4_5_mmu_common *armv4_5_mmu,
55 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
56
57 enum
58 {
59 ARMV4_5_MMU_ENABLED = 0x1,
60 ARMV4_5_ALIGNMENT_CHECK = 0x2,
61 ARMV4_5_MMU_S_BIT = 0x100,
62 ARMV4_5_MMU_R_BIT = 0x200
63 };
64
65 #endif /* ARMV4_5_MMU_H */