src/target/armv4_5_mmu.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include <helper/log.h>
  25 #include "target.h"
  26 #include "armv4_5_mmu.h"
  27
  28
  29 int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, int *type, uint32_t *cb, int *domain, uint32_t *ap, uint32_t *val)
  30 {
  31         uint32_t first_lvl_descriptor = 0x0;
  32         uint32_t second_lvl_descriptor = 0x0;
  33         uint32_t ttb = armv4_5_mmu->get_ttb(target);
  34         int retval;
  35
  36         retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
  37                 (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
  38                 4, 1, (uint8_t*)&first_lvl_descriptor);
  39         if (retval != ERROR_OK)
  40           return retval;
  41         first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&first_lvl_descriptor);
  42
  43         LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
  44
  45         if ((first_lvl_descriptor & 0x3) == 0)
  46         {
  47                 *type = -1;
  48                 LOG_ERROR("Address translation failure");
  49                 return ERROR_TARGET_TRANSLATION_FAULT;
  50         }
  51
  52         if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3))
  53         {
  54                 *type = -1;
  55                 LOG_ERROR("Address translation failure");
  56                 return ERROR_TARGET_TRANSLATION_FAULT;
  57         }
  58
  59         /* domain is always specified in bits 8-5 */
  60         *domain = (first_lvl_descriptor & 0x1e0) >> 5;
  61
  62         if ((first_lvl_descriptor & 0x3) == 2)
  63         {
  64                 /* section descriptor */
  65                 *type = ARMV4_5_SECTION;
  66                 *cb = (first_lvl_descriptor & 0xc) >> 2;
  67                 *ap = (first_lvl_descriptor & 0xc00) >> 10;
  68                 *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
  69                 return ERROR_OK;
  70         }
  71
  72         if ((first_lvl_descriptor & 0x3) == 1)
  73         {
  74                 /* coarse page table */
  75                 retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
  76                         (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
  77                         4, 1, (uint8_t*)&second_lvl_descriptor);
  78                 if (retval != ERROR_OK)
  79                         return retval;
  80         }
  81         else if ((first_lvl_descriptor & 0x3) == 3)
  82         {
  83                 /* fine page table */
  84                 retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
  85                         (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
  86                         4, 1, (uint8_t*)&second_lvl_descriptor);
  87                 if (retval != ERROR_OK)
  88                         return retval;
  89         }
  90
  91         second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&second_lvl_descriptor);
  92
  93         LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
  94
  95         if ((second_lvl_descriptor & 0x3) == 0)
  96         {
  97                 *type = -1;
  98                 LOG_ERROR("Address translation failure");
  99                 return ERROR_TARGET_TRANSLATION_FAULT;
 100         }
 101
 102         /* cacheable/bufferable is always specified in bits 3-2 */
 103         *cb = (second_lvl_descriptor & 0xc) >> 2;
 104
 105         if ((second_lvl_descriptor & 0x3) == 1)
 106         {
 107                 /* large page descriptor */
 108                 *type = ARMV4_5_LARGE_PAGE;
 109                 *ap = (second_lvl_descriptor & 0xff0) >> 4;
 110                 *val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
 111                 return ERROR_OK;
 112         }
 113
 114         if ((second_lvl_descriptor & 0x3) == 2)
 115         {
 116                 /* small page descriptor */
 117                 *type = ARMV4_5_SMALL_PAGE;
 118                 *ap = (second_lvl_descriptor & 0xff0) >> 4;
 119                 *val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
 120                 return ERROR_OK;
 121         }
 122
 123         if ((second_lvl_descriptor & 0x3) == 3)
 124         {
 125                 /* tiny page descriptor */
 126                 *type = ARMV4_5_TINY_PAGE;
 127                 *ap = (second_lvl_descriptor & 0x30) >> 4;
 128                 *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
 129                 return ERROR_OK;
 130         }
 131
 132         /* should not happen */
 133         *type = -1;
 134         LOG_ERROR("Address translation failure");
 135         return ERROR_TARGET_TRANSLATION_FAULT;
 136 }
 137
 138 int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 139 {
 140         int retval;
 141
 142         if (target->state != TARGET_HALTED)
 143                 return ERROR_TARGET_NOT_HALTED;
 144
 145         /* disable MMU and data (or unified) cache */
 146         armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
 147
 148         retval = armv4_5_mmu->read_memory(target, address, size, count, buffer);
 149
 150         /* reenable MMU / cache */
 151         armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
 152                 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
 153                 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
 154
 155         return retval;
 156 }
 157
 158 int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 159 {
 160         int retval;
 161
 162         if (target->state != TARGET_HALTED)
 163                 return ERROR_TARGET_NOT_HALTED;
 164
 165         /* disable MMU and data (or unified) cache */
 166         armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
 167
 168         retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
 169
 170         /* reenable MMU / cache */
 171         armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
 172                 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
 173                 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
 174
 175         return retval;
 176 }