52756c11e6319885e698cf66cf91ae7100b032d5
[openocd.git] / src / target / armv4_5_mmu.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include <helper/log.h>
25 #include "target.h"
26 #include "armv4_5_mmu.h"
27
28
29 int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, int *type, uint32_t *cb, int *domain, uint32_t *ap, uint32_t *val)
30 {
31 uint32_t first_lvl_descriptor = 0x0;
32 uint32_t second_lvl_descriptor = 0x0;
33 uint32_t ttb = armv4_5_mmu->get_ttb(target);
34 int retval;
35
36 retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
37 (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
38 4, 1, (uint8_t*)&first_lvl_descriptor);
39 if (retval != ERROR_OK)
40 return retval;
41 first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&first_lvl_descriptor);
42
43 LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
44
45 if ((first_lvl_descriptor & 0x3) == 0)
46 {
47 LOG_ERROR("Address translation failure");
48 return ERROR_TARGET_TRANSLATION_FAULT;
49 }
50
51 if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3))
52 {
53 LOG_ERROR("Address translation failure");
54 return ERROR_TARGET_TRANSLATION_FAULT;
55 }
56
57 /* domain is always specified in bits 8-5 */
58 *domain = (first_lvl_descriptor & 0x1e0) >> 5;
59
60 if ((first_lvl_descriptor & 0x3) == 2)
61 {
62 /* section descriptor */
63 *type = ARMV4_5_SECTION;
64 *cb = (first_lvl_descriptor & 0xc) >> 2;
65 *ap = (first_lvl_descriptor & 0xc00) >> 10;
66 *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
67 return ERROR_OK;
68 }
69
70 if ((first_lvl_descriptor & 0x3) == 1)
71 {
72 /* coarse page table */
73 retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
74 (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
75 4, 1, (uint8_t*)&second_lvl_descriptor);
76 if (retval != ERROR_OK)
77 return retval;
78 }
79 else if ((first_lvl_descriptor & 0x3) == 3)
80 {
81 /* fine page table */
82 retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
83 (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
84 4, 1, (uint8_t*)&second_lvl_descriptor);
85 if (retval != ERROR_OK)
86 return retval;
87 }
88
89 second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&second_lvl_descriptor);
90
91 LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
92
93 if ((second_lvl_descriptor & 0x3) == 0)
94 {
95 LOG_ERROR("Address translation failure");
96 return ERROR_TARGET_TRANSLATION_FAULT;
97 }
98
99 /* cacheable/bufferable is always specified in bits 3-2 */
100 *cb = (second_lvl_descriptor & 0xc) >> 2;
101
102 if ((second_lvl_descriptor & 0x3) == 1)
103 {
104 /* large page descriptor */
105 *type = ARMV4_5_LARGE_PAGE;
106 *ap = (second_lvl_descriptor & 0xff0) >> 4;
107 *val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
108 return ERROR_OK;
109 }
110
111 if ((second_lvl_descriptor & 0x3) == 2)
112 {
113 /* small page descriptor */
114 *type = ARMV4_5_SMALL_PAGE;
115 *ap = (second_lvl_descriptor & 0xff0) >> 4;
116 *val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
117 return ERROR_OK;
118 }
119
120 if ((second_lvl_descriptor & 0x3) == 3)
121 {
122 /* tiny page descriptor */
123 *type = ARMV4_5_TINY_PAGE;
124 *ap = (second_lvl_descriptor & 0x30) >> 4;
125 *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
126 return ERROR_OK;
127 }
128
129 /* should not happen */
130 LOG_ERROR("Address translation failure");
131 return ERROR_TARGET_TRANSLATION_FAULT;
132 }
133
134 int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
135 {
136 int retval;
137
138 if (target->state != TARGET_HALTED)
139 return ERROR_TARGET_NOT_HALTED;
140
141 /* disable MMU and data (or unified) cache */
142 armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
143
144 retval = armv4_5_mmu->read_memory(target, address, size, count, buffer);
145
146 /* reenable MMU / cache */
147 armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
148 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
149 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
150
151 return retval;
152 }
153
154 int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
155 {
156 int retval;
157
158 if (target->state != TARGET_HALTED)
159 return ERROR_TARGET_NOT_HALTED;
160
161 /* disable MMU and data (or unified) cache */
162 armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
163
164 retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
165
166 /* reenable MMU / cache */
167 armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
168 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
169 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
170
171 return retval;
172 }

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