1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2005 by Dominic Rath *
5 * Dominic.Rath@gmx.de *
7 * Copyright (C) 2008 by Spencer Oliver *
8 * spen@spen-soft.co.uk *
10 * Copyright (C) 2008 by Oyvind Harboe *
11 * oyvind.harboe@zylin.com *
13 * Copyright (C) 2018 by Liviu Ionescu *
15 ***************************************************************************/
24 #include "breakpoints.h"
25 #include "arm_disassembler.h"
26 #include <helper/binarybuffer.h>
27 #include "algorithm.h"
29 #include "semihosting_common.h"
31 /* offsets into armv4_5 core register cache */
33 /* ARMV4_5_CPSR = 31, */
34 ARMV4_5_SPSR_FIQ
= 32,
35 ARMV4_5_SPSR_IRQ
= 33,
36 ARMV4_5_SPSR_SVC
= 34,
37 ARMV4_5_SPSR_ABT
= 35,
38 ARMV4_5_SPSR_UND
= 36,
43 static const uint8_t arm_usr_indices
[17] = {
44 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR
,
47 static const uint8_t arm_fiq_indices
[8] = {
48 16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ
,
51 static const uint8_t arm_irq_indices
[3] = {
52 23, 24, ARMV4_5_SPSR_IRQ
,
55 static const uint8_t arm_svc_indices
[3] = {
56 25, 26, ARMV4_5_SPSR_SVC
,
59 static const uint8_t arm_abt_indices
[3] = {
60 27, 28, ARMV4_5_SPSR_ABT
,
63 static const uint8_t arm_und_indices
[3] = {
64 29, 30, ARMV4_5_SPSR_UND
,
67 static const uint8_t arm_mon_indices
[3] = {
71 static const uint8_t arm_hyp_indices
[2] = {
78 /* For user and system modes, these list indices for all registers.
79 * otherwise they're just indices for the shadow registers and SPSR.
81 unsigned short n_indices
;
82 const uint8_t *indices
;
84 /* Seven modes are standard from ARM7 on. "System" and "User" share
85 * the same registers; other modes shadow from 3 to 8 registers.
90 .n_indices
= ARRAY_SIZE(arm_usr_indices
),
91 .indices
= arm_usr_indices
,
96 .n_indices
= ARRAY_SIZE(arm_fiq_indices
),
97 .indices
= arm_fiq_indices
,
100 .name
= "Supervisor",
102 .n_indices
= ARRAY_SIZE(arm_svc_indices
),
103 .indices
= arm_svc_indices
,
108 .n_indices
= ARRAY_SIZE(arm_abt_indices
),
109 .indices
= arm_abt_indices
,
114 .n_indices
= ARRAY_SIZE(arm_irq_indices
),
115 .indices
= arm_irq_indices
,
118 .name
= "Undefined instruction",
120 .n_indices
= ARRAY_SIZE(arm_und_indices
),
121 .indices
= arm_und_indices
,
126 .n_indices
= ARRAY_SIZE(arm_usr_indices
),
127 .indices
= arm_usr_indices
,
129 /* TrustZone "Security Extensions" add a secure monitor mode.
130 * This is distinct from a "debug monitor" which can support
131 * non-halting debug, in conjunction with some debuggers.
134 .name
= "Secure Monitor",
136 .n_indices
= ARRAY_SIZE(arm_mon_indices
),
137 .indices
= arm_mon_indices
,
140 .name
= "Secure Monitor ARM1176JZF-S",
141 .psr
= ARM_MODE_1176_MON
,
142 .n_indices
= ARRAY_SIZE(arm_mon_indices
),
143 .indices
= arm_mon_indices
,
146 /* These special modes are currently only supported
147 * by ARMv6M and ARMv7M profiles */
150 .psr
= ARM_MODE_THREAD
,
153 .name
= "Thread (User)",
154 .psr
= ARM_MODE_USER_THREAD
,
158 .psr
= ARM_MODE_HANDLER
,
161 /* armv7-a with virtualization extension */
163 .name
= "Hypervisor",
165 .n_indices
= ARRAY_SIZE(arm_hyp_indices
),
166 .indices
= arm_hyp_indices
,
170 /** Map PSR mode bits to the name of an ARM processor operating mode. */
171 const char *arm_mode_name(unsigned psr_mode
)
173 for (unsigned i
= 0; i
< ARRAY_SIZE(arm_mode_data
); i
++) {
174 if (arm_mode_data
[i
].psr
== psr_mode
)
175 return arm_mode_data
[i
].name
;
177 LOG_ERROR("unrecognized psr mode: %#02x", psr_mode
);
178 return "UNRECOGNIZED";
181 /** Return true iff the parameter denotes a valid ARM processor mode. */
182 bool is_arm_mode(unsigned psr_mode
)
184 for (unsigned i
= 0; i
< ARRAY_SIZE(arm_mode_data
); i
++) {
185 if (arm_mode_data
[i
].psr
== psr_mode
)
191 /** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
192 int arm_mode_to_number(enum arm_mode mode
)
196 /* map MODE_ANY to user mode */
212 case ARM_MODE_1176_MON
:
217 LOG_ERROR("invalid mode value encountered %d", mode
);
222 /** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
223 enum arm_mode
armv4_5_number_to_mode(int number
)
245 LOG_ERROR("mode index out of bounds %d", number
);
250 static const char *arm_state_strings
[] = {
251 "ARM", "Thumb", "Jazelle", "ThumbEE",
254 /* Templates for ARM core registers.
256 * NOTE: offsets in this table are coupled to the arm_mode_data
257 * table above, the armv4_5_core_reg_map array below, and also to
258 * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates).
260 static const struct {
261 /* The name is used for e.g. the "regs" command. */
264 /* The {cookie, mode} tuple uniquely identifies one register.
265 * In a given mode, cookies 0..15 map to registers R0..R15,
266 * with R13..R15 usually called SP, LR, PC.
268 * MODE_ANY is used as *input* to the mapping, and indicates
269 * various special cases (sigh) and errors.
271 * Cookie 16 is (currently) confusing, since it indicates
272 * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
273 * (Exception modes have both CPSR and SPSR registers ...)
278 } arm_core_regs
[] = {
279 /* IMPORTANT: we guarantee that the first eight cached registers
280 * correspond to r0..r7, and the fifteenth to PC, so that callers
281 * don't need to map them.
283 [0] = { .name
= "r0", .cookie
= 0, .mode
= ARM_MODE_ANY
, .gdb_index
= 0, },
284 [1] = { .name
= "r1", .cookie
= 1, .mode
= ARM_MODE_ANY
, .gdb_index
= 1, },
285 [2] = { .name
= "r2", .cookie
= 2, .mode
= ARM_MODE_ANY
, .gdb_index
= 2, },
286 [3] = { .name
= "r3", .cookie
= 3, .mode
= ARM_MODE_ANY
, .gdb_index
= 3, },
287 [4] = { .name
= "r4", .cookie
= 4, .mode
= ARM_MODE_ANY
, .gdb_index
= 4, },
288 [5] = { .name
= "r5", .cookie
= 5, .mode
= ARM_MODE_ANY
, .gdb_index
= 5, },
289 [6] = { .name
= "r6", .cookie
= 6, .mode
= ARM_MODE_ANY
, .gdb_index
= 6, },
290 [7] = { .name
= "r7", .cookie
= 7, .mode
= ARM_MODE_ANY
, .gdb_index
= 7, },
292 /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
293 * them as MODE_ANY creates special cases. (ANY means
294 * "not mapped" elsewhere; here it's "everything but FIQ".)
296 [8] = { .name
= "r8", .cookie
= 8, .mode
= ARM_MODE_ANY
, .gdb_index
= 8, },
297 [9] = { .name
= "r9", .cookie
= 9, .mode
= ARM_MODE_ANY
, .gdb_index
= 9, },
298 [10] = { .name
= "r10", .cookie
= 10, .mode
= ARM_MODE_ANY
, .gdb_index
= 10, },
299 [11] = { .name
= "r11", .cookie
= 11, .mode
= ARM_MODE_ANY
, .gdb_index
= 11, },
300 [12] = { .name
= "r12", .cookie
= 12, .mode
= ARM_MODE_ANY
, .gdb_index
= 12, },
302 /* Historical GDB mapping of indices:
303 * - 13-14 are sp and lr, but banked counterparts are used
304 * - 16-24 are left for deprecated 8 FPA + 1 FPS
308 /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
309 [13] = { .name
= "sp_usr", .cookie
= 13, .mode
= ARM_MODE_USR
, .gdb_index
= 26, },
310 [14] = { .name
= "lr_usr", .cookie
= 14, .mode
= ARM_MODE_USR
, .gdb_index
= 27, },
312 /* guaranteed to be at index 15 */
313 [15] = { .name
= "pc", .cookie
= 15, .mode
= ARM_MODE_ANY
, .gdb_index
= 15, },
314 [16] = { .name
= "r8_fiq", .cookie
= 8, .mode
= ARM_MODE_FIQ
, .gdb_index
= 28, },
315 [17] = { .name
= "r9_fiq", .cookie
= 9, .mode
= ARM_MODE_FIQ
, .gdb_index
= 29, },
316 [18] = { .name
= "r10_fiq", .cookie
= 10, .mode
= ARM_MODE_FIQ
, .gdb_index
= 30, },
317 [19] = { .name
= "r11_fiq", .cookie
= 11, .mode
= ARM_MODE_FIQ
, .gdb_index
= 31, },
318 [20] = { .name
= "r12_fiq", .cookie
= 12, .mode
= ARM_MODE_FIQ
, .gdb_index
= 32, },
320 [21] = { .name
= "sp_fiq", .cookie
= 13, .mode
= ARM_MODE_FIQ
, .gdb_index
= 33, },
321 [22] = { .name
= "lr_fiq", .cookie
= 14, .mode
= ARM_MODE_FIQ
, .gdb_index
= 34, },
323 [23] = { .name
= "sp_irq", .cookie
= 13, .mode
= ARM_MODE_IRQ
, .gdb_index
= 35, },
324 [24] = { .name
= "lr_irq", .cookie
= 14, .mode
= ARM_MODE_IRQ
, .gdb_index
= 36, },
326 [25] = { .name
= "sp_svc", .cookie
= 13, .mode
= ARM_MODE_SVC
, .gdb_index
= 37, },
327 [26] = { .name
= "lr_svc", .cookie
= 14, .mode
= ARM_MODE_SVC
, .gdb_index
= 38, },
329 [27] = { .name
= "sp_abt", .cookie
= 13, .mode
= ARM_MODE_ABT
, .gdb_index
= 39, },
330 [28] = { .name
= "lr_abt", .cookie
= 14, .mode
= ARM_MODE_ABT
, .gdb_index
= 40, },
332 [29] = { .name
= "sp_und", .cookie
= 13, .mode
= ARM_MODE_UND
, .gdb_index
= 41, },
333 [30] = { .name
= "lr_und", .cookie
= 14, .mode
= ARM_MODE_UND
, .gdb_index
= 42, },
335 [31] = { .name
= "cpsr", .cookie
= 16, .mode
= ARM_MODE_ANY
, .gdb_index
= 25, },
336 [32] = { .name
= "spsr_fiq", .cookie
= 16, .mode
= ARM_MODE_FIQ
, .gdb_index
= 43, },
337 [33] = { .name
= "spsr_irq", .cookie
= 16, .mode
= ARM_MODE_IRQ
, .gdb_index
= 44, },
338 [34] = { .name
= "spsr_svc", .cookie
= 16, .mode
= ARM_MODE_SVC
, .gdb_index
= 45, },
339 [35] = { .name
= "spsr_abt", .cookie
= 16, .mode
= ARM_MODE_ABT
, .gdb_index
= 46, },
340 [36] = { .name
= "spsr_und", .cookie
= 16, .mode
= ARM_MODE_UND
, .gdb_index
= 47, },
342 /* These are only used for GDB target description, banked registers are accessed instead */
343 [37] = { .name
= "sp", .cookie
= 13, .mode
= ARM_MODE_ANY
, .gdb_index
= 13, },
344 [38] = { .name
= "lr", .cookie
= 14, .mode
= ARM_MODE_ANY
, .gdb_index
= 14, },
346 /* These exist only when the Security Extension (TrustZone) is present */
347 [39] = { .name
= "sp_mon", .cookie
= 13, .mode
= ARM_MODE_MON
, .gdb_index
= 48, },
348 [40] = { .name
= "lr_mon", .cookie
= 14, .mode
= ARM_MODE_MON
, .gdb_index
= 49, },
349 [41] = { .name
= "spsr_mon", .cookie
= 16, .mode
= ARM_MODE_MON
, .gdb_index
= 50, },
351 /* These exist only when the Virtualization Extensions is present */
352 [42] = { .name
= "sp_hyp", .cookie
= 13, .mode
= ARM_MODE_HYP
, .gdb_index
= 51, },
353 [43] = { .name
= "spsr_hyp", .cookie
= 16, .mode
= ARM_MODE_HYP
, .gdb_index
= 52, },
356 static const struct {
364 } arm_vfp_v3_regs
[] = {
365 { ARM_VFP_V3_D0
, "d0", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
366 { ARM_VFP_V3_D1
, "d1", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
367 { ARM_VFP_V3_D2
, "d2", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
368 { ARM_VFP_V3_D3
, "d3", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
369 { ARM_VFP_V3_D4
, "d4", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
370 { ARM_VFP_V3_D5
, "d5", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
371 { ARM_VFP_V3_D6
, "d6", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
372 { ARM_VFP_V3_D7
, "d7", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
373 { ARM_VFP_V3_D8
, "d8", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
374 { ARM_VFP_V3_D9
, "d9", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
375 { ARM_VFP_V3_D10
, "d10", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
376 { ARM_VFP_V3_D11
, "d11", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
377 { ARM_VFP_V3_D12
, "d12", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
378 { ARM_VFP_V3_D13
, "d13", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
379 { ARM_VFP_V3_D14
, "d14", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
380 { ARM_VFP_V3_D15
, "d15", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
381 { ARM_VFP_V3_D16
, "d16", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
382 { ARM_VFP_V3_D17
, "d17", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
383 { ARM_VFP_V3_D18
, "d18", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
384 { ARM_VFP_V3_D19
, "d19", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
385 { ARM_VFP_V3_D20
, "d20", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
386 { ARM_VFP_V3_D21
, "d21", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
387 { ARM_VFP_V3_D22
, "d22", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
388 { ARM_VFP_V3_D23
, "d23", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
389 { ARM_VFP_V3_D24
, "d24", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
390 { ARM_VFP_V3_D25
, "d25", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
391 { ARM_VFP_V3_D26
, "d26", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
392 { ARM_VFP_V3_D27
, "d27", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
393 { ARM_VFP_V3_D28
, "d28", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
394 { ARM_VFP_V3_D29
, "d29", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
395 { ARM_VFP_V3_D30
, "d30", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
396 { ARM_VFP_V3_D31
, "d31", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
397 { ARM_VFP_V3_FPSCR
, "fpscr", 32, ARM_MODE_ANY
, REG_TYPE_INT
, "float", "org.gnu.gdb.arm.vfp"},
400 /* map core mode (USR, FIQ, ...) and register number to
401 * indices into the register cache
403 const int armv4_5_core_reg_map
[9][17] = {
405 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
407 { /* FIQ (8 shadows of USR, vs normal 3) */
408 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
411 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
414 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
417 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
420 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
422 { /* SYS (same registers as USR) */
423 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
426 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 39, 40, 15, 41,
429 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 42, 14, 15, 43,
434 * Configures host-side ARM records to reflect the specified CPSR.
435 * Later, code can use arm_reg_current() to map register numbers
436 * according to how they are exposed by this mode.
438 void arm_set_cpsr(struct arm
*arm
, uint32_t cpsr
)
440 enum arm_mode mode
= cpsr
& 0x1f;
443 /* NOTE: this may be called very early, before the register
444 * cache is set up. We can't defend against many errors, in
445 * particular against CPSRs that aren't valid *here* ...
448 buf_set_u32(arm
->cpsr
->value
, 0, 32, cpsr
);
449 arm
->cpsr
->valid
= true;
450 arm
->cpsr
->dirty
= false;
453 arm
->core_mode
= mode
;
455 /* mode_to_number() warned; set up a somewhat-sane mapping */
456 num
= arm_mode_to_number(mode
);
462 arm
->map
= &armv4_5_core_reg_map
[num
][0];
463 arm
->spsr
= (mode
== ARM_MODE_USR
|| mode
== ARM_MODE_SYS
)
465 : arm
->core_cache
->reg_list
+ arm
->map
[16];
467 /* Older ARMs won't have the J bit */
468 enum arm_state state
;
470 if (cpsr
& (1 << 5)) { /* T */
471 if (cpsr
& (1 << 24)) { /* J */
472 LOG_WARNING("ThumbEE -- incomplete support");
473 state
= ARM_STATE_THUMB_EE
;
475 state
= ARM_STATE_THUMB
;
477 if (cpsr
& (1 << 24)) { /* J */
478 LOG_ERROR("Jazelle state handling is BROKEN!");
479 state
= ARM_STATE_JAZELLE
;
481 state
= ARM_STATE_ARM
;
483 arm
->core_state
= state
;
485 LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr
,
487 arm_state_strings
[arm
->core_state
]);
491 * Returns handle to the register currently mapped to a given number.
492 * Someone must have called arm_set_cpsr() before.
494 * \param arm This core's state and registers are used.
495 * \param regnum From 0..15 corresponding to R0..R14 and PC.
496 * Note that R0..R7 don't require mapping; you may access those
497 * as the first eight entries in the register cache. Likewise
498 * R15 (PC) doesn't need mapping; you may also access it directly.
499 * However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
500 * CPSR (arm->cpsr) is also not mapped.
502 struct reg
*arm_reg_current(struct arm
*arm
, unsigned regnum
)
510 LOG_ERROR("Register map is not available yet, the target is not fully initialised");
511 r
= arm
->core_cache
->reg_list
+ regnum
;
513 r
= arm
->core_cache
->reg_list
+ arm
->map
[regnum
];
515 /* e.g. invalid CPSR said "secure monitor" mode on a core
516 * that doesn't support it...
519 LOG_ERROR("Invalid CPSR mode");
520 r
= arm
->core_cache
->reg_list
+ regnum
;
526 static const uint8_t arm_gdb_dummy_fp_value
[12];
528 static struct reg_feature arm_gdb_dummy_fp_features
= {
529 .name
= "net.sourceforge.openocd.fake_fpa"
533 * Dummy FPA registers are required to support GDB on ARM.
534 * Register packets require eight obsolete FPA register values.
535 * Modern ARM cores use Vector Floating Point (VFP), if they
536 * have any floating point support. VFP is not FPA-compatible.
538 static struct reg arm_gdb_dummy_fp_reg
= {
539 .name
= "GDB dummy FPA register",
540 .value
= (uint8_t *) arm_gdb_dummy_fp_value
,
545 .feature
= &arm_gdb_dummy_fp_features
,
549 static const uint8_t arm_gdb_dummy_fps_value
[4];
552 * Dummy FPA status registers are required to support GDB on ARM.
553 * Register packets require an obsolete FPA status register.
555 static struct reg arm_gdb_dummy_fps_reg
= {
556 .name
= "GDB dummy FPA status register",
557 .value
= (uint8_t *) arm_gdb_dummy_fps_value
,
562 .feature
= &arm_gdb_dummy_fp_features
,
566 static void arm_gdb_dummy_init(void) __attribute__ ((constructor
));
568 static void arm_gdb_dummy_init(void)
570 register_init_dummy(&arm_gdb_dummy_fp_reg
);
571 register_init_dummy(&arm_gdb_dummy_fps_reg
);
574 static int armv4_5_get_core_reg(struct reg
*reg
)
577 struct arm_reg
*reg_arch_info
= reg
->arch_info
;
578 struct target
*target
= reg_arch_info
->target
;
580 if (target
->state
!= TARGET_HALTED
) {
581 LOG_TARGET_ERROR(target
, "not halted");
582 return ERROR_TARGET_NOT_HALTED
;
585 retval
= reg_arch_info
->arm
->read_core_reg(target
, reg
,
586 reg_arch_info
->num
, reg_arch_info
->mode
);
587 if (retval
== ERROR_OK
) {
595 static int armv4_5_set_core_reg(struct reg
*reg
, uint8_t *buf
)
597 struct arm_reg
*reg_arch_info
= reg
->arch_info
;
598 struct target
*target
= reg_arch_info
->target
;
599 struct arm
*armv4_5_target
= target_to_arm(target
);
600 uint32_t value
= buf_get_u32(buf
, 0, 32);
602 if (target
->state
!= TARGET_HALTED
) {
603 LOG_TARGET_ERROR(target
, "not halted");
604 return ERROR_TARGET_NOT_HALTED
;
607 /* Except for CPSR, the "reg" command exposes a writeback model
608 * for the register cache.
610 if (reg
== armv4_5_target
->cpsr
) {
611 arm_set_cpsr(armv4_5_target
, value
);
613 /* Older cores need help to be in ARM mode during halt
614 * mode debug, so we clear the J and T bits if we flush.
615 * For newer cores (v6/v7a/v7r) we don't need that, but
616 * it won't hurt since CPSR is always flushed anyway.
618 if (armv4_5_target
->core_mode
!=
619 (enum arm_mode
)(value
& 0x1f)) {
620 LOG_DEBUG("changing ARM core mode to '%s'",
621 arm_mode_name(value
& 0x1f));
622 value
&= ~((1 << 24) | (1 << 5));
624 buf_set_u32(t
, 0, 32, value
);
625 armv4_5_target
->write_core_reg(target
, reg
,
626 16, ARM_MODE_ANY
, t
);
629 buf_set_u32(reg
->value
, 0, 32, value
);
630 if (reg
->size
== 64) {
631 value
= buf_get_u32(buf
+ 4, 0, 32);
632 buf_set_u32(reg
->value
+ 4, 0, 32, value
);
641 static const struct reg_arch_type arm_reg_type
= {
642 .get
= armv4_5_get_core_reg
,
643 .set
= armv4_5_set_core_reg
,
646 struct reg_cache
*arm_build_reg_cache(struct target
*target
, struct arm
*arm
)
648 int num_regs
= ARRAY_SIZE(arm_core_regs
);
649 int num_core_regs
= num_regs
;
650 if (arm
->arm_vfp_version
== ARM_VFP_V3
)
651 num_regs
+= ARRAY_SIZE(arm_vfp_v3_regs
);
653 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
654 struct reg
*reg_list
= calloc(num_regs
, sizeof(struct reg
));
655 struct arm_reg
*reg_arch_info
= calloc(num_regs
, sizeof(struct arm_reg
));
658 if (!cache
|| !reg_list
|| !reg_arch_info
) {
665 cache
->name
= "ARM registers";
667 cache
->reg_list
= reg_list
;
670 for (i
= 0; i
< num_core_regs
; i
++) {
671 /* Skip registers this core doesn't expose */
672 if (arm_core_regs
[i
].mode
== ARM_MODE_MON
673 && arm
->core_type
!= ARM_CORE_TYPE_SEC_EXT
674 && arm
->core_type
!= ARM_CORE_TYPE_VIRT_EXT
)
676 if (arm_core_regs
[i
].mode
== ARM_MODE_HYP
677 && arm
->core_type
!= ARM_CORE_TYPE_VIRT_EXT
)
680 /* REVISIT handle Cortex-M, which only shadows R13/SP */
682 reg_arch_info
[i
].num
= arm_core_regs
[i
].cookie
;
683 reg_arch_info
[i
].mode
= arm_core_regs
[i
].mode
;
684 reg_arch_info
[i
].target
= target
;
685 reg_arch_info
[i
].arm
= arm
;
687 reg_list
[i
].name
= arm_core_regs
[i
].name
;
688 reg_list
[i
].number
= arm_core_regs
[i
].gdb_index
;
689 reg_list
[i
].size
= 32;
690 reg_list
[i
].value
= reg_arch_info
[i
].value
;
691 reg_list
[i
].type
= &arm_reg_type
;
692 reg_list
[i
].arch_info
= ®_arch_info
[i
];
693 reg_list
[i
].exist
= true;
695 /* This really depends on the calling convention in use */
696 reg_list
[i
].caller_save
= false;
698 /* Registers data type, as used by GDB target description */
699 reg_list
[i
].reg_data_type
= malloc(sizeof(struct reg_data_type
));
700 switch (arm_core_regs
[i
].cookie
) {
702 reg_list
[i
].reg_data_type
->type
= REG_TYPE_DATA_PTR
;
706 reg_list
[i
].reg_data_type
->type
= REG_TYPE_CODE_PTR
;
709 reg_list
[i
].reg_data_type
->type
= REG_TYPE_UINT32
;
713 /* let GDB shows banked registers only in "info all-reg" */
714 reg_list
[i
].feature
= malloc(sizeof(struct reg_feature
));
715 if (reg_list
[i
].number
<= 15 || reg_list
[i
].number
== 25) {
716 reg_list
[i
].feature
->name
= "org.gnu.gdb.arm.core";
717 reg_list
[i
].group
= "general";
719 reg_list
[i
].feature
->name
= "net.sourceforge.openocd.banked";
720 reg_list
[i
].group
= "banked";
727 for (i
= num_core_regs
, j
= 0; i
< num_regs
; i
++, j
++) {
728 reg_arch_info
[i
].num
= arm_vfp_v3_regs
[j
].id
;
729 reg_arch_info
[i
].mode
= arm_vfp_v3_regs
[j
].mode
;
730 reg_arch_info
[i
].target
= target
;
731 reg_arch_info
[i
].arm
= arm
;
733 reg_list
[i
].name
= arm_vfp_v3_regs
[j
].name
;
734 reg_list
[i
].number
= arm_vfp_v3_regs
[j
].id
;
735 reg_list
[i
].size
= arm_vfp_v3_regs
[j
].bits
;
736 reg_list
[i
].value
= reg_arch_info
[i
].value
;
737 reg_list
[i
].type
= &arm_reg_type
;
738 reg_list
[i
].arch_info
= ®_arch_info
[i
];
739 reg_list
[i
].exist
= true;
741 reg_list
[i
].caller_save
= false;
743 reg_list
[i
].reg_data_type
= malloc(sizeof(struct reg_data_type
));
744 reg_list
[i
].reg_data_type
->type
= arm_vfp_v3_regs
[j
].type
;
746 reg_list
[i
].feature
= malloc(sizeof(struct reg_feature
));
747 reg_list
[i
].feature
->name
= arm_vfp_v3_regs
[j
].feature
;
749 reg_list
[i
].group
= arm_vfp_v3_regs
[j
].group
;
754 arm
->pc
= reg_list
+ 15;
755 arm
->cpsr
= reg_list
+ ARMV4_5_CPSR
;
756 arm
->core_cache
= cache
;
761 void arm_free_reg_cache(struct arm
*arm
)
763 if (!arm
|| !arm
->core_cache
)
766 struct reg_cache
*cache
= arm
->core_cache
;
768 for (unsigned int i
= 0; i
< cache
->num_regs
; i
++) {
769 struct reg
*reg
= &cache
->reg_list
[i
];
772 free(reg
->reg_data_type
);
775 free(cache
->reg_list
[0].arch_info
);
776 free(cache
->reg_list
);
779 arm
->core_cache
= NULL
;
782 int arm_arch_state(struct target
*target
)
784 struct arm
*arm
= target_to_arm(target
);
786 if (arm
->common_magic
!= ARM_COMMON_MAGIC
) {
787 LOG_ERROR("BUG: called for a non-ARM target");
791 /* avoid filling log waiting for fileio reply */
792 if (target
->semihosting
&& target
->semihosting
->hit_fileio
)
795 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
796 "cpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"%s%s",
797 arm_state_strings
[arm
->core_state
],
798 debug_reason_name(target
),
799 arm_mode_name(arm
->core_mode
),
800 buf_get_u32(arm
->cpsr
->value
, 0, 32),
801 buf_get_u32(arm
->pc
->value
, 0, 32),
802 (target
->semihosting
&& target
->semihosting
->is_active
) ? ", semihosting" : "",
803 (target
->semihosting
&& target
->semihosting
->is_fileio
) ? " fileio" : "");
808 COMMAND_HANDLER(handle_armv4_5_reg_command
)
810 struct target
*target
= get_current_target(CMD_CTX
);
811 struct arm
*arm
= target_to_arm(target
);
815 command_print(CMD
, "current target isn't an ARM");
819 if (target
->state
!= TARGET_HALTED
) {
820 command_print(CMD
, "Error: target must be halted for register accesses");
821 return ERROR_TARGET_NOT_HALTED
;
824 if (arm
->core_type
!= ARM_CORE_TYPE_STD
) {
826 "Microcontroller Profile not supported - use standard reg cmd");
830 if (!is_arm_mode(arm
->core_mode
)) {
831 LOG_ERROR("not a valid arm core mode - communication failure?");
835 if (!arm
->full_context
) {
836 command_print(CMD
, "Error: target doesn't support %s",
841 regs
= arm
->core_cache
->reg_list
;
843 for (unsigned mode
= 0; mode
< ARRAY_SIZE(arm_mode_data
); mode
++) {
848 if (!arm_mode_data
[mode
].n_indices
)
851 /* label this bank of registers (or shadows) */
852 switch (arm_mode_data
[mode
].psr
) {
856 name
= "System and User";
860 if (arm
->core_type
!= ARM_CORE_TYPE_VIRT_EXT
)
864 case ARM_MODE_1176_MON
:
865 if (arm
->core_type
!= ARM_CORE_TYPE_SEC_EXT
866 && arm
->core_type
!= ARM_CORE_TYPE_VIRT_EXT
)
870 name
= arm_mode_data
[mode
].name
;
874 command_print(CMD
, "%s%s mode %sregisters",
877 /* display N rows of up to 4 registers each */
878 for (unsigned i
= 0; i
< arm_mode_data
[mode
].n_indices
; ) {
882 for (unsigned j
= 0; j
< 4; j
++, i
++) {
884 struct reg
*reg
= regs
;
886 if (i
>= arm_mode_data
[mode
].n_indices
)
889 reg
+= arm_mode_data
[mode
].indices
[i
];
891 /* REVISIT be smarter about faults... */
893 arm
->full_context(target
);
895 value
= buf_get_u32(reg
->value
, 0, 32);
896 output_len
+= snprintf(output
+ output_len
,
897 sizeof(output
) - output_len
,
898 "%8s: %8.8" PRIx32
" ",
901 command_print(CMD
, "%s", output
);
908 COMMAND_HANDLER(handle_arm_core_state_command
)
910 struct target
*target
= get_current_target(CMD_CTX
);
911 struct arm
*arm
= target_to_arm(target
);
915 command_print(CMD
, "current target isn't an ARM");
920 if (strcmp(CMD_ARGV
[0], "arm") == 0) {
921 if (arm
->core_type
== ARM_CORE_TYPE_M_PROFILE
) {
922 command_print(CMD
, "arm mode not supported on Cortex-M");
925 arm
->core_state
= ARM_STATE_ARM
;
928 if (strcmp(CMD_ARGV
[0], "thumb") == 0)
929 arm
->core_state
= ARM_STATE_THUMB
;
932 command_print(CMD
, "core state: %s", arm_state_strings
[arm
->core_state
]);
937 COMMAND_HANDLER(handle_arm_disassemble_command
)
940 struct target
*target
= get_current_target(CMD_CTX
);
943 LOG_ERROR("No target selected");
947 struct arm
*arm
= target_to_arm(target
);
948 target_addr_t address
;
949 unsigned int count
= 1;
953 command_print(CMD
, "current target isn't an ARM");
957 if (arm
->core_type
== ARM_CORE_TYPE_M_PROFILE
) {
958 /* armv7m is always thumb mode */
964 if (strcmp(CMD_ARGV
[2], "thumb") != 0)
965 return ERROR_COMMAND_SYNTAX_ERROR
;
969 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[1], count
);
972 COMMAND_PARSE_ADDRESS(CMD_ARGV
[0], address
);
973 if (address
& 0x01) {
975 command_print(CMD
, "Disassemble as Thumb");
982 return ERROR_COMMAND_SYNTAX_ERROR
;
985 return arm_disassemble(CMD
, target
, address
, count
, thumb
);
987 command_print(CMD
, "capstone disassembly framework required");
992 COMMAND_HANDLER(handle_armv4_5_mcrmrc
)
995 unsigned int arg_cnt
= 5;
997 if (!strcmp(CMD_NAME
, "mcr")) {
1002 if (arg_cnt
!= CMD_ARGC
)
1003 return ERROR_COMMAND_SYNTAX_ERROR
;
1005 struct target
*target
= get_current_target(CMD_CTX
);
1007 command_print(CMD
, "no current target");
1010 if (!target_was_examined(target
)) {
1011 command_print(CMD
, "%s: not yet examined", target_name(target
));
1012 return ERROR_TARGET_NOT_EXAMINED
;
1015 struct arm
*arm
= target_to_arm(target
);
1017 command_print(CMD
, "%s: not an ARM", target_name(target
));
1021 if (target
->state
!= TARGET_HALTED
) {
1022 command_print(CMD
, "Error: [%s] not halted", target_name(target
));
1023 return ERROR_TARGET_NOT_HALTED
;
1033 /* NOTE: parameter sequence matches ARM instruction set usage:
1034 * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
1035 * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
1036 * The "rX" is necessarily omitted; it uses Tcl mechanisms.
1038 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], cpnum
);
1040 command_print(CMD
, "coprocessor %d out of range", cpnum
);
1041 return ERROR_COMMAND_ARGUMENT_INVALID
;
1044 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], op1
);
1046 command_print(CMD
, "op1 %d out of range", op1
);
1047 return ERROR_COMMAND_ARGUMENT_INVALID
;
1050 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], crn
);
1052 command_print(CMD
, "CRn %d out of range", crn
);
1053 return ERROR_COMMAND_ARGUMENT_INVALID
;
1056 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[3], crm
);
1058 command_print(CMD
, "CRm %d out of range", crm
);
1059 return ERROR_COMMAND_ARGUMENT_INVALID
;
1062 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[4], op2
);
1064 command_print(CMD
, "op2 %d out of range", op2
);
1065 return ERROR_COMMAND_ARGUMENT_INVALID
;
1069 * FIXME change the call syntax here ... simplest to just pass
1070 * the MRC() or MCR() instruction to be executed. That will also
1071 * let us support the "mrc2" and "mcr2" opcodes (toggling one bit)
1072 * if that's ever needed.
1075 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[5], value
);
1077 /* NOTE: parameters reordered! */
1078 /* ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2) */
1079 int retval
= arm
->mcr(target
, cpnum
, op1
, op2
, crn
, crm
, value
);
1080 if (retval
!= ERROR_OK
)
1084 /* NOTE: parameters reordered! */
1085 /* ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2) */
1086 int retval
= arm
->mrc(target
, cpnum
, op1
, op2
, crn
, crm
, &value
);
1087 if (retval
!= ERROR_OK
)
1090 command_print(CMD
, "0x%" PRIx32
, value
);
1096 static const struct command_registration arm_exec_command_handlers
[] = {
1099 .handler
= handle_armv4_5_reg_command
,
1100 .mode
= COMMAND_EXEC
,
1101 .help
= "display ARM core registers",
1106 .mode
= COMMAND_EXEC
,
1107 .handler
= handle_armv4_5_mcrmrc
,
1108 .help
= "write coprocessor register",
1109 .usage
= "cpnum op1 CRn CRm op2 value",
1113 .mode
= COMMAND_EXEC
,
1114 .handler
= handle_armv4_5_mcrmrc
,
1115 .help
= "read coprocessor register",
1116 .usage
= "cpnum op1 CRn CRm op2",
1119 .chain
= arm_all_profiles_command_handlers
,
1121 COMMAND_REGISTRATION_DONE
1124 const struct command_registration arm_all_profiles_command_handlers
[] = {
1126 .name
= "core_state",
1127 .handler
= handle_arm_core_state_command
,
1128 .mode
= COMMAND_EXEC
,
1129 .usage
= "['arm'|'thumb']",
1130 .help
= "display/change ARM core state",
1133 .name
= "disassemble",
1134 .handler
= handle_arm_disassemble_command
,
1135 .mode
= COMMAND_EXEC
,
1136 .usage
= "address [count ['thumb']]",
1137 .help
= "disassemble instructions",
1140 .chain
= semihosting_common_handlers
,
1142 COMMAND_REGISTRATION_DONE
1145 const struct command_registration arm_command_handlers
[] = {
1148 .mode
= COMMAND_ANY
,
1149 .help
= "ARM command group",
1151 .chain
= arm_exec_command_handlers
,
1153 COMMAND_REGISTRATION_DONE
1157 * gdb for arm targets (e.g. arm-none-eabi-gdb) supports several variants
1158 * of arm architecture. You can list them using the autocompletion of gdb
1159 * command prompt by typing "set architecture " and then press TAB key.
1160 * The default, selected automatically, is "arm".
1161 * Let's use the default value, here, to make gdb-multiarch behave in the
1162 * same way as a gdb for arm. This can be changed later on. User can still
1163 * set the specific architecture variant with the gdb command.
1165 const char *arm_get_gdb_arch(struct target
*target
)
1170 int arm_get_gdb_reg_list(struct target
*target
,
1171 struct reg
**reg_list
[], int *reg_list_size
,
1172 enum target_register_class reg_class
)
1174 struct arm
*arm
= target_to_arm(target
);
1177 if (!is_arm_mode(arm
->core_mode
)) {
1178 LOG_ERROR("not a valid arm core mode - communication failure?");
1182 switch (reg_class
) {
1183 case REG_CLASS_GENERAL
:
1184 *reg_list_size
= 26;
1185 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
1187 for (i
= 0; i
< 16; i
++)
1188 (*reg_list
)[i
] = arm_reg_current(arm
, i
);
1190 /* For GDB compatibility, take FPA registers size into account and zero-fill it*/
1191 for (i
= 16; i
< 24; i
++)
1192 (*reg_list
)[i
] = &arm_gdb_dummy_fp_reg
;
1193 (*reg_list
)[24] = &arm_gdb_dummy_fps_reg
;
1195 (*reg_list
)[25] = arm
->cpsr
;
1200 switch (arm
->core_type
) {
1201 case ARM_CORE_TYPE_SEC_EXT
:
1202 *reg_list_size
= 51;
1204 case ARM_CORE_TYPE_VIRT_EXT
:
1205 *reg_list_size
= 53;
1208 *reg_list_size
= 48;
1210 unsigned int list_size_core
= *reg_list_size
;
1211 if (arm
->arm_vfp_version
== ARM_VFP_V3
)
1212 *reg_list_size
+= 33;
1214 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
1216 for (i
= 0; i
< 16; i
++)
1217 (*reg_list
)[i
] = arm_reg_current(arm
, i
);
1219 for (i
= 13; i
< ARRAY_SIZE(arm_core_regs
); i
++) {
1220 int reg_index
= arm
->core_cache
->reg_list
[i
].number
;
1222 if (arm_core_regs
[i
].mode
== ARM_MODE_MON
1223 && arm
->core_type
!= ARM_CORE_TYPE_SEC_EXT
1224 && arm
->core_type
!= ARM_CORE_TYPE_VIRT_EXT
)
1226 if (arm_core_regs
[i
].mode
== ARM_MODE_HYP
1227 && arm
->core_type
!= ARM_CORE_TYPE_VIRT_EXT
)
1229 (*reg_list
)[reg_index
] = &(arm
->core_cache
->reg_list
[i
]);
1232 /* When we supply the target description, there is no need for fake FPA */
1233 for (i
= 16; i
< 24; i
++) {
1234 (*reg_list
)[i
] = &arm_gdb_dummy_fp_reg
;
1235 (*reg_list
)[i
]->size
= 0;
1237 (*reg_list
)[24] = &arm_gdb_dummy_fps_reg
;
1238 (*reg_list
)[24]->size
= 0;
1240 if (arm
->arm_vfp_version
== ARM_VFP_V3
) {
1241 unsigned int num_core_regs
= ARRAY_SIZE(arm_core_regs
);
1242 for (i
= 0; i
< 33; i
++)
1243 (*reg_list
)[list_size_core
+ i
] = &(arm
->core_cache
->reg_list
[num_core_regs
+ i
]);
1249 LOG_ERROR("not a valid register class type in query.");
1254 /* wait for execution to complete and check exit point */
1255 static int armv4_5_run_algorithm_completion(struct target
*target
,
1256 uint32_t exit_point
,
1257 unsigned int timeout_ms
,
1261 struct arm
*arm
= target_to_arm(target
);
1263 retval
= target_wait_state(target
, TARGET_HALTED
, timeout_ms
);
1264 if (retval
!= ERROR_OK
)
1266 if (target
->state
!= TARGET_HALTED
) {
1267 retval
= target_halt(target
);
1268 if (retval
!= ERROR_OK
)
1270 retval
= target_wait_state(target
, TARGET_HALTED
, 500);
1271 if (retval
!= ERROR_OK
)
1273 return ERROR_TARGET_TIMEOUT
;
1276 /* fast exit: ARMv5+ code can use BKPT */
1277 if (exit_point
&& buf_get_u32(arm
->pc
->value
, 0, 32) != exit_point
) {
1279 "target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32
"",
1280 buf_get_u32(arm
->pc
->value
, 0, 32));
1281 return ERROR_TARGET_TIMEOUT
;
1287 int armv4_5_run_algorithm_inner(struct target
*target
,
1288 int num_mem_params
, struct mem_param
*mem_params
,
1289 int num_reg_params
, struct reg_param
*reg_params
,
1290 uint32_t entry_point
, uint32_t exit_point
,
1291 unsigned int timeout_ms
, void *arch_info
,
1292 int (*run_it
)(struct target
*target
, uint32_t exit_point
,
1293 unsigned int timeout_ms
, void *arch_info
))
1295 struct arm
*arm
= target_to_arm(target
);
1296 struct arm_algorithm
*arm_algorithm_info
= arch_info
;
1297 enum arm_state core_state
= arm
->core_state
;
1298 uint32_t context
[17];
1300 int exit_breakpoint_size
= 0;
1302 int retval
= ERROR_OK
;
1304 LOG_DEBUG("Running algorithm");
1306 if (arm_algorithm_info
->common_magic
!= ARM_COMMON_MAGIC
) {
1307 LOG_ERROR("current target isn't an ARMV4/5 target");
1308 return ERROR_TARGET_INVALID
;
1311 if (target
->state
!= TARGET_HALTED
) {
1312 LOG_TARGET_ERROR(target
, "not halted (run target algo)");
1313 return ERROR_TARGET_NOT_HALTED
;
1316 if (!is_arm_mode(arm
->core_mode
)) {
1317 LOG_ERROR("not a valid arm core mode - communication failure?");
1321 /* armv5 and later can terminate with BKPT instruction; less overhead */
1322 if (!exit_point
&& arm
->arch
== ARM_ARCH_V4
) {
1323 LOG_ERROR("ARMv4 target needs HW breakpoint location");
1327 /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
1328 * they'll be restored later.
1330 for (i
= 0; i
<= 16; i
++) {
1333 r
= &ARMV4_5_CORE_REG_MODE(arm
->core_cache
,
1334 arm_algorithm_info
->core_mode
, i
);
1336 arm
->read_core_reg(target
, r
, i
,
1337 arm_algorithm_info
->core_mode
);
1338 context
[i
] = buf_get_u32(r
->value
, 0, 32);
1340 cpsr
= buf_get_u32(arm
->cpsr
->value
, 0, 32);
1342 for (i
= 0; i
< num_mem_params
; i
++) {
1343 if (mem_params
[i
].direction
== PARAM_IN
)
1345 retval
= target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
,
1346 mem_params
[i
].value
);
1347 if (retval
!= ERROR_OK
)
1351 for (i
= 0; i
< num_reg_params
; i
++) {
1352 if (reg_params
[i
].direction
== PARAM_IN
)
1355 struct reg
*reg
= register_get_by_name(arm
->core_cache
, reg_params
[i
].reg_name
, false);
1357 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1358 return ERROR_COMMAND_SYNTAX_ERROR
;
1361 if (reg
->size
!= reg_params
[i
].size
) {
1362 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
1363 reg_params
[i
].reg_name
);
1364 return ERROR_COMMAND_SYNTAX_ERROR
;
1367 retval
= armv4_5_set_core_reg(reg
, reg_params
[i
].value
);
1368 if (retval
!= ERROR_OK
)
1372 arm
->core_state
= arm_algorithm_info
->core_state
;
1373 if (arm
->core_state
== ARM_STATE_ARM
)
1374 exit_breakpoint_size
= 4;
1375 else if (arm
->core_state
== ARM_STATE_THUMB
)
1376 exit_breakpoint_size
= 2;
1378 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1379 return ERROR_COMMAND_SYNTAX_ERROR
;
1382 if (arm_algorithm_info
->core_mode
!= ARM_MODE_ANY
) {
1383 LOG_DEBUG("setting core_mode: 0x%2.2x",
1384 arm_algorithm_info
->core_mode
);
1385 buf_set_u32(arm
->cpsr
->value
, 0, 5,
1386 arm_algorithm_info
->core_mode
);
1387 arm
->cpsr
->dirty
= true;
1388 arm
->cpsr
->valid
= true;
1391 /* terminate using a hardware or (ARMv5+) software breakpoint */
1393 retval
= breakpoint_add(target
, exit_point
,
1394 exit_breakpoint_size
, BKPT_HARD
);
1395 if (retval
!= ERROR_OK
) {
1396 LOG_ERROR("can't add HW breakpoint to terminate algorithm");
1397 return ERROR_TARGET_FAILURE
;
1401 retval
= target_resume(target
, 0, entry_point
, 1, 1);
1402 if (retval
!= ERROR_OK
)
1404 retval
= run_it(target
, exit_point
, timeout_ms
, arch_info
);
1407 breakpoint_remove(target
, exit_point
);
1409 if (retval
!= ERROR_OK
)
1412 for (i
= 0; i
< num_mem_params
; i
++) {
1413 if (mem_params
[i
].direction
!= PARAM_OUT
) {
1414 int retvaltemp
= target_read_buffer(target
, mem_params
[i
].address
,
1416 mem_params
[i
].value
);
1417 if (retvaltemp
!= ERROR_OK
)
1418 retval
= retvaltemp
;
1422 for (i
= 0; i
< num_reg_params
; i
++) {
1423 if (reg_params
[i
].direction
!= PARAM_OUT
) {
1425 struct reg
*reg
= register_get_by_name(arm
->core_cache
,
1426 reg_params
[i
].reg_name
,
1429 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1430 retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1434 if (reg
->size
!= reg_params
[i
].size
) {
1436 "BUG: register '%s' size doesn't match reg_params[i].size",
1437 reg_params
[i
].reg_name
);
1438 retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1442 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
1446 /* restore everything we saved before (17 or 18 registers) */
1447 for (i
= 0; i
<= 16; i
++) {
1449 regvalue
= buf_get_u32(ARMV4_5_CORE_REG_MODE(arm
->core_cache
,
1450 arm_algorithm_info
->core_mode
, i
).value
, 0, 32);
1451 if (regvalue
!= context
[i
]) {
1452 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32
"",
1453 ARMV4_5_CORE_REG_MODE(arm
->core_cache
,
1454 arm_algorithm_info
->core_mode
, i
).name
, context
[i
]);
1455 buf_set_u32(ARMV4_5_CORE_REG_MODE(arm
->core_cache
,
1456 arm_algorithm_info
->core_mode
, i
).value
, 0, 32, context
[i
]);
1457 ARMV4_5_CORE_REG_MODE(arm
->core_cache
, arm_algorithm_info
->core_mode
,
1459 ARMV4_5_CORE_REG_MODE(arm
->core_cache
, arm_algorithm_info
->core_mode
,
1464 arm_set_cpsr(arm
, cpsr
);
1465 arm
->cpsr
->dirty
= true;
1467 arm
->core_state
= core_state
;
1472 int armv4_5_run_algorithm(struct target
*target
,
1474 struct mem_param
*mem_params
,
1476 struct reg_param
*reg_params
,
1477 target_addr_t entry_point
,
1478 target_addr_t exit_point
,
1479 unsigned int timeout_ms
,
1482 return armv4_5_run_algorithm_inner(target
,
1487 (uint32_t)entry_point
,
1488 (uint32_t)exit_point
,
1491 armv4_5_run_algorithm_completion
);
1495 * Runs ARM code in the target to calculate a CRC32 checksum.
1498 int arm_checksum_memory(struct target
*target
,
1499 target_addr_t address
, uint32_t count
, uint32_t *checksum
)
1501 struct working_area
*crc_algorithm
;
1502 struct arm_algorithm arm_algo
;
1503 struct arm
*arm
= target_to_arm(target
);
1504 struct reg_param reg_params
[2];
1507 uint32_t exit_var
= 0;
1509 static const uint8_t arm_crc_code_le
[] = {
1510 #include "../../contrib/loaders/checksum/armv4_5_crc.inc"
1513 assert(sizeof(arm_crc_code_le
) % 4 == 0);
1515 retval
= target_alloc_working_area(target
,
1516 sizeof(arm_crc_code_le
), &crc_algorithm
);
1517 if (retval
!= ERROR_OK
)
1520 /* convert code into a buffer in target endianness */
1521 for (i
= 0; i
< ARRAY_SIZE(arm_crc_code_le
) / 4; i
++) {
1522 retval
= target_write_u32(target
,
1523 crc_algorithm
->address
+ i
* sizeof(uint32_t),
1524 le_to_h_u32(&arm_crc_code_le
[i
* 4]));
1525 if (retval
!= ERROR_OK
)
1529 arm_algo
.common_magic
= ARM_COMMON_MAGIC
;
1530 arm_algo
.core_mode
= ARM_MODE_SVC
;
1531 arm_algo
.core_state
= ARM_STATE_ARM
;
1533 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
);
1534 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1536 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
1537 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
1539 /* 20 second timeout/megabyte */
1540 unsigned int timeout
= 20000 * (1 + (count
/ (1024 * 1024)));
1542 /* armv4 must exit using a hardware breakpoint */
1543 if (arm
->arch
== ARM_ARCH_V4
)
1544 exit_var
= crc_algorithm
->address
+ sizeof(arm_crc_code_le
) - 8;
1546 retval
= target_run_algorithm(target
, 0, NULL
, 2, reg_params
,
1547 crc_algorithm
->address
,
1549 timeout
, &arm_algo
);
1551 if (retval
== ERROR_OK
)
1552 *checksum
= buf_get_u32(reg_params
[0].value
, 0, 32);
1554 LOG_ERROR("error executing ARM crc algorithm");
1556 destroy_reg_param(®_params
[0]);
1557 destroy_reg_param(®_params
[1]);
1560 target_free_working_area(target
, crc_algorithm
);
1566 * Runs ARM code in the target to check whether a memory block holds
1567 * all ones. NOR flash which has been erased, and thus may be written,
1571 int arm_blank_check_memory(struct target
*target
,
1572 struct target_memory_check_block
*blocks
, int num_blocks
, uint8_t erased_value
)
1574 struct working_area
*check_algorithm
;
1575 struct reg_param reg_params
[3];
1576 struct arm_algorithm arm_algo
;
1577 struct arm
*arm
= target_to_arm(target
);
1580 uint32_t exit_var
= 0;
1582 static const uint8_t check_code_le
[] = {
1583 #include "../../contrib/loaders/erase_check/armv4_5_erase_check.inc"
1586 assert(sizeof(check_code_le
) % 4 == 0);
1588 if (erased_value
!= 0xff) {
1589 LOG_ERROR("Erase value 0x%02" PRIx8
" not yet supported for ARMv4/v5 targets",
1594 /* make sure we have a working area */
1595 retval
= target_alloc_working_area(target
,
1596 sizeof(check_code_le
), &check_algorithm
);
1597 if (retval
!= ERROR_OK
)
1600 /* convert code into a buffer in target endianness */
1601 for (i
= 0; i
< ARRAY_SIZE(check_code_le
) / 4; i
++) {
1602 retval
= target_write_u32(target
,
1603 check_algorithm
->address
1604 + i
* sizeof(uint32_t),
1605 le_to_h_u32(&check_code_le
[i
* 4]));
1606 if (retval
!= ERROR_OK
)
1610 arm_algo
.common_magic
= ARM_COMMON_MAGIC
;
1611 arm_algo
.core_mode
= ARM_MODE_SVC
;
1612 arm_algo
.core_state
= ARM_STATE_ARM
;
1614 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1615 buf_set_u32(reg_params
[0].value
, 0, 32, blocks
[0].address
);
1617 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1618 buf_set_u32(reg_params
[1].value
, 0, 32, blocks
[0].size
);
1620 init_reg_param(®_params
[2], "r2", 32, PARAM_IN_OUT
);
1621 buf_set_u32(reg_params
[2].value
, 0, 32, erased_value
);
1623 /* armv4 must exit using a hardware breakpoint */
1624 if (arm
->arch
== ARM_ARCH_V4
)
1625 exit_var
= check_algorithm
->address
+ sizeof(check_code_le
) - 4;
1627 retval
= target_run_algorithm(target
, 0, NULL
, 3, reg_params
,
1628 check_algorithm
->address
,
1632 if (retval
== ERROR_OK
)
1633 blocks
[0].result
= buf_get_u32(reg_params
[2].value
, 0, 32);
1635 destroy_reg_param(®_params
[0]);
1636 destroy_reg_param(®_params
[1]);
1637 destroy_reg_param(®_params
[2]);
1640 target_free_working_area(target
, check_algorithm
);
1642 if (retval
!= ERROR_OK
)
1645 return 1; /* only one block has been checked */
1648 static int arm_full_context(struct target
*target
)
1650 struct arm
*arm
= target_to_arm(target
);
1651 unsigned num_regs
= arm
->core_cache
->num_regs
;
1652 struct reg
*reg
= arm
->core_cache
->reg_list
;
1653 int retval
= ERROR_OK
;
1655 for (; num_regs
&& retval
== ERROR_OK
; num_regs
--, reg
++) {
1656 if (!reg
->exist
|| reg
->valid
)
1658 retval
= armv4_5_get_core_reg(reg
);
1663 static int arm_default_mrc(struct target
*target
, int cpnum
,
1664 uint32_t op1
, uint32_t op2
,
1665 uint32_t crn
, uint32_t crm
,
1668 LOG_ERROR("%s doesn't implement MRC", target_type_name(target
));
1672 static int arm_default_mcr(struct target
*target
, int cpnum
,
1673 uint32_t op1
, uint32_t op2
,
1674 uint32_t crn
, uint32_t crm
,
1677 LOG_ERROR("%s doesn't implement MCR", target_type_name(target
));
1681 int arm_init_arch_info(struct target
*target
, struct arm
*arm
)
1683 target
->arch_info
= arm
;
1684 arm
->target
= target
;
1686 arm
->common_magic
= ARM_COMMON_MAGIC
;
1688 /* core_type may be overridden by subtype logic */
1689 if (arm
->core_type
!= ARM_CORE_TYPE_M_PROFILE
) {
1690 arm
->core_type
= ARM_CORE_TYPE_STD
;
1691 arm_set_cpsr(arm
, ARM_MODE_USR
);
1694 /* default full_context() has no core-specific optimizations */
1695 if (!arm
->full_context
&& arm
->read_core_reg
)
1696 arm
->full_context
= arm_full_context
;
1699 arm
->mrc
= arm_default_mrc
;
1701 arm
->mcr
= arm_default_mcr
;
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