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[openocd.git] / src / target / armv4_5.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2008 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifdef HAVE_CONFIG_H
27 #include "config.h"
28 #endif
29
30 #include "replacements.h"
31
32 #include "arm_disassembler.h"
33
34 #include "armv4_5.h"
35
36 #include "target.h"
37 #include "register.h"
38 #include "log.h"
39 #include "binarybuffer.h"
40 #include "command.h"
41
42 #include <stdlib.h>
43 #include <string.h>
44 #include <unistd.h>
45
46 bitfield_desc_t armv4_5_psr_bitfield_desc[] =
47 {
48 {"M[4:0]", 5},
49 {"T", 1},
50 {"F", 1},
51 {"I", 1},
52 {"reserved", 16},
53 {"J", 1},
54 {"reserved", 2},
55 {"Q", 1},
56 {"V", 1},
57 {"C", 1},
58 {"Z", 1},
59 {"N", 1},
60 };
61
62 char* armv4_5_core_reg_list[] =
63 {
64 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
65
66 "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "r13_fiq", "lr_fiq",
67
68 "r13_irq", "lr_irq",
69
70 "r13_svc", "lr_svc",
71
72 "r13_abt", "lr_abt",
73
74 "r13_und", "lr_und",
75
76 "cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und"
77 };
78
79 char * armv4_5_mode_strings_list[] =
80 {
81 "Illegal mode value", "User", "FIQ", "IRQ", "Supervisor", "Abort", "Undefined", "System"
82 };
83
84 /* Hack! Yuk! allow -1 index, which simplifies codepaths elsewhere in the code */
85 char** armv4_5_mode_strings = armv4_5_mode_strings_list+1;
86
87 char* armv4_5_state_strings[] =
88 {
89 "ARM", "Thumb", "Jazelle"
90 };
91
92 int armv4_5_core_reg_arch_type = -1;
93
94 armv4_5_core_reg_t armv4_5_core_reg_list_arch_info[] =
95 {
96 {0, ARMV4_5_MODE_ANY, NULL, NULL},
97 {1, ARMV4_5_MODE_ANY, NULL, NULL},
98 {2, ARMV4_5_MODE_ANY, NULL, NULL},
99 {3, ARMV4_5_MODE_ANY, NULL, NULL},
100 {4, ARMV4_5_MODE_ANY, NULL, NULL},
101 {5, ARMV4_5_MODE_ANY, NULL, NULL},
102 {6, ARMV4_5_MODE_ANY, NULL, NULL},
103 {7, ARMV4_5_MODE_ANY, NULL, NULL},
104 {8, ARMV4_5_MODE_ANY, NULL, NULL},
105 {9, ARMV4_5_MODE_ANY, NULL, NULL},
106 {10, ARMV4_5_MODE_ANY, NULL, NULL},
107 {11, ARMV4_5_MODE_ANY, NULL, NULL},
108 {12, ARMV4_5_MODE_ANY, NULL, NULL},
109 {13, ARMV4_5_MODE_USR, NULL, NULL},
110 {14, ARMV4_5_MODE_USR, NULL, NULL},
111 {15, ARMV4_5_MODE_ANY, NULL, NULL},
112
113 {8, ARMV4_5_MODE_FIQ, NULL, NULL},
114 {9, ARMV4_5_MODE_FIQ, NULL, NULL},
115 {10, ARMV4_5_MODE_FIQ, NULL, NULL},
116 {11, ARMV4_5_MODE_FIQ, NULL, NULL},
117 {12, ARMV4_5_MODE_FIQ, NULL, NULL},
118 {13, ARMV4_5_MODE_FIQ, NULL, NULL},
119 {14, ARMV4_5_MODE_FIQ, NULL, NULL},
120
121 {13, ARMV4_5_MODE_IRQ, NULL, NULL},
122 {14, ARMV4_5_MODE_IRQ, NULL, NULL},
123
124 {13, ARMV4_5_MODE_SVC, NULL, NULL},
125 {14, ARMV4_5_MODE_SVC, NULL, NULL},
126
127 {13, ARMV4_5_MODE_ABT, NULL, NULL},
128 {14, ARMV4_5_MODE_ABT, NULL, NULL},
129
130 {13, ARMV4_5_MODE_UND, NULL, NULL},
131 {14, ARMV4_5_MODE_UND, NULL, NULL},
132
133 {16, ARMV4_5_MODE_ANY, NULL, NULL},
134 {16, ARMV4_5_MODE_FIQ, NULL, NULL},
135 {16, ARMV4_5_MODE_IRQ, NULL, NULL},
136 {16, ARMV4_5_MODE_SVC, NULL, NULL},
137 {16, ARMV4_5_MODE_ABT, NULL, NULL},
138 {16, ARMV4_5_MODE_UND, NULL, NULL}
139 };
140
141 /* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */
142 int armv4_5_core_reg_map[7][17] =
143 {
144 { /* USR */
145 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
146 },
147 { /* FIQ */
148 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
149 },
150 { /* IRQ */
151 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
152 },
153 { /* SVC */
154 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
155 },
156 { /* ABT */
157 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
158 },
159 { /* UND */
160 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
161 },
162 { /* SYS */
163 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
164 }
165 };
166
167 u8 armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
168
169 reg_t armv4_5_gdb_dummy_fp_reg =
170 {
171 "GDB dummy floating-point register", armv4_5_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
172 };
173
174 u8 armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0};
175
176 reg_t armv4_5_gdb_dummy_fps_reg =
177 {
178 "GDB dummy floating-point status register", armv4_5_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
179 };
180
181
182 int armv4_5_get_core_reg(reg_t *reg)
183 {
184 int retval;
185 armv4_5_core_reg_t *armv4_5 = reg->arch_info;
186 target_t *target = armv4_5->target;
187
188 if (target->state != TARGET_HALTED)
189 {
190 LOG_ERROR("Target not halted");
191 return ERROR_TARGET_NOT_HALTED;
192 }
193
194 /* retval = armv4_5->armv4_5_common->full_context(target); */
195 retval = armv4_5->armv4_5_common->read_core_reg(target, armv4_5->num, armv4_5->mode);
196
197 return retval;
198 }
199
200 int armv4_5_set_core_reg(reg_t *reg, u8 *buf)
201 {
202 armv4_5_core_reg_t *armv4_5 = reg->arch_info;
203 target_t *target = armv4_5->target;
204 armv4_5_common_t *armv4_5_target = target->arch_info;
205 u32 value = buf_get_u32(buf, 0, 32);
206
207 if (target->state != TARGET_HALTED)
208 {
209 return ERROR_TARGET_NOT_HALTED;
210 }
211
212 if (reg == &armv4_5_target->core_cache->reg_list[ARMV4_5_CPSR])
213 {
214 if (value & 0x20)
215 {
216 /* T bit should be set */
217 if (armv4_5_target->core_state == ARMV4_5_STATE_ARM)
218 {
219 /* change state to Thumb */
220 LOG_DEBUG("changing to Thumb state");
221 armv4_5_target->core_state = ARMV4_5_STATE_THUMB;
222 }
223 }
224 else
225 {
226 /* T bit should be cleared */
227 if (armv4_5_target->core_state == ARMV4_5_STATE_THUMB)
228 {
229 /* change state to ARM */
230 LOG_DEBUG("changing to ARM state");
231 armv4_5_target->core_state = ARMV4_5_STATE_ARM;
232 }
233 }
234
235 if (armv4_5_target->core_mode != (value & 0x1f))
236 {
237 LOG_DEBUG("changing ARM core mode to '%s'", armv4_5_mode_strings[armv4_5_mode_to_number(value & 0x1f)]);
238 armv4_5_target->core_mode = value & 0x1f;
239 armv4_5_target->write_core_reg(target, 16, ARMV4_5_MODE_ANY, value);
240 }
241 }
242
243 buf_set_u32(reg->value, 0, 32, value);
244 reg->dirty = 1;
245 reg->valid = 1;
246
247 return ERROR_OK;
248 }
249
250 int armv4_5_invalidate_core_regs(target_t *target)
251 {
252 armv4_5_common_t *armv4_5 = target->arch_info;
253 int i;
254
255 for (i = 0; i < 37; i++)
256 {
257 armv4_5->core_cache->reg_list[i].valid = 0;
258 armv4_5->core_cache->reg_list[i].dirty = 0;
259 }
260
261 return ERROR_OK;
262 }
263
264 reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common)
265 {
266 int num_regs = 37;
267 reg_cache_t *cache = malloc(sizeof(reg_cache_t));
268 reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
269 armv4_5_core_reg_t *arch_info = malloc(sizeof(armv4_5_core_reg_t) * num_regs);
270 int i;
271
272 cache->name = "arm v4/5 registers";
273 cache->next = NULL;
274 cache->reg_list = reg_list;
275 cache->num_regs = num_regs;
276
277 if (armv4_5_core_reg_arch_type == -1)
278 armv4_5_core_reg_arch_type = register_reg_arch_type(armv4_5_get_core_reg, armv4_5_set_core_reg);
279
280 register_init_dummy(&armv4_5_gdb_dummy_fp_reg);
281 register_init_dummy(&armv4_5_gdb_dummy_fps_reg);
282
283 for (i = 0; i < 37; i++)
284 {
285 arch_info[i] = armv4_5_core_reg_list_arch_info[i];
286 arch_info[i].target = target;
287 arch_info[i].armv4_5_common = armv4_5_common;
288 reg_list[i].name = armv4_5_core_reg_list[i];
289 reg_list[i].size = 32;
290 reg_list[i].value = calloc(1, 4);
291 reg_list[i].dirty = 0;
292 reg_list[i].valid = 0;
293 reg_list[i].bitfield_desc = NULL;
294 reg_list[i].num_bitfields = 0;
295 reg_list[i].arch_type = armv4_5_core_reg_arch_type;
296 reg_list[i].arch_info = &arch_info[i];
297 }
298
299 return cache;
300 }
301
302 int armv4_5_arch_state(struct target_s *target)
303 {
304 armv4_5_common_t *armv4_5 = target->arch_info;
305
306 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
307 {
308 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
309 exit(-1);
310 }
311
312 LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
313 armv4_5_state_strings[armv4_5->core_state],
314 Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name,
315 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
316 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
317 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
318
319 return ERROR_OK;
320 }
321
322 int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
323 {
324 char output[128];
325 int output_len;
326 int mode, num;
327 target_t *target = get_current_target(cmd_ctx);
328 armv4_5_common_t *armv4_5 = target->arch_info;
329
330 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
331 {
332 command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
333 return ERROR_OK;
334 }
335
336 if (target->state != TARGET_HALTED)
337 {
338 command_print(cmd_ctx, "error: target must be halted for register accesses");
339 return ERROR_OK;
340 }
341
342 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
343 return ERROR_FAIL;
344
345 for (num = 0; num <= 15; num++)
346 {
347 output_len = 0;
348 for (mode = 0; mode < 6; mode++)
349 {
350 if (!ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).valid)
351 {
352 armv4_5->full_context(target);
353 }
354 output_len += snprintf(output + output_len, 128 - output_len, "%8s: %8.8x ", ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name,
355 buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32));
356 }
357 command_print(cmd_ctx, output);
358 }
359 command_print(cmd_ctx, " cpsr: %8.8x spsr_fiq: %8.8x spsr_irq: %8.8x spsr_svc: %8.8x spsr_abt: %8.8x spsr_und: %8.8x",
360 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
361 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_FIQ].value, 0, 32),
362 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_IRQ].value, 0, 32),
363 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_SVC].value, 0, 32),
364 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_ABT].value, 0, 32),
365 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_UND].value, 0, 32));
366
367 return ERROR_OK;
368 }
369
370 int handle_armv4_5_core_state_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
371 {
372 target_t *target = get_current_target(cmd_ctx);
373 armv4_5_common_t *armv4_5 = target->arch_info;
374
375 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
376 {
377 command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
378 return ERROR_OK;
379 }
380
381 if (argc > 0)
382 {
383 if (strcmp(args[0], "arm") == 0)
384 {
385 armv4_5->core_state = ARMV4_5_STATE_ARM;
386 }
387 if (strcmp(args[0], "thumb") == 0)
388 {
389 armv4_5->core_state = ARMV4_5_STATE_THUMB;
390 }
391 }
392
393 command_print(cmd_ctx, "core state: %s", armv4_5_state_strings[armv4_5->core_state]);
394
395 return ERROR_OK;
396 }
397
398 int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
399 {
400 target_t *target = get_current_target(cmd_ctx);
401 armv4_5_common_t *armv4_5 = target->arch_info;
402 u32 address;
403 int count;
404 int i;
405 arm_instruction_t cur_instruction;
406 u32 opcode;
407 int thumb = 0;
408
409 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
410 {
411 command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
412 return ERROR_OK;
413 }
414
415 if (argc < 2)
416 {
417 command_print(cmd_ctx, "usage: armv4_5 disassemble <address> <count> ['thumb']");
418 return ERROR_OK;
419 }
420
421 address = strtoul(args[0], NULL, 0);
422 count = strtoul(args[1], NULL, 0);
423
424 if (argc >= 3)
425 if (strcmp(args[2], "thumb") == 0)
426 thumb = 1;
427
428 for (i = 0; i < count; i++)
429 {
430 target_read_u32(target, address, &opcode);
431 arm_evaluate_opcode(opcode, address, &cur_instruction);
432 command_print(cmd_ctx, "%s", cur_instruction.text);
433 address += (thumb) ? 2 : 4;
434 }
435
436 return ERROR_OK;
437 }
438
439 int armv4_5_register_commands(struct command_context_s *cmd_ctx)
440 {
441 command_t *armv4_5_cmd;
442
443 armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5", NULL, COMMAND_ANY, "armv4/5 specific commands");
444
445 register_command(cmd_ctx, armv4_5_cmd, "reg", handle_armv4_5_reg_command, COMMAND_EXEC, "display ARM core registers");
446 register_command(cmd_ctx, armv4_5_cmd, "core_state", handle_armv4_5_core_state_command, COMMAND_EXEC, "display/change ARM core state <arm|thumb>");
447
448 register_command(cmd_ctx, armv4_5_cmd, "disassemble", handle_armv4_5_disassemble_command, COMMAND_EXEC, "disassemble instructions <address> <count> ['thumb']");
449 return ERROR_OK;
450 }
451
452 int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
453 {
454 armv4_5_common_t *armv4_5 = target->arch_info;
455 int i;
456
457 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
458 return ERROR_FAIL;
459
460 *reg_list_size = 26;
461 *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
462
463 for (i = 0; i < 16; i++)
464 {
465 (*reg_list)[i] = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i);
466 }
467
468 for (i = 16; i < 24; i++)
469 {
470 (*reg_list)[i] = &armv4_5_gdb_dummy_fp_reg;
471 }
472
473 (*reg_list)[24] = &armv4_5_gdb_dummy_fps_reg;
474 (*reg_list)[25] = &armv4_5->core_cache->reg_list[ARMV4_5_CPSR];
475
476 return ERROR_OK;
477 }
478
479 int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
480 {
481 armv4_5_common_t *armv4_5 = target->arch_info;
482 armv4_5_algorithm_t *armv4_5_algorithm_info = arch_info;
483 enum armv4_5_state core_state = armv4_5->core_state;
484 enum armv4_5_mode core_mode = armv4_5->core_mode;
485 u32 context[17];
486 u32 cpsr;
487 int exit_breakpoint_size = 0;
488 int i;
489 int retval = ERROR_OK;
490 LOG_DEBUG("Running algorithm");
491
492 if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
493 {
494 LOG_ERROR("current target isn't an ARMV4/5 target");
495 return ERROR_TARGET_INVALID;
496 }
497
498 if (target->state != TARGET_HALTED)
499 {
500 LOG_WARNING("target not halted");
501 return ERROR_TARGET_NOT_HALTED;
502 }
503
504 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
505 return ERROR_FAIL;
506
507 for (i = 0; i <= 16; i++)
508 {
509 if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid)
510 armv4_5->read_core_reg(target, i, armv4_5_algorithm_info->core_mode);
511 context[i] = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
512 }
513 cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32);
514
515 for (i = 0; i < num_mem_params; i++)
516 {
517 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
518 }
519
520 for (i = 0; i < num_reg_params; i++)
521 {
522 reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
523 if (!reg)
524 {
525 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
526 exit(-1);
527 }
528
529 if (reg->size != reg_params[i].size)
530 {
531 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
532 exit(-1);
533 }
534
535 armv4_5_set_core_reg(reg, reg_params[i].value);
536 }
537
538 armv4_5->core_state = armv4_5_algorithm_info->core_state;
539 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
540 exit_breakpoint_size = 4;
541 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
542 exit_breakpoint_size = 2;
543 else
544 {
545 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
546 exit(-1);
547 }
548
549 if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
550 {
551 LOG_DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode);
552 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 5, armv4_5_algorithm_info->core_mode);
553 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
554 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
555 }
556
557 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
558 {
559 LOG_ERROR("can't add breakpoint to finish algorithm execution");
560 return ERROR_TARGET_FAILURE;
561 }
562
563 target_resume(target, 0, entry_point, 1, 1);
564
565 target_wait_state(target, TARGET_HALTED, timeout_ms);
566 if (target->state != TARGET_HALTED)
567 {
568 if ((retval=target_halt(target))!=ERROR_OK)
569 return retval;
570 if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
571 {
572 return retval;
573 }
574 return ERROR_TARGET_TIMEOUT;
575 }
576
577 if (buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) != exit_point)
578 {
579 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
580 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
581 return ERROR_TARGET_TIMEOUT;
582 }
583
584 breakpoint_remove(target, exit_point);
585
586 for (i = 0; i < num_mem_params; i++)
587 {
588 if (mem_params[i].direction != PARAM_OUT)
589 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
590 }
591
592 for (i = 0; i < num_reg_params; i++)
593 {
594 if (reg_params[i].direction != PARAM_OUT)
595 {
596
597 reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
598 if (!reg)
599 {
600 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
601 exit(-1);
602 }
603
604 if (reg->size != reg_params[i].size)
605 {
606 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
607 exit(-1);
608 }
609
610 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
611 }
612 }
613
614 for (i = 0; i <= 16; i++)
615 {
616 LOG_DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
617 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
618 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
619 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
620 }
621 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
622 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
623 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
624
625 armv4_5->core_state = core_state;
626 armv4_5->core_mode = core_mode;
627
628 return retval;
629 }
630
631 int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5)
632 {
633 target->arch_info = armv4_5;
634
635 armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
636 armv4_5->core_state = ARMV4_5_STATE_ARM;
637 armv4_5->core_mode = ARMV4_5_MODE_USR;
638
639 return ERROR_OK;
640 }
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