ARM: update arm_opcodes.h copyright
[openocd.git] / src / target / arm_opcodes.h
1 /*
2 * Copyright (C) 2005 by Dominic Rath
3 * Dominic.Rath@gmx.de
4 *
5 * Copyright (C) 2006 by Magnus Lundin
6 * lundin@mlu.mine.nu
7 *
8 * Copyright (C) 2008 by Spencer Oliver
9 * spen@spen-soft.co.uk
10 *
11 * Copyright (C) 2009 by √ėyvind Harboe
12 * oyvind.harboe@zylin.com
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the
26 * Free Software Foundation, Inc.,
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 */
29 #ifndef __ARM_OPCODES_H
30 #define __ARM_OPCODES_H
31
32 /**
33 * @file
34 * Macros used to generate various ARM or Thumb opcodes.
35 */
36
37 /* ARM mode instructions */
38
39 /* Store multiple increment after
40 * Rn: base register
41 * List: for each bit in list: store register
42 * S: in priviledged mode: store user-mode registers
43 * W = 1: update the base register. W = 0: leave the base register untouched
44 */
45 #define ARMV4_5_STMIA(Rn, List, S, W) \
46 (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
47
48 /* Load multiple increment after
49 * Rn: base register
50 * List: for each bit in list: store register
51 * S: in priviledged mode: store user-mode registers
52 * W = 1: update the base register. W = 0: leave the base register untouched
53 */
54 #define ARMV4_5_LDMIA(Rn, List, S, W) \
55 (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
56
57 /* MOV r8, r8 */
58 #define ARMV4_5_NOP (0xe1a08008)
59
60 /* Move PSR to general purpose register
61 * R = 1: SPSR R = 0: CPSR
62 * Rn: target register
63 */
64 #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
65
66 /* Store register
67 * Rd: register to store
68 * Rn: base register
69 */
70 #define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
71
72 /* Load register
73 * Rd: register to load
74 * Rn: base register
75 */
76 #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
77
78 /* Move general purpose register to PSR
79 * R = 1: SPSR R = 0: CPSR
80 * Field: Field mask
81 * 1: control field 2: extension field 4: status field 8: flags field
82 * Rm: source register
83 */
84 #define ARMV4_5_MSR_GP(Rm, Field, R) \
85 (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
86 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \
87 (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
88
89 /* Load Register Halfword Immediate Post-Index
90 * Rd: register to load
91 * Rn: base register
92 */
93 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
94
95 /* Load Register Byte Immediate Post-Index
96 * Rd: register to load
97 * Rn: base register
98 */
99 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
100
101 /* Store register Halfword Immediate Post-Index
102 * Rd: register to store
103 * Rn: base register
104 */
105 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
106
107 /* Store register Byte Immediate Post-Index
108 * Rd: register to store
109 * Rn: base register
110 */
111 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
112
113 /* Branch (and Link)
114 * Im: Branch target (left-shifted by 2 bits, added to PC)
115 * L: 1: branch and link 0: branch only
116 */
117 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
118
119 /* Branch and exchange (ARM state)
120 * Rm: register holding branch target address
121 */
122 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
123
124 /* Move to ARM register from coprocessor
125 * CP: Coprocessor number
126 * op1: Coprocessor opcode
127 * Rd: destination register
128 * CRn: first coprocessor operand
129 * CRm: second coprocessor operand
130 * op2: Second coprocessor opcode
131 */
132 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) \
133 (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
134 | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
135
136 /* Move to coprocessor from ARM register
137 * CP: Coprocessor number
138 * op1: Coprocessor opcode
139 * Rd: destination register
140 * CRn: first coprocessor operand
141 * CRm: second coprocessor operand
142 * op2: Second coprocessor opcode
143 */
144 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) \
145 (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
146 | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
147
148 /* Breakpoint instruction (ARMv5)
149 * Im: 16-bit immediate
150 */
151 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
152
153
154 /* Thumb mode instructions
155 *
156 * NOTE: these 16-bit opcodes fill both halves of a word with the same
157 * value. The reason for this is that when we need to execute Thumb
158 * opcodes on ARM7/ARM9 cores (to switch to ARM state on debug entry),
159 * we must shift 32 bits to the bus using scan chain 1 ... if we write
160 * both halves, we don't need to track which half matters. On ARMv6 and
161 * ARMv7 we don't execute Thumb instructions in debug mode; the ITR
162 * register does not accept Thumb (or Thumb2) opcodes.
163 */
164
165 /* Store register (Thumb mode)
166 * Rd: source register
167 * Rn: base register
168 */
169 #define ARMV4_5_T_STR(Rd, Rn) \
170 ((0x6000 | (Rd) | ((Rn) << 3)) | \
171 ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
172
173 /* Load register (Thumb state)
174 * Rd: destination register
175 * Rn: base register
176 */
177 #define ARMV4_5_T_LDR(Rd, Rn) \
178 ((0x6800 | ((Rn) << 3) | (Rd)) \
179 | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
180
181 /* Load multiple (Thumb state)
182 * Rn: base register
183 * List: for each bit in list: store register
184 */
185 #define ARMV4_5_T_LDMIA(Rn, List) \
186 ((0xc800 | ((Rn) << 8) | (List)) \
187 | ((0xc800 | ((Rn) << 8) | (List)) << 16))
188
189 /* Load register with PC relative addressing
190 * Rd: register to load
191 */
192 #define ARMV4_5_T_LDR_PCREL(Rd) \
193 ((0x4800 | ((Rd) << 8)) \
194 | ((0x4800 | ((Rd) << 8)) << 16))
195
196 /* Move hi register (Thumb mode)
197 * Rd: destination register
198 * Rm: source register
199 */
200 #define ARMV4_5_T_MOV(Rd, Rm) \
201 ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
202 (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) \
203 | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
204 (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
205
206 /* No operation (Thumb mode)
207 * NOTE: this is "MOV r8, r8" ... Thumb2 adds two
208 * architected NOPs, 16-bit and 32-bit.
209 */
210 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
211
212 /* Move immediate to register (Thumb state)
213 * Rd: destination register
214 * Im: 8-bit immediate value
215 */
216 #define ARMV4_5_T_MOV_IM(Rd, Im) \
217 ((0x2000 | ((Rd) << 8) | (Im)) \
218 | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
219
220 /* Branch and Exchange
221 * Rm: register containing branch target
222 */
223 #define ARMV4_5_T_BX(Rm) \
224 ((0x4700 | ((Rm) << 3)) \
225 | ((0x4700 | ((Rm) << 3)) << 16))
226
227 /* Branch (Thumb state)
228 * Imm: Branch target
229 */
230 #define ARMV4_5_T_B(Imm) \
231 ((0xe000 | (Imm)) \
232 | ((0xe000 | (Imm)) << 16))
233
234 /* Breakpoint instruction (ARMv5) (Thumb state)
235 * Im: 8-bit immediate
236 */
237 #define ARMV5_T_BKPT(Im) \
238 ((0xbe00 | (Im)) \
239 | ((0xbe00 | (Im)) << 16))
240
241 /* Move to Register from Special Register
242 * 32 bit Thumb2 instruction
243 * Rd: destination register
244 * SYSm: source special register
245 */
246 #define ARM_T2_MRS(Rd, SYSm) \
247 ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
248
249 /* Move from Register from Special Register
250 * 32 bit Thumb2 instruction
251 * Rd: source register
252 * SYSm: destination special register
253 */
254 #define ARM_T2_MSR(SYSm, Rn) \
255 ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
256
257 /* Change Processor State.
258 * 16 bit Thumb2 instruction
259 * Rd: source register
260 * IF: A_FLAG and/or I_FLAG and/or F_FLAG
261 */
262 #define A_FLAG 4
263 #define I_FLAG 2
264 #define F_FLAG 1
265 #define ARM_T2_CPSID(IF) \
266 ((0xB660 | (1 << 8) | ((IF)&0x3)) \
267 | ((0xB660 | (1 << 8) | ((IF)&0x3)) << 16))
268 #define ARM_T2_CPSIE(IF) \
269 ((0xB660 | (0 << 8) | ((IF)&0x3)) \
270 | ((0xB660 | (0 << 8) | ((IF)&0x3)) << 16))
271
272 #endif /* __ARM_OPCODES_H */