2 * Copyright (C) 2009 by David Brownell
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 #include <jtag/jtag.h>
26 #include "breakpoints.h"
27 #include "target_type.h"
28 #include "arm_opcodes.h"
33 * Implements various ARM DPM operations using architectural debug registers.
34 * These routines layer over core-specific communication methods to cope with
35 * implementation differences between cores like ARM1136 and Cortex-A8.
37 * The "Debug Programmers' Model" (DPM) for ARMv6 and ARMv7 is defined by
38 * Part C (Debug Architecture) of the ARM Architecture Reference Manual,
39 * ARMv7-A and ARMv7-R edition (ARM DDI 0406B). In OpenOCD, DPM operations
40 * are abstracted through internal programming interfaces to share code and
41 * to minimize needless differences in debug behavior between cores.
44 /*----------------------------------------------------------------------*/
50 /* Read coprocessor */
51 static int dpm_mrc(struct target
*target
, int cpnum
,
52 uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
,
55 struct arm
*arm
= target_to_arm(target
);
56 struct arm_dpm
*dpm
= arm
->dpm
;
59 retval
= dpm
->prepare(dpm
);
60 if (retval
!= ERROR_OK
)
63 LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum
,
65 (int) CRm
, (int) op2
);
67 /* read coprocessor register into R0; return via DCC */
68 retval
= dpm
->instr_read_data_r0(dpm
,
69 ARMV4_5_MRC(cpnum
, op1
, 0, CRn
, CRm
, op2
),
72 /* (void) */ dpm
->finish(dpm
);
76 static int dpm_mcr(struct target
*target
, int cpnum
,
77 uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
,
80 struct arm
*arm
= target_to_arm(target
);
81 struct arm_dpm
*dpm
= arm
->dpm
;
84 retval
= dpm
->prepare(dpm
);
85 if (retval
!= ERROR_OK
)
88 LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum
,
90 (int) CRm
, (int) op2
);
92 /* read DCC into r0; then write coprocessor register from R0 */
93 retval
= dpm
->instr_write_data_r0(dpm
,
94 ARMV4_5_MCR(cpnum
, op1
, 0, CRn
, CRm
, op2
),
97 /* (void) */ dpm
->finish(dpm
);
101 /*----------------------------------------------------------------------*/
104 * Register access utilities
107 /* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
108 * Routines *must* restore the original mode before returning!!
110 int dpm_modeswitch(struct arm_dpm
*dpm
, enum arm_mode mode
)
115 /* restore previous mode */
116 if (mode
== ARM_MODE_ANY
)
117 cpsr
= buf_get_u32(dpm
->arm
->cpsr
->value
, 0, 32);
119 /* else force to the specified mode */
123 retval
= dpm
->instr_write_data_r0(dpm
, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr
);
124 if (retval
!= ERROR_OK
)
127 if (dpm
->instr_cpsr_sync
)
128 retval
= dpm
->instr_cpsr_sync(dpm
);
133 /* just read the register -- rely on the core mode being right */
134 static int dpm_read_reg(struct arm_dpm
*dpm
, struct reg
*r
, unsigned regnum
)
141 /* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
142 retval
= dpm
->instr_read_data_dcc(dpm
,
143 ARMV4_5_MCR(14, 0, regnum
, 0, 5, 0),
147 * "MOV r0, pc"; then return via DCC */
148 retval
= dpm
->instr_read_data_r0(dpm
, 0xe1a0000f, &value
);
150 /* NOTE: this seems like a slightly awkward place to update
151 * this value ... but if the PC gets written (the only way
152 * to change what we compute), the arch spec says subsequent
153 * reads return values which are "unpredictable". So this
154 * is always right except in those broken-by-intent cases.
156 switch (dpm
->arm
->core_state
) {
160 case ARM_STATE_THUMB
:
161 case ARM_STATE_THUMB_EE
:
164 case ARM_STATE_JAZELLE
:
165 /* core-specific ... ? */
166 LOG_WARNING("Jazelle PC adjustment unknown");
171 /* 16: "MRS r0, CPSR"; then return via DCC
172 * 17: "MRS r0, SPSR"; then return via DCC
174 retval
= dpm
->instr_read_data_r0(dpm
,
175 ARMV4_5_MRS(0, regnum
& 1),
180 if (retval
== ERROR_OK
) {
181 buf_set_u32(r
->value
, 0, 32, value
);
184 LOG_DEBUG("READ: %s, %8.8x", r
->name
, (unsigned) value
);
190 /* just write the register -- rely on the core mode being right */
191 static int dpm_write_reg(struct arm_dpm
*dpm
, struct reg
*r
, unsigned regnum
)
194 uint32_t value
= buf_get_u32(r
->value
, 0, 32);
198 /* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */
199 retval
= dpm
->instr_write_data_dcc(dpm
,
200 ARMV4_5_MRC(14, 0, regnum
, 0, 5, 0),
204 * read r0 from DCC; then "MOV pc, r0" */
205 retval
= dpm
->instr_write_data_r0(dpm
, 0xe1a0f000, value
);
208 /* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf"
209 * 17: read r0 from DCC, then "MSR r0, SPSR_cxsf"
211 retval
= dpm
->instr_write_data_r0(dpm
,
212 ARMV4_5_MSR_GP(0, 0xf, regnum
& 1),
214 if (retval
!= ERROR_OK
)
217 if (regnum
== 16 && dpm
->instr_cpsr_sync
)
218 retval
= dpm
->instr_cpsr_sync(dpm
);
223 if (retval
== ERROR_OK
) {
225 LOG_DEBUG("WRITE: %s, %8.8x", r
->name
, (unsigned) value
);
232 * Write to program counter and switch the core state (arm/thumb) according to
235 static int dpm_write_pc_core_state(struct arm_dpm
*dpm
, struct reg
*r
)
237 uint32_t value
= buf_get_u32(r
->value
, 0, 32);
239 /* read r0 from DCC; then "BX r0" */
240 return dpm
->instr_write_data_r0(dpm
, ARMV4_5_BX(0), value
);
244 * Read basic registers of the the current context: R0 to R15, and CPSR;
245 * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
246 * In normal operation this is called on entry to halting debug state,
247 * possibly after some other operations supporting restore of debug state
248 * or making sure the CPU is fully idle (drain write buffer, etc).
250 int arm_dpm_read_current_registers(struct arm_dpm
*dpm
)
252 struct arm
*arm
= dpm
->arm
;
257 retval
= dpm
->prepare(dpm
);
258 if (retval
!= ERROR_OK
)
261 /* read R0 first (it's used for scratch), then CPSR */
262 r
= arm
->core_cache
->reg_list
+ 0;
264 retval
= dpm_read_reg(dpm
, r
, 0);
265 if (retval
!= ERROR_OK
)
270 retval
= dpm
->instr_read_data_r0(dpm
, ARMV4_5_MRS(0, 0), &cpsr
);
271 if (retval
!= ERROR_OK
)
274 /* update core mode and state, plus shadow mapping for R8..R14 */
275 arm_set_cpsr(arm
, cpsr
);
277 /* REVISIT we can probably avoid reading R1..R14, saving time... */
278 for (unsigned i
= 1; i
< 16; i
++) {
279 r
= arm_reg_current(arm
, i
);
283 retval
= dpm_read_reg(dpm
, r
, i
);
284 if (retval
!= ERROR_OK
)
288 /* NOTE: SPSR ignored (if it's even relevant). */
290 /* REVISIT the debugger can trigger various exceptions. See the
291 * ARMv7A architecture spec, section C5.7, for more info about
292 * what defenses are needed; v6 debug has the most issues.
296 /* (void) */ dpm
->finish(dpm
);
300 /* Avoid needless I/O ... leave breakpoints and watchpoints alone
301 * unless they're removed, or need updating because of single-stepping
302 * or running debugger code.
304 static int dpm_maybe_update_bpwp(struct arm_dpm
*dpm
, bool bpwp
,
305 struct dpm_bpwp
*xp
, int *set_p
)
307 int retval
= ERROR_OK
;
314 /* removed or startup; we must disable it */
319 /* disabled, but we must set it */
320 xp
->dirty
= disable
= false;
325 /* set, but we must temporarily disable it */
326 xp
->dirty
= disable
= true;
331 retval
= dpm
->bpwp_disable(dpm
, xp
->number
);
333 retval
= dpm
->bpwp_enable(dpm
, xp
->number
,
334 xp
->address
, xp
->control
);
336 if (retval
!= ERROR_OK
)
337 LOG_ERROR("%s: can't %s HW %spoint %d",
338 disable
? "disable" : "enable",
339 target_name(dpm
->arm
->target
),
340 (xp
->number
< 16) ? "break" : "watch",
346 static int dpm_add_breakpoint(struct target
*target
, struct breakpoint
*bp
);
349 * Writes all modified core registers for all processor modes. In normal
350 * operation this is called on exit from halting debug state.
352 * @param dpm: represents the processor
353 * @param bpwp: true ensures breakpoints and watchpoints are set,
354 * false ensures they are cleared
356 int arm_dpm_write_dirty_registers(struct arm_dpm
*dpm
, bool bpwp
)
358 struct arm
*arm
= dpm
->arm
;
359 struct reg_cache
*cache
= arm
->core_cache
;
363 retval
= dpm
->prepare(dpm
);
364 if (retval
!= ERROR_OK
)
367 /* If we're managing hardware breakpoints for this core, enable
368 * or disable them as requested.
370 * REVISIT We don't yet manage them for ANY cores. Eventually
371 * we should be able to assume we handle them; but until then,
372 * cope with the hand-crafted breakpoint code.
374 if (arm
->target
->type
->add_breakpoint
== dpm_add_breakpoint
) {
375 for (unsigned i
= 0; i
< dpm
->nbp
; i
++) {
376 struct dpm_bp
*dbp
= dpm
->dbp
+ i
;
377 struct breakpoint
*bp
= dbp
->bp
;
379 retval
= dpm_maybe_update_bpwp(dpm
, bpwp
, &dbp
->bpwp
,
380 bp
? &bp
->set
: NULL
);
381 if (retval
!= ERROR_OK
)
386 /* enable/disable watchpoints */
387 for (unsigned i
= 0; i
< dpm
->nwp
; i
++) {
388 struct dpm_wp
*dwp
= dpm
->dwp
+ i
;
389 struct watchpoint
*wp
= dwp
->wp
;
391 retval
= dpm_maybe_update_bpwp(dpm
, bpwp
, &dwp
->bpwp
,
392 wp
? &wp
->set
: NULL
);
393 if (retval
!= ERROR_OK
)
397 /* NOTE: writes to breakpoint and watchpoint registers might
398 * be queued, and need (efficient/batched) flushing later.
401 /* Scan the registers until we find one that's both dirty and
402 * eligible for flushing. Flush that and everything else that
403 * shares the same core mode setting. Typically this won't
404 * actually find anything to do...
407 enum arm_mode mode
= ARM_MODE_ANY
;
411 /* check everything except our scratch register R0 */
412 for (unsigned i
= 1; i
< cache
->num_regs
; i
++) {
416 /* also skip PC, CPSR, and non-dirty */
419 if (arm
->cpsr
== cache
->reg_list
+ i
)
421 if (!cache
->reg_list
[i
].dirty
)
424 r
= cache
->reg_list
[i
].arch_info
;
427 /* may need to pick and set a mode */
432 mode
= tmode
= r
->mode
;
434 /* cope with special cases */
437 /* r8..r12 "anything but FIQ" case;
438 * we "know" core mode is accurate
439 * since we haven't changed it yet
441 if (arm
->core_mode
== ARM_MODE_FIQ
444 tmode
= ARM_MODE_USR
;
452 /* REVISIT error checks */
453 if (tmode
!= ARM_MODE_ANY
) {
454 retval
= dpm_modeswitch(dpm
, tmode
);
455 if (retval
!= ERROR_OK
)
462 retval
= dpm_write_reg(dpm
,
465 if (retval
!= ERROR_OK
)
471 /* Restore original CPSR ... assuming either that we changed it,
472 * or it's dirty. Must write PC to ensure the return address is
473 * defined, and must not write it before CPSR.
475 retval
= dpm_modeswitch(dpm
, ARM_MODE_ANY
);
476 if (retval
!= ERROR_OK
)
478 arm
->cpsr
->dirty
= false;
480 /* restore the PC, make sure to also switch the core state
481 * to whatever it was set to with "arm core_state" command.
482 * target code will have set PC to an appropriate resume address.
484 retval
= dpm_write_pc_core_state(dpm
, arm
->pc
);
485 if (retval
!= ERROR_OK
)
487 /* on Cortex-A5 (as found on NXP VF610 SoC), BX instruction
488 * executed in debug state doesn't appear to set the PC,
489 * explicitly set it with a "MOV pc, r0". This doesn't influence
490 * CPSR on Cortex-A9 so it should be OK. Maybe due to different
493 retval
= dpm_write_reg(dpm
, arm
->pc
, 15);
494 if (retval
!= ERROR_OK
)
496 arm
->pc
->dirty
= false;
498 /* flush R0 -- it's *very* dirty by now */
499 retval
= dpm_write_reg(dpm
, &cache
->reg_list
[0], 0);
500 if (retval
!= ERROR_OK
)
502 cache
->reg_list
[0].dirty
= false;
504 /* (void) */ dpm
->finish(dpm
);
509 /* Returns ARM_MODE_ANY or temporary mode to use while reading the
510 * specified register ... works around flakiness from ARM core calls.
511 * Caller already filtered out SPSR access; mode is never MODE_SYS
514 static enum arm_mode
dpm_mapmode(struct arm
*arm
,
515 unsigned num
, enum arm_mode mode
)
517 enum arm_mode amode
= arm
->core_mode
;
519 /* don't switch if the mode is already correct */
520 if (amode
== ARM_MODE_SYS
)
521 amode
= ARM_MODE_USR
;
526 /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */
531 /* r8..r12 aren't shadowed for anything except FIQ */
533 if (mode
== ARM_MODE_FIQ
)
536 /* r13/sp, and r14/lr are always shadowed */
541 LOG_WARNING("invalid register #%u", num
);
549 * Standard ARM register accessors ... there are three methods
550 * in "struct arm", to support individual read/write and bulk read
554 static int arm_dpm_read_core_reg(struct target
*target
, struct reg
*r
,
555 int regnum
, enum arm_mode mode
)
557 struct arm_dpm
*dpm
= target_to_arm(target
)->dpm
;
560 if (regnum
< 0 || regnum
> 16)
561 return ERROR_COMMAND_SYNTAX_ERROR
;
564 if (mode
!= ARM_MODE_ANY
)
567 mode
= dpm_mapmode(dpm
->arm
, regnum
, mode
);
569 /* REVISIT what happens if we try to read SPSR in a core mode
570 * which has no such register?
573 retval
= dpm
->prepare(dpm
);
574 if (retval
!= ERROR_OK
)
577 if (mode
!= ARM_MODE_ANY
) {
578 retval
= dpm_modeswitch(dpm
, mode
);
579 if (retval
!= ERROR_OK
)
583 retval
= dpm_read_reg(dpm
, r
, regnum
);
584 if (retval
!= ERROR_OK
)
586 /* always clean up, regardless of error */
588 if (mode
!= ARM_MODE_ANY
)
589 /* (void) */ dpm_modeswitch(dpm
, ARM_MODE_ANY
);
592 /* (void) */ dpm
->finish(dpm
);
596 static int arm_dpm_write_core_reg(struct target
*target
, struct reg
*r
,
597 int regnum
, enum arm_mode mode
, uint8_t *value
)
599 struct arm_dpm
*dpm
= target_to_arm(target
)->dpm
;
603 if (regnum
< 0 || regnum
> 16)
604 return ERROR_COMMAND_SYNTAX_ERROR
;
607 if (mode
!= ARM_MODE_ANY
)
610 mode
= dpm_mapmode(dpm
->arm
, regnum
, mode
);
612 /* REVISIT what happens if we try to write SPSR in a core mode
613 * which has no such register?
616 retval
= dpm
->prepare(dpm
);
617 if (retval
!= ERROR_OK
)
620 if (mode
!= ARM_MODE_ANY
) {
621 retval
= dpm_modeswitch(dpm
, mode
);
622 if (retval
!= ERROR_OK
)
626 retval
= dpm_write_reg(dpm
, r
, regnum
);
627 /* always clean up, regardless of error */
629 if (mode
!= ARM_MODE_ANY
)
630 /* (void) */ dpm_modeswitch(dpm
, ARM_MODE_ANY
);
633 /* (void) */ dpm
->finish(dpm
);
637 static int arm_dpm_full_context(struct target
*target
)
639 struct arm
*arm
= target_to_arm(target
);
640 struct arm_dpm
*dpm
= arm
->dpm
;
641 struct reg_cache
*cache
= arm
->core_cache
;
645 retval
= dpm
->prepare(dpm
);
646 if (retval
!= ERROR_OK
)
650 enum arm_mode mode
= ARM_MODE_ANY
;
654 /* We "know" arm_dpm_read_current_registers() was called so
655 * the unmapped registers (R0..R7, PC, AND CPSR) and some
656 * view of R8..R14 are current. We also "know" oddities of
657 * register mapping: special cases for R8..R12 and SPSR.
659 * Pick some mode with unread registers and read them all.
662 for (unsigned i
= 0; i
< cache
->num_regs
; i
++) {
665 if (cache
->reg_list
[i
].valid
)
667 r
= cache
->reg_list
[i
].arch_info
;
669 /* may need to pick a mode and set CPSR */
674 /* For regular (ARM_MODE_ANY) R8..R12
675 * in case we've entered debug state
676 * in FIQ mode we need to patch mode.
678 if (mode
!= ARM_MODE_ANY
)
679 retval
= dpm_modeswitch(dpm
, mode
);
681 retval
= dpm_modeswitch(dpm
, ARM_MODE_USR
);
683 if (retval
!= ERROR_OK
)
689 /* CPSR was read, so "R16" must mean SPSR */
690 retval
= dpm_read_reg(dpm
,
692 (r
->num
== 16) ? 17 : r
->num
);
693 if (retval
!= ERROR_OK
)
699 retval
= dpm_modeswitch(dpm
, ARM_MODE_ANY
);
700 /* (void) */ dpm
->finish(dpm
);
706 /*----------------------------------------------------------------------*/
709 * Breakpoint and Watchpoint support.
711 * Hardware {break,watch}points are usually left active, to minimize
712 * debug entry/exit costs. When they are set or cleared, it's done in
713 * batches. Also, DPM-conformant hardware can update debug registers
714 * regardless of whether the CPU is running or halted ... though that
715 * fact isn't currently leveraged.
718 static int dpm_bpwp_setup(struct arm_dpm
*dpm
, struct dpm_bpwp
*xp
,
719 uint32_t addr
, uint32_t length
)
723 control
= (1 << 0) /* enable */
724 | (3 << 1); /* both user and privileged access */
726 /* Match 1, 2, or all 4 byte addresses in this word.
728 * FIXME: v7 hardware allows lengths up to 2 GB for BP and WP.
729 * Support larger length, when addr is suitably aligned. In
730 * particular, allow watchpoints on 8 byte "double" values.
732 * REVISIT allow watchpoints on unaligned 2-bit values; and on
733 * v7 hardware, unaligned 4-byte ones too.
737 control
|= (1 << (addr
& 3)) << 5;
740 /* require 2-byte alignment */
742 control
|= (3 << (addr
& 2)) << 5;
747 /* require 4-byte alignment */
754 LOG_ERROR("unsupported {break,watch}point length/alignment");
755 return ERROR_COMMAND_SYNTAX_ERROR
;
758 /* other shared control bits:
759 * bits 15:14 == 0 ... both secure and nonsecure states (v6.1+ only)
760 * bit 20 == 0 ... not linked to a context ID
761 * bit 28:24 == 0 ... not ignoring N LSBs (v7 only)
764 xp
->address
= addr
& ~3;
765 xp
->control
= control
;
768 LOG_DEBUG("BPWP: addr %8.8" PRIx32
", control %" PRIx32
", number %d",
769 xp
->address
, control
, xp
->number
);
771 /* hardware is updated in write_dirty_registers() */
775 static int dpm_add_breakpoint(struct target
*target
, struct breakpoint
*bp
)
777 struct arm
*arm
= target_to_arm(target
);
778 struct arm_dpm
*dpm
= arm
->dpm
;
779 int retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
782 return ERROR_COMMAND_SYNTAX_ERROR
;
783 if (!dpm
->bpwp_enable
)
786 /* FIXME we need a generic solution for software breakpoints. */
787 if (bp
->type
== BKPT_SOFT
)
788 LOG_DEBUG("using HW bkpt, not SW...");
790 for (unsigned i
= 0; i
< dpm
->nbp
; i
++) {
791 if (!dpm
->dbp
[i
].bp
) {
792 retval
= dpm_bpwp_setup(dpm
, &dpm
->dbp
[i
].bpwp
,
793 bp
->address
, bp
->length
);
794 if (retval
== ERROR_OK
)
803 static int dpm_remove_breakpoint(struct target
*target
, struct breakpoint
*bp
)
805 struct arm
*arm
= target_to_arm(target
);
806 struct arm_dpm
*dpm
= arm
->dpm
;
807 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
809 for (unsigned i
= 0; i
< dpm
->nbp
; i
++) {
810 if (dpm
->dbp
[i
].bp
== bp
) {
811 dpm
->dbp
[i
].bp
= NULL
;
812 dpm
->dbp
[i
].bpwp
.dirty
= true;
814 /* hardware is updated in write_dirty_registers() */
823 static int dpm_watchpoint_setup(struct arm_dpm
*dpm
, unsigned index_t
,
824 struct watchpoint
*wp
)
827 struct dpm_wp
*dwp
= dpm
->dwp
+ index_t
;
830 /* this hardware doesn't support data value matching or masking */
831 if (wp
->value
|| wp
->mask
!= ~(uint32_t)0) {
832 LOG_DEBUG("watchpoint values and masking not supported");
833 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
836 retval
= dpm_bpwp_setup(dpm
, &dwp
->bpwp
, wp
->address
, wp
->length
);
837 if (retval
!= ERROR_OK
)
840 control
= dwp
->bpwp
.control
;
852 dwp
->bpwp
.control
= control
;
854 dpm
->dwp
[index_t
].wp
= wp
;
859 static int dpm_add_watchpoint(struct target
*target
, struct watchpoint
*wp
)
861 struct arm
*arm
= target_to_arm(target
);
862 struct arm_dpm
*dpm
= arm
->dpm
;
863 int retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
865 if (dpm
->bpwp_enable
) {
866 for (unsigned i
= 0; i
< dpm
->nwp
; i
++) {
867 if (!dpm
->dwp
[i
].wp
) {
868 retval
= dpm_watchpoint_setup(dpm
, i
, wp
);
877 static int dpm_remove_watchpoint(struct target
*target
, struct watchpoint
*wp
)
879 struct arm
*arm
= target_to_arm(target
);
880 struct arm_dpm
*dpm
= arm
->dpm
;
881 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
883 for (unsigned i
= 0; i
< dpm
->nwp
; i
++) {
884 if (dpm
->dwp
[i
].wp
== wp
) {
885 dpm
->dwp
[i
].wp
= NULL
;
886 dpm
->dwp
[i
].bpwp
.dirty
= true;
888 /* hardware is updated in write_dirty_registers() */
897 void arm_dpm_report_wfar(struct arm_dpm
*dpm
, uint32_t addr
)
899 switch (dpm
->arm
->core_state
) {
903 case ARM_STATE_THUMB
:
904 case ARM_STATE_THUMB_EE
:
907 case ARM_STATE_JAZELLE
:
914 /*----------------------------------------------------------------------*/
917 * Other debug and support utilities
920 void arm_dpm_report_dscr(struct arm_dpm
*dpm
, uint32_t dscr
)
922 struct target
*target
= dpm
->arm
->target
;
926 /* Examine debug reason */
927 switch (DSCR_ENTRY(dscr
)) {
928 case 6: /* Data abort (v6 only) */
929 case 7: /* Prefetch abort (v6 only) */
930 /* FALL THROUGH -- assume a v6 core in abort mode */
931 case 0: /* HALT request from debugger */
933 target
->debug_reason
= DBG_REASON_DBGRQ
;
935 case 1: /* HW breakpoint */
936 case 3: /* SW BKPT */
937 case 5: /* vector catch */
938 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
940 case 2: /* asynch watchpoint */
941 case 10:/* precise watchpoint */
942 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
945 target
->debug_reason
= DBG_REASON_UNDEFINED
;
950 /*----------------------------------------------------------------------*/
953 * Setup and management support.
957 * Hooks up this DPM to its associated target; call only once.
958 * Initially this only covers the register cache.
960 * Oh, and watchpoints. Yeah.
962 int arm_dpm_setup(struct arm_dpm
*dpm
)
964 struct arm
*arm
= dpm
->arm
;
965 struct target
*target
= arm
->target
;
966 struct reg_cache
*cache
;
970 /* register access setup */
971 arm
->full_context
= arm_dpm_full_context
;
972 arm
->read_core_reg
= arm_dpm_read_core_reg
;
973 arm
->write_core_reg
= arm_dpm_write_core_reg
;
975 cache
= arm_build_reg_cache(target
, arm
);
979 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
981 /* coprocessor access setup */
985 /* breakpoint setup -- optional until it works everywhere */
986 if (!target
->type
->add_breakpoint
) {
987 target
->type
->add_breakpoint
= dpm_add_breakpoint
;
988 target
->type
->remove_breakpoint
= dpm_remove_breakpoint
;
991 /* watchpoint setup */
992 target
->type
->add_watchpoint
= dpm_add_watchpoint
;
993 target
->type
->remove_watchpoint
= dpm_remove_watchpoint
;
995 /* FIXME add vector catch support */
997 dpm
->nbp
= 1 + ((dpm
->didr
>> 24) & 0xf);
998 dpm
->dbp
= calloc(dpm
->nbp
, sizeof *dpm
->dbp
);
1000 dpm
->nwp
= 1 + ((dpm
->didr
>> 28) & 0xf);
1001 dpm
->dwp
= calloc(dpm
->nwp
, sizeof *dpm
->dwp
);
1003 if (!dpm
->dbp
|| !dpm
->dwp
) {
1009 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1010 target_name(target
), dpm
->nbp
, dpm
->nwp
);
1012 /* REVISIT ... and some of those breakpoints could match
1013 * execution context IDs...
1020 * Reinitializes DPM state at the beginning of a new debug session
1021 * or after a reset which may have affected the debug module.
1023 int arm_dpm_initialize(struct arm_dpm
*dpm
)
1025 /* Disable all breakpoints and watchpoints at startup. */
1026 if (dpm
->bpwp_disable
) {
1029 for (i
= 0; i
< dpm
->nbp
; i
++) {
1030 dpm
->dbp
[i
].bpwp
.number
= i
;
1031 (void) dpm
->bpwp_disable(dpm
, i
);
1033 for (i
= 0; i
< dpm
->nwp
; i
++) {
1034 dpm
->dwp
[i
].bpwp
.number
= 16 + i
;
1035 (void) dpm
->bpwp_disable(dpm
, 16 + i
);
1038 LOG_WARNING("%s: can't disable breakpoints and watchpoints",
1039 target_name(dpm
->arm
->target
));
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