55f253e464ff95e730541939b8d44de1d03d2021
[openocd.git] / src / target / arm_dpm.c
1 /*
2 * Copyright (C) 2009 by David Brownell
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #ifdef HAVE_CONFIG_H
19 #include "config.h"
20 #endif
21
22 #include "arm.h"
23 #include "arm_dpm.h"
24 #include <jtag/jtag.h>
25 #include "register.h"
26 #include "breakpoints.h"
27 #include "target_type.h"
28 #include "arm_opcodes.h"
29
30
31 /**
32 * @file
33 * Implements various ARM DPM operations using architectural debug registers.
34 * These routines layer over core-specific communication methods to cope with
35 * implementation differences between cores like ARM1136 and Cortex-A8.
36 *
37 * The "Debug Programmers' Model" (DPM) for ARMv6 and ARMv7 is defined by
38 * Part C (Debug Architecture) of the ARM Architecture Reference Manual,
39 * ARMv7-A and ARMv7-R edition (ARM DDI 0406B). In OpenOCD, DPM operations
40 * are abstracted through internal programming interfaces to share code and
41 * to minimize needless differences in debug behavior between cores.
42 */
43
44 /*----------------------------------------------------------------------*/
45
46 /*
47 * Coprocessor support
48 */
49
50 /* Read coprocessor */
51 static int dpm_mrc(struct target *target, int cpnum,
52 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
53 uint32_t *value)
54 {
55 struct arm *arm = target_to_arm(target);
56 struct arm_dpm *dpm = arm->dpm;
57 int retval;
58
59 retval = dpm->prepare(dpm);
60 if (retval != ERROR_OK)
61 return retval;
62
63 LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
64 (int) op1, (int) CRn,
65 (int) CRm, (int) op2);
66
67 /* read coprocessor register into R0; return via DCC */
68 retval = dpm->instr_read_data_r0(dpm,
69 ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
70 value);
71
72 /* (void) */ dpm->finish(dpm);
73 return retval;
74 }
75
76 static int dpm_mcr(struct target *target, int cpnum,
77 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
78 uint32_t value)
79 {
80 struct arm *arm = target_to_arm(target);
81 struct arm_dpm *dpm = arm->dpm;
82 int retval;
83
84 retval = dpm->prepare(dpm);
85 if (retval != ERROR_OK)
86 return retval;
87
88 LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
89 (int) op1, (int) CRn,
90 (int) CRm, (int) op2);
91
92 /* read DCC into r0; then write coprocessor register from R0 */
93 retval = dpm->instr_write_data_r0(dpm,
94 ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
95 value);
96
97 /* (void) */ dpm->finish(dpm);
98 return retval;
99 }
100
101 /*----------------------------------------------------------------------*/
102
103 /*
104 * Register access utilities
105 */
106
107 /* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
108 * Routines *must* restore the original mode before returning!!
109 */
110 int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
111 {
112 int retval;
113 uint32_t cpsr;
114
115 /* restore previous mode */
116 if (mode == ARM_MODE_ANY)
117 cpsr = buf_get_u32(dpm->arm->cpsr->value, 0, 32);
118
119 /* else force to the specified mode */
120 else
121 cpsr = mode;
122
123 retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr);
124 if (retval != ERROR_OK)
125 return retval;
126
127 if (dpm->instr_cpsr_sync)
128 retval = dpm->instr_cpsr_sync(dpm);
129
130 return retval;
131 }
132
133
134 static int dpm_read_reg32(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
135 {
136 uint32_t value;
137 int retval = ERROR_FAIL;
138
139 switch (regnum) {
140 case 0 ... 14:
141 /* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
142 retval = dpm->instr_read_data_dcc(dpm,
143 ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
144 &value);
145 break;
146 case 15:/* PC
147 * "MOV r0, pc"; then return via DCC */
148 retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value);
149
150 /* NOTE: this seems like a slightly awkward place to update
151 * this value ... but if the PC gets written (the only way
152 * to change what we compute), the arch spec says subsequent
153 * reads return values which are "unpredictable". So this
154 * is always right except in those broken-by-intent cases.
155 */
156 switch (dpm->arm->core_state) {
157 case ARM_STATE_ARM:
158 value -= 8;
159 break;
160 case ARM_STATE_THUMB:
161 case ARM_STATE_THUMB_EE:
162 value -= 4;
163 break;
164 case ARM_STATE_JAZELLE:
165 /* core-specific ... ? */
166 LOG_WARNING("Jazelle PC adjustment unknown");
167 break;
168 case ARM_STATE_AARCH64:
169 LOG_ERROR("AARCH64: 32bit read requested");
170 break;
171 }
172 break;
173 default:
174 /* 16: "MRS r0, CPSR"; then return via DCC
175 * 17: "MRS r0, SPSR"; then return via DCC
176 */
177 retval = dpm->instr_read_data_r0(dpm,
178 ARMV4_5_MRS(0, regnum & 1),
179 &value);
180 break;
181 }
182
183 if (retval == ERROR_OK) {
184 buf_set_u32(r->value, 0, 32, value);
185 r->valid = true;
186 r->dirty = false;
187 LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned) value);
188 }
189
190 return retval;
191 }
192
193 static int dpm_read_reg64(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
194 {
195 uint64_t value;
196 uint32_t i;
197 int retval = ERROR_FAIL;
198
199 switch (regnum) {
200 case 0 ... 30:
201 i = 0xd5130400 + regnum; /* msr dbgdtr_el0,reg */
202 retval = dpm->instr_read_data_dcc_64(dpm, i, &value);
203 break;
204 case 31: /* SP */
205 i = 0x910003e0;
206 retval = dpm->instr_read_data_r0_64(dpm, i, &value);
207 break;
208 case 32: /* PC */
209 i = 0xd53b4520;
210 retval = dpm->instr_read_data_r0_64(dpm, i, &value);
211 break;
212 case 33: /* CPSR */
213 i = 0xd53b4500;
214 retval = dpm->instr_read_data_r0_64(dpm, i, &value);
215 break;
216
217 default:
218 break;
219 }
220
221 if (retval == ERROR_OK) {
222 buf_set_u64(r->value, 0, 64, value);
223 r->valid = true;
224 r->dirty = false;
225 LOG_DEBUG("READ: %s, %16.16llx", r->name, (long long)value);
226 }
227
228 return retval;
229 }
230
231
232 /* just read the register -- rely on the core mode being right */
233 static int dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
234 {
235 if (r->size == 64)
236 return dpm_read_reg64(dpm, r, regnum);
237 else
238 return dpm_read_reg32(dpm, r, regnum);
239 }
240
241 static int dpm_write_reg32(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
242 {
243 int retval = ERROR_FAIL;
244 uint32_t value = buf_get_u32(r->value, 0, 32);
245
246 switch (regnum) {
247 case 0 ... 14:
248 /* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */
249 retval = dpm->instr_write_data_dcc(dpm,
250 ARMV4_5_MRC(14, 0, regnum, 0, 5, 0),
251 value);
252 break;
253 case 15:/* PC
254 * read r0 from DCC; then "MOV pc, r0" */
255 retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value);
256 break;
257 default:
258 /* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf"
259 * 17: read r0 from DCC, then "MSR r0, SPSR_cxsf"
260 */
261 retval = dpm->instr_write_data_r0(dpm,
262 ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
263 value);
264 if (retval != ERROR_OK)
265 return retval;
266
267 if (regnum == 16 && dpm->instr_cpsr_sync)
268 retval = dpm->instr_cpsr_sync(dpm);
269
270 break;
271 }
272
273 if (retval == ERROR_OK) {
274 r->dirty = false;
275 LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned) value);
276 }
277
278 return retval;
279 }
280
281 /**
282 * Write to program counter and switch the core state (arm/thumb) according to
283 * the address.
284 */
285 static int dpm_write_pc_core_state(struct arm_dpm *dpm, struct reg *r)
286 {
287 uint32_t value = buf_get_u32(r->value, 0, 32);
288
289 /* read r0 from DCC; then "BX r0" */
290 return dpm->instr_write_data_r0(dpm, ARMV4_5_BX(0), value);
291 }
292
293 static int dpm_write_reg64(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
294 {
295 int retval = ERROR_FAIL;
296 uint32_t i;
297 uint64_t value = buf_get_u64(r->value, 0, 64);
298
299 switch (regnum) {
300 case 0 ... 30:
301 i = 0xd5330400 + regnum;
302 retval = dpm->instr_write_data_dcc_64(dpm, i, value);
303 break;
304 case 32: /* PC */
305 i = 0xd51b4520;
306 retval = dpm->instr_write_data_r0_64(dpm, i, value);
307 break;
308 default:
309 LOG_DEBUG("register %s (%16.16llx) not defined", r->name,
310 (unsigned long long)value);
311 break;
312 }
313
314 if (retval == ERROR_OK) {
315 r->dirty = false;
316 LOG_DEBUG("WRITE: %s, %16.16llx", r->name, (unsigned long long)value);
317 }
318
319 return retval;
320 }
321
322 /* just write the register -- rely on the core mode being right */
323 static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
324 {
325 if (r->size == 64)
326 return dpm_write_reg64(dpm, r, regnum);
327 else
328 return dpm_write_reg32(dpm, r, regnum);
329 }
330
331 static int arm_dpm_read_current_registers_i(struct arm_dpm *dpm)
332 {
333 struct arm *arm = dpm->arm;
334 uint32_t cpsr, instr, core_regs;
335 int retval;
336 struct reg *r;
337 enum arm_state core_state = arm->core_state;
338
339 retval = dpm->prepare(dpm);
340 if (retval != ERROR_OK)
341 return retval;
342
343 /* read R0 first (it's used for scratch), then CPSR */
344 r = arm->core_cache->reg_list + 0;
345 if (!r->valid) {
346 retval = dpm_read_reg(dpm, r, 0);
347 if (retval != ERROR_OK)
348 goto fail;
349 }
350 r->dirty = true;
351
352 if (core_state == ARM_STATE_AARCH64)
353 instr = 0xd53b4500; /* mrs x0, dspsr_el0 */
354 else
355 instr = ARMV4_5_MRS(0, 0);
356 retval = dpm->instr_read_data_r0(dpm, instr, &cpsr);
357 if (retval != ERROR_OK)
358 goto fail;
359
360 /* update core mode and state, plus shadow mapping for R8..R14 */
361 arm_set_cpsr(arm, cpsr);
362 if (core_state == ARM_STATE_AARCH64)
363 /* arm_set_cpsr changes core_state, restore it for now */
364 arm->core_state = ARM_STATE_AARCH64;
365
366 core_regs = arm->core_cache->num_regs;
367
368 /* REVISIT we can probably avoid reading R1..R14, saving time... */
369 for (unsigned i = 1; i < core_regs; i++) {
370 r = dpm->arm_reg_current(arm, i);
371 if (r->valid)
372 continue;
373
374 retval = dpm_read_reg(dpm, r, i);
375 if (retval != ERROR_OK)
376 goto fail;
377 }
378
379 /* NOTE: SPSR ignored (if it's even relevant). */
380
381 /* REVISIT the debugger can trigger various exceptions. See the
382 * ARMv7A architecture spec, section C5.7, for more info about
383 * what defenses are needed; v6 debug has the most issues.
384 */
385
386 fail:
387 /* (void) */ dpm->finish(dpm);
388 return retval;
389 }
390
391 /**
392 * Read basic registers of the the current context: R0 to R15, and CPSR;
393 * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
394 * In normal operation this is called on entry to halting debug state,
395 * possibly after some other operations supporting restore of debug state
396 * or making sure the CPU is fully idle (drain write buffer, etc).
397 */
398 int arm_dpm_read_current_registers(struct arm_dpm *dpm)
399 {
400 return arm_dpm_read_current_registers_i(dpm);
401 }
402
403 int arm_dpm_read_current_registers_64(struct arm_dpm *dpm)
404 {
405 return arm_dpm_read_current_registers_i(dpm);
406 }
407
408 /* Avoid needless I/O ... leave breakpoints and watchpoints alone
409 * unless they're removed, or need updating because of single-stepping
410 * or running debugger code.
411 */
412 static int dpm_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp,
413 struct dpm_bpwp *xp, int *set_p)
414 {
415 int retval = ERROR_OK;
416 bool disable;
417
418 if (!set_p) {
419 if (!xp->dirty)
420 goto done;
421 xp->dirty = false;
422 /* removed or startup; we must disable it */
423 disable = true;
424 } else if (bpwp) {
425 if (!xp->dirty)
426 goto done;
427 /* disabled, but we must set it */
428 xp->dirty = disable = false;
429 *set_p = true;
430 } else {
431 if (!*set_p)
432 goto done;
433 /* set, but we must temporarily disable it */
434 xp->dirty = disable = true;
435 *set_p = false;
436 }
437
438 if (disable)
439 retval = dpm->bpwp_disable(dpm, xp->number);
440 else
441 retval = dpm->bpwp_enable(dpm, xp->number,
442 xp->address, xp->control);
443
444 if (retval != ERROR_OK)
445 LOG_ERROR("%s: can't %s HW %spoint %d",
446 disable ? "disable" : "enable",
447 target_name(dpm->arm->target),
448 (xp->number < 16) ? "break" : "watch",
449 xp->number & 0xf);
450 done:
451 return retval;
452 }
453
454 static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp);
455
456
457 static int arm_dpm_write_dirty_registers_32(struct arm_dpm *dpm)
458 {
459 struct arm *arm = dpm->arm;
460 struct reg_cache *cache = arm->core_cache;
461 int retval;
462 bool did_write;
463
464 /* Scan the registers until we find one that's both dirty and
465 * eligible for flushing. Flush that and everything else that
466 * shares the same core mode setting. Typically this won't
467 * actually find anything to do...
468 */
469 do {
470 enum arm_mode mode = ARM_MODE_ANY;
471
472 did_write = false;
473
474 /* check everything except our scratch register R0 */
475 for (unsigned i = 1; i < cache->num_regs; i++) {
476 struct arm_reg *r;
477 unsigned regnum;
478
479 /* also skip PC, CPSR, and non-dirty */
480 if (i == 15)
481 continue;
482 if (arm->cpsr == cache->reg_list + i)
483 continue;
484 if (!cache->reg_list[i].dirty)
485 continue;
486
487 r = cache->reg_list[i].arch_info;
488 regnum = r->num;
489
490 /* may need to pick and set a mode */
491 if (!did_write) {
492 enum arm_mode tmode;
493
494 did_write = true;
495 mode = tmode = r->mode;
496
497 /* cope with special cases */
498 switch (regnum) {
499 case 8 ... 12:
500 /* r8..r12 "anything but FIQ" case;
501 * we "know" core mode is accurate
502 * since we haven't changed it yet
503 */
504 if (arm->core_mode == ARM_MODE_FIQ
505 && ARM_MODE_ANY
506 != mode)
507 tmode = ARM_MODE_USR;
508 break;
509 case 16:
510 /* SPSR */
511 regnum++;
512 break;
513 }
514
515 /* REVISIT error checks */
516 if (tmode != ARM_MODE_ANY) {
517 retval = dpm_modeswitch(dpm, tmode);
518 if (retval != ERROR_OK)
519 goto done;
520 }
521 }
522 if (r->mode != mode)
523 continue;
524
525 retval = dpm_write_reg(dpm,
526 &cache->reg_list[i],
527 regnum);
528 if (retval != ERROR_OK)
529 goto done;
530 }
531
532 } while (did_write);
533
534 /* Restore original CPSR ... assuming either that we changed it,
535 * or it's dirty. Must write PC to ensure the return address is
536 * defined, and must not write it before CPSR.
537 */
538 retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
539 if (retval != ERROR_OK)
540 goto done;
541 arm->cpsr->dirty = false;
542
543 /* restore the PC, make sure to also switch the core state
544 * to whatever it was set to with "arm core_state" command.
545 * target code will have set PC to an appropriate resume address.
546 */
547 retval = dpm_write_pc_core_state(dpm, arm->pc);
548 if (retval != ERROR_OK)
549 goto done;
550 /* on Cortex-A5 (as found on NXP VF610 SoC), BX instruction
551 * executed in debug state doesn't appear to set the PC,
552 * explicitly set it with a "MOV pc, r0". This doesn't influence
553 * CPSR on Cortex-A9 so it should be OK. Maybe due to different
554 * debug version?
555 */
556 retval = dpm_write_reg(dpm, arm->pc, 15);
557 if (retval != ERROR_OK)
558 goto done;
559 arm->pc->dirty = false;
560
561 /* flush R0 -- it's *very* dirty by now */
562 retval = dpm_write_reg(dpm, &cache->reg_list[0], 0);
563 if (retval != ERROR_OK)
564 goto done;
565 cache->reg_list[0].dirty = false;
566
567 done:
568 return retval;
569 }
570
571 static int arm_dpm_write_dirty_registers_64(struct arm_dpm *dpm)
572 {
573 struct arm *arm = dpm->arm;
574 struct reg_cache *cache = arm->core_cache;
575 int retval;
576
577 /* Scan the registers until we find one that's both dirty and
578 * eligible for flushing. Flush that and everything else that
579 * shares the same core mode setting. Typically this won't
580 * actually find anything to do...
581 */
582
583 /* check everything except our scratch register R0 */
584 for (unsigned i = 1; i <= 32; i++) {
585 struct arm_reg *r;
586 unsigned regnum;
587
588 if (!cache->reg_list[i].dirty)
589 continue;
590
591 r = cache->reg_list[i].arch_info;
592 regnum = r->num;
593 retval = dpm_write_reg(dpm,
594 &cache->reg_list[i],
595 regnum);
596 if (retval != ERROR_OK)
597 goto done;
598 }
599
600 /* flush R0 -- it's *very* dirty by now */
601 retval = dpm_write_reg(dpm, &cache->reg_list[0], 0);
602 if (retval != ERROR_OK)
603 goto done;
604 cache->reg_list[0].dirty = false;
605
606 done:
607 return retval;
608 }
609
610 /**
611 * Writes all modified core registers for all processor modes. In normal
612 * operation this is called on exit from halting debug state.
613 *
614 * @param dpm: represents the processor
615 * @param bpwp: true ensures breakpoints and watchpoints are set,
616 * false ensures they are cleared
617 */
618 int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
619 {
620 struct arm *arm = dpm->arm;
621 struct reg_cache *cache = arm->core_cache;
622 int retval;
623
624 retval = dpm->prepare(dpm);
625 if (retval != ERROR_OK)
626 goto done;
627
628 /* If we're managing hardware breakpoints for this core, enable
629 * or disable them as requested.
630 *
631 * REVISIT We don't yet manage them for ANY cores. Eventually
632 * we should be able to assume we handle them; but until then,
633 * cope with the hand-crafted breakpoint code.
634 */
635 if (arm->target->type->add_breakpoint == dpm_add_breakpoint) {
636 for (unsigned i = 0; i < dpm->nbp; i++) {
637 struct dpm_bp *dbp = dpm->dbp + i;
638 struct breakpoint *bp = dbp->bp;
639
640 retval = dpm_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp,
641 bp ? &bp->set : NULL);
642 if (retval != ERROR_OK)
643 goto done;
644 }
645 }
646
647 /* enable/disable watchpoints */
648 for (unsigned i = 0; i < dpm->nwp; i++) {
649 struct dpm_wp *dwp = dpm->dwp + i;
650 struct watchpoint *wp = dwp->wp;
651
652 retval = dpm_maybe_update_bpwp(dpm, bpwp, &dwp->bpwp,
653 wp ? &wp->set : NULL);
654 if (retval != ERROR_OK)
655 goto done;
656 }
657
658 /* NOTE: writes to breakpoint and watchpoint registers might
659 * be queued, and need (efficient/batched) flushing later.
660 */
661
662 if (cache->reg_list[0].size == 64)
663 retval = arm_dpm_write_dirty_registers_64(dpm);
664 else
665 retval = arm_dpm_write_dirty_registers_32(dpm);
666
667 /* (void) */ dpm->finish(dpm);
668 done:
669 return retval;
670 }
671
672 /* Returns ARM_MODE_ANY or temporary mode to use while reading the
673 * specified register ... works around flakiness from ARM core calls.
674 * Caller already filtered out SPSR access; mode is never MODE_SYS
675 * or MODE_ANY.
676 */
677 static enum arm_mode dpm_mapmode(struct arm *arm,
678 unsigned num, enum arm_mode mode)
679 {
680 enum arm_mode amode = arm->core_mode;
681
682 /* don't switch if the mode is already correct */
683 if (amode == ARM_MODE_SYS)
684 amode = ARM_MODE_USR;
685 if (mode == amode)
686 return ARM_MODE_ANY;
687
688 switch (num) {
689 /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */
690 case 0 ... 7:
691 case 15:
692 case 16:
693 break;
694 /* r8..r12 aren't shadowed for anything except FIQ */
695 case 8 ... 12:
696 if (mode == ARM_MODE_FIQ)
697 return mode;
698 break;
699 /* r13/sp, and r14/lr are always shadowed */
700 case 13:
701 case 14:
702 return mode;
703 default:
704 LOG_WARNING("invalid register #%u", num);
705 break;
706 }
707 return ARM_MODE_ANY;
708 }
709
710
711 /*
712 * Standard ARM register accessors ... there are three methods
713 * in "struct arm", to support individual read/write and bulk read
714 * of registers.
715 */
716
717 static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
718 int regnum, enum arm_mode mode)
719 {
720 struct arm_dpm *dpm = target_to_arm(target)->dpm;
721 int retval;
722
723 if (regnum < 0 || regnum > 16)
724 return ERROR_COMMAND_SYNTAX_ERROR;
725
726 if (regnum == 16) {
727 if (mode != ARM_MODE_ANY)
728 regnum = 17;
729 } else
730 mode = dpm_mapmode(dpm->arm, regnum, mode);
731
732 /* REVISIT what happens if we try to read SPSR in a core mode
733 * which has no such register?
734 */
735
736 retval = dpm->prepare(dpm);
737 if (retval != ERROR_OK)
738 return retval;
739
740 if (mode != ARM_MODE_ANY) {
741 retval = dpm_modeswitch(dpm, mode);
742 if (retval != ERROR_OK)
743 goto fail;
744 }
745
746 retval = dpm_read_reg(dpm, r, regnum);
747 if (retval != ERROR_OK)
748 goto fail;
749 /* always clean up, regardless of error */
750
751 if (mode != ARM_MODE_ANY)
752 /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
753
754 fail:
755 /* (void) */ dpm->finish(dpm);
756 return retval;
757 }
758
759 static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
760 int regnum, enum arm_mode mode, uint8_t *value)
761 {
762 struct arm_dpm *dpm = target_to_arm(target)->dpm;
763 int retval;
764
765
766 if (regnum < 0 || regnum > 16)
767 return ERROR_COMMAND_SYNTAX_ERROR;
768
769 if (regnum == 16) {
770 if (mode != ARM_MODE_ANY)
771 regnum = 17;
772 } else
773 mode = dpm_mapmode(dpm->arm, regnum, mode);
774
775 /* REVISIT what happens if we try to write SPSR in a core mode
776 * which has no such register?
777 */
778
779 retval = dpm->prepare(dpm);
780 if (retval != ERROR_OK)
781 return retval;
782
783 if (mode != ARM_MODE_ANY) {
784 retval = dpm_modeswitch(dpm, mode);
785 if (retval != ERROR_OK)
786 goto fail;
787 }
788
789 retval = dpm_write_reg(dpm, r, regnum);
790 /* always clean up, regardless of error */
791
792 if (mode != ARM_MODE_ANY)
793 /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
794
795 fail:
796 /* (void) */ dpm->finish(dpm);
797 return retval;
798 }
799
800 static int arm_dpm_full_context(struct target *target)
801 {
802 struct arm *arm = target_to_arm(target);
803 struct arm_dpm *dpm = arm->dpm;
804 struct reg_cache *cache = arm->core_cache;
805 int retval;
806 bool did_read;
807
808 retval = dpm->prepare(dpm);
809 if (retval != ERROR_OK)
810 goto done;
811
812 do {
813 enum arm_mode mode = ARM_MODE_ANY;
814
815 did_read = false;
816
817 /* We "know" arm_dpm_read_current_registers() was called so
818 * the unmapped registers (R0..R7, PC, AND CPSR) and some
819 * view of R8..R14 are current. We also "know" oddities of
820 * register mapping: special cases for R8..R12 and SPSR.
821 *
822 * Pick some mode with unread registers and read them all.
823 * Repeat until done.
824 */
825 for (unsigned i = 0; i < cache->num_regs; i++) {
826 struct arm_reg *r;
827
828 if (cache->reg_list[i].valid)
829 continue;
830 r = cache->reg_list[i].arch_info;
831
832 /* may need to pick a mode and set CPSR */
833 if (!did_read) {
834 did_read = true;
835 mode = r->mode;
836
837 /* For regular (ARM_MODE_ANY) R8..R12
838 * in case we've entered debug state
839 * in FIQ mode we need to patch mode.
840 */
841 if (mode != ARM_MODE_ANY)
842 retval = dpm_modeswitch(dpm, mode);
843 else
844 retval = dpm_modeswitch(dpm, ARM_MODE_USR);
845
846 if (retval != ERROR_OK)
847 goto done;
848 }
849 if (r->mode != mode)
850 continue;
851
852 /* CPSR was read, so "R16" must mean SPSR */
853 retval = dpm_read_reg(dpm,
854 &cache->reg_list[i],
855 (r->num == 16) ? 17 : r->num);
856 if (retval != ERROR_OK)
857 goto done;
858 }
859
860 } while (did_read);
861
862 retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
863 /* (void) */ dpm->finish(dpm);
864 done:
865 return retval;
866 }
867
868
869 /*----------------------------------------------------------------------*/
870
871 /*
872 * Breakpoint and Watchpoint support.
873 *
874 * Hardware {break,watch}points are usually left active, to minimize
875 * debug entry/exit costs. When they are set or cleared, it's done in
876 * batches. Also, DPM-conformant hardware can update debug registers
877 * regardless of whether the CPU is running or halted ... though that
878 * fact isn't currently leveraged.
879 */
880
881 static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp,
882 uint32_t addr, uint32_t length)
883 {
884 uint32_t control;
885
886 control = (1 << 0) /* enable */
887 | (3 << 1); /* both user and privileged access */
888
889 /* Match 1, 2, or all 4 byte addresses in this word.
890 *
891 * FIXME: v7 hardware allows lengths up to 2 GB for BP and WP.
892 * Support larger length, when addr is suitably aligned. In
893 * particular, allow watchpoints on 8 byte "double" values.
894 *
895 * REVISIT allow watchpoints on unaligned 2-bit values; and on
896 * v7 hardware, unaligned 4-byte ones too.
897 */
898 switch (length) {
899 case 1:
900 control |= (1 << (addr & 3)) << 5;
901 break;
902 case 2:
903 /* require 2-byte alignment */
904 if (!(addr & 1)) {
905 control |= (3 << (addr & 2)) << 5;
906 break;
907 }
908 /* FALL THROUGH */
909 case 4:
910 /* require 4-byte alignment */
911 if (!(addr & 3)) {
912 control |= 0xf << 5;
913 break;
914 }
915 /* FALL THROUGH */
916 default:
917 LOG_ERROR("unsupported {break,watch}point length/alignment");
918 return ERROR_COMMAND_SYNTAX_ERROR;
919 }
920
921 /* other shared control bits:
922 * bits 15:14 == 0 ... both secure and nonsecure states (v6.1+ only)
923 * bit 20 == 0 ... not linked to a context ID
924 * bit 28:24 == 0 ... not ignoring N LSBs (v7 only)
925 */
926
927 xp->address = addr & ~3;
928 xp->control = control;
929 xp->dirty = true;
930
931 LOG_DEBUG("BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d",
932 xp->address, control, xp->number);
933
934 /* hardware is updated in write_dirty_registers() */
935 return ERROR_OK;
936 }
937
938 static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp)
939 {
940 struct arm *arm = target_to_arm(target);
941 struct arm_dpm *dpm = arm->dpm;
942 int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
943
944 if (bp->length < 2)
945 return ERROR_COMMAND_SYNTAX_ERROR;
946 if (!dpm->bpwp_enable)
947 return retval;
948
949 /* FIXME we need a generic solution for software breakpoints. */
950 if (bp->type == BKPT_SOFT)
951 LOG_DEBUG("using HW bkpt, not SW...");
952
953 for (unsigned i = 0; i < dpm->nbp; i++) {
954 if (!dpm->dbp[i].bp) {
955 retval = dpm_bpwp_setup(dpm, &dpm->dbp[i].bpwp,
956 bp->address, bp->length);
957 if (retval == ERROR_OK)
958 dpm->dbp[i].bp = bp;
959 break;
960 }
961 }
962
963 return retval;
964 }
965
966 static int dpm_remove_breakpoint(struct target *target, struct breakpoint *bp)
967 {
968 struct arm *arm = target_to_arm(target);
969 struct arm_dpm *dpm = arm->dpm;
970 int retval = ERROR_COMMAND_SYNTAX_ERROR;
971
972 for (unsigned i = 0; i < dpm->nbp; i++) {
973 if (dpm->dbp[i].bp == bp) {
974 dpm->dbp[i].bp = NULL;
975 dpm->dbp[i].bpwp.dirty = true;
976
977 /* hardware is updated in write_dirty_registers() */
978 retval = ERROR_OK;
979 break;
980 }
981 }
982
983 return retval;
984 }
985
986 static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t,
987 struct watchpoint *wp)
988 {
989 int retval;
990 struct dpm_wp *dwp = dpm->dwp + index_t;
991 uint32_t control;
992
993 /* this hardware doesn't support data value matching or masking */
994 if (wp->value || wp->mask != ~(uint32_t)0) {
995 LOG_DEBUG("watchpoint values and masking not supported");
996 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
997 }
998
999 retval = dpm_bpwp_setup(dpm, &dwp->bpwp, wp->address, wp->length);
1000 if (retval != ERROR_OK)
1001 return retval;
1002
1003 control = dwp->bpwp.control;
1004 switch (wp->rw) {
1005 case WPT_READ:
1006 control |= 1 << 3;
1007 break;
1008 case WPT_WRITE:
1009 control |= 2 << 3;
1010 break;
1011 case WPT_ACCESS:
1012 control |= 3 << 3;
1013 break;
1014 }
1015 dwp->bpwp.control = control;
1016
1017 dpm->dwp[index_t].wp = wp;
1018
1019 return retval;
1020 }
1021
1022 static int dpm_add_watchpoint(struct target *target, struct watchpoint *wp)
1023 {
1024 struct arm *arm = target_to_arm(target);
1025 struct arm_dpm *dpm = arm->dpm;
1026 int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1027
1028 if (dpm->bpwp_enable) {
1029 for (unsigned i = 0; i < dpm->nwp; i++) {
1030 if (!dpm->dwp[i].wp) {
1031 retval = dpm_watchpoint_setup(dpm, i, wp);
1032 break;
1033 }
1034 }
1035 }
1036
1037 return retval;
1038 }
1039
1040 static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp)
1041 {
1042 struct arm *arm = target_to_arm(target);
1043 struct arm_dpm *dpm = arm->dpm;
1044 int retval = ERROR_COMMAND_SYNTAX_ERROR;
1045
1046 for (unsigned i = 0; i < dpm->nwp; i++) {
1047 if (dpm->dwp[i].wp == wp) {
1048 dpm->dwp[i].wp = NULL;
1049 dpm->dwp[i].bpwp.dirty = true;
1050
1051 /* hardware is updated in write_dirty_registers() */
1052 retval = ERROR_OK;
1053 break;
1054 }
1055 }
1056
1057 return retval;
1058 }
1059
1060 void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
1061 {
1062 switch (dpm->arm->core_state) {
1063 case ARM_STATE_ARM:
1064 addr -= 8;
1065 break;
1066 case ARM_STATE_THUMB:
1067 case ARM_STATE_THUMB_EE:
1068 addr -= 4;
1069 break;
1070 case ARM_STATE_JAZELLE:
1071 case ARM_STATE_AARCH64:
1072 /* ?? */
1073 break;
1074 }
1075 dpm->wp_pc = addr;
1076 }
1077
1078 /*----------------------------------------------------------------------*/
1079
1080 /*
1081 * Other debug and support utilities
1082 */
1083
1084 void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
1085 {
1086 struct target *target = dpm->arm->target;
1087
1088 dpm->dscr = dscr;
1089
1090 /* Examine debug reason */
1091 switch (DSCR_ENTRY(dscr)) {
1092 case 6: /* Data abort (v6 only) */
1093 case 7: /* Prefetch abort (v6 only) */
1094 /* FALL THROUGH -- assume a v6 core in abort mode */
1095 case 0: /* HALT request from debugger */
1096 case 4: /* EDBGRQ */
1097 target->debug_reason = DBG_REASON_DBGRQ;
1098 break;
1099 case 1: /* HW breakpoint */
1100 case 3: /* SW BKPT */
1101 case 5: /* vector catch */
1102 target->debug_reason = DBG_REASON_BREAKPOINT;
1103 break;
1104 case 2: /* asynch watchpoint */
1105 case 10:/* precise watchpoint */
1106 target->debug_reason = DBG_REASON_WATCHPOINT;
1107 break;
1108 default:
1109 target->debug_reason = DBG_REASON_UNDEFINED;
1110 break;
1111 }
1112 }
1113
1114 /*----------------------------------------------------------------------*/
1115
1116 /*
1117 * Setup and management support.
1118 */
1119
1120 /**
1121 * Hooks up this DPM to its associated target; call only once.
1122 * Initially this only covers the register cache.
1123 *
1124 * Oh, and watchpoints. Yeah.
1125 */
1126 int arm_dpm_setup(struct arm_dpm *dpm)
1127 {
1128 struct arm *arm = dpm->arm;
1129 struct target *target = arm->target;
1130 struct reg_cache *cache = 0;
1131
1132 arm->dpm = dpm;
1133
1134 /* register access setup */
1135 arm->full_context = arm_dpm_full_context;
1136 arm->read_core_reg = arm->read_core_reg ? : arm_dpm_read_core_reg;
1137 arm->write_core_reg = arm->write_core_reg ? : arm_dpm_write_core_reg;
1138
1139 if (arm->core_cache != NULL) {
1140 if (arm->core_state == ARM_STATE_AARCH64) {
1141 cache = armv8_build_reg_cache(target);
1142 target->reg_cache = cache;
1143 } else {
1144 cache = arm_build_reg_cache(target, arm);
1145 *register_get_last_cache_p(&target->reg_cache) = cache;
1146 }
1147
1148 if (!cache)
1149 return ERROR_FAIL;
1150 }
1151
1152 /* coprocessor access setup */
1153 arm->mrc = dpm_mrc;
1154 arm->mcr = dpm_mcr;
1155
1156 /* breakpoint setup -- optional until it works everywhere */
1157 if (!target->type->add_breakpoint) {
1158 target->type->add_breakpoint = dpm_add_breakpoint;
1159 target->type->remove_breakpoint = dpm_remove_breakpoint;
1160 }
1161
1162 /* watchpoint setup */
1163 target->type->add_watchpoint = dpm_add_watchpoint;
1164 target->type->remove_watchpoint = dpm_remove_watchpoint;
1165
1166
1167 if (dpm->arm_reg_current == 0)
1168 dpm->arm_reg_current = arm_reg_current;
1169
1170 /* FIXME add vector catch support */
1171
1172 if (arm->core_state == ARM_STATE_AARCH64) {
1173 dpm->nbp = 1 + ((dpm->didr >> 24) & 0xf);
1174 dpm->nwp = 1 + ((dpm->didr >> 28) & 0xf);
1175 } else {
1176 dpm->nbp = 1 + ((dpm->didr >> 12) & 0xf);
1177 dpm->nwp = 1 + ((dpm->didr >> 20) & 0xf);
1178 }
1179
1180 dpm->dbp = calloc(dpm->nbp, sizeof *dpm->dbp);
1181 dpm->dwp = calloc(dpm->nwp, sizeof *dpm->dwp);
1182
1183 if (!dpm->dbp || !dpm->dwp) {
1184 free(dpm->dbp);
1185 free(dpm->dwp);
1186 return ERROR_FAIL;
1187 }
1188
1189 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1190 target_name(target), dpm->nbp, dpm->nwp);
1191
1192 /* REVISIT ... and some of those breakpoints could match
1193 * execution context IDs...
1194 */
1195
1196 return ERROR_OK;
1197 }
1198
1199 /**
1200 * Reinitializes DPM state at the beginning of a new debug session
1201 * or after a reset which may have affected the debug module.
1202 */
1203 int arm_dpm_initialize(struct arm_dpm *dpm)
1204 {
1205 /* Disable all breakpoints and watchpoints at startup. */
1206 if (dpm->bpwp_disable) {
1207 unsigned i;
1208
1209 for (i = 0; i < dpm->nbp; i++) {
1210 dpm->dbp[i].bpwp.number = i;
1211 (void) dpm->bpwp_disable(dpm, i);
1212 }
1213 for (i = 0; i < dpm->nwp; i++) {
1214 dpm->dwp[i].bpwp.number = 16 + i;
1215 (void) dpm->bpwp_disable(dpm, 16 + i);
1216 }
1217 } else
1218 LOG_WARNING("%s: can't disable breakpoints and watchpoints",
1219 target_name(dpm->arm->target));
1220
1221 return ERROR_OK;
1222 }