bdfdb038cd78d6316e9deca38760e6434fa01955
[openocd.git] / src / target / arm_disassembler.h
1 /***************************************************************************
2 * Copyright (C) 2006 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20
21 #ifndef ARM_DISASSEMBLER_H
22 #define ARM_DISASSEMBLER_H
23
24 #include <helper/types.h>
25
26 enum arm_instruction_type {
27 ARM_UNKNOWN_INSTUCTION,
28
29 /* Branch instructions */
30 ARM_B,
31 ARM_BL,
32 ARM_BX,
33 ARM_BLX,
34
35 /* Data processing instructions */
36 ARM_AND,
37 ARM_EOR,
38 ARM_SUB,
39 ARM_RSB,
40 ARM_ADD,
41 ARM_ADC,
42 ARM_SBC,
43 ARM_RSC,
44 ARM_TST,
45 ARM_TEQ,
46 ARM_CMP,
47 ARM_CMN,
48 ARM_ORR,
49 ARM_MOV,
50 ARM_BIC,
51 ARM_MVN,
52
53 /* Load/store instructions */
54 ARM_LDR,
55 ARM_LDRB,
56 ARM_LDRT,
57 ARM_LDRBT,
58
59 ARM_LDRH,
60 ARM_LDRSB,
61 ARM_LDRSH,
62
63 ARM_LDM,
64
65 ARM_STR,
66 ARM_STRB,
67 ARM_STRT,
68 ARM_STRBT,
69
70 ARM_STRH,
71
72 ARM_STM,
73
74 /* Status register access instructions */
75 ARM_MRS,
76 ARM_MSR,
77
78 /* Multiply instructions */
79 ARM_MUL,
80 ARM_MLA,
81 ARM_SMULL,
82 ARM_SMLAL,
83 ARM_UMULL,
84 ARM_UMLAL,
85
86 /* Miscellaneous instructions */
87 ARM_CLZ,
88
89 /* Exception generating instructions */
90 ARM_BKPT,
91 ARM_SWI,
92
93 /* Coprocessor instructions */
94 ARM_CDP,
95 ARM_LDC,
96 ARM_STC,
97 ARM_MCR,
98 ARM_MRC,
99
100 /* Semaphore instructions */
101 ARM_SWP,
102 ARM_SWPB,
103
104 /* Enhanced DSP extensions */
105 ARM_MCRR,
106 ARM_MRRC,
107 ARM_PLD,
108 ARM_QADD,
109 ARM_QDADD,
110 ARM_QSUB,
111 ARM_QDSUB,
112 ARM_SMLAxy,
113 ARM_SMLALxy,
114 ARM_SMLAWy,
115 ARM_SMULxy,
116 ARM_SMULWy,
117 ARM_LDRD,
118 ARM_STRD,
119
120 ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
121 };
122
123 struct arm_b_bl_bx_blx_instr {
124 int reg_operand;
125 uint32_t target_address;
126 };
127
128 union arm_shifter_operand {
129 struct {
130 uint32_t immediate;
131 } immediate;
132 struct {
133 uint8_t Rm;
134 uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
135 uint8_t shift_imm;
136 } immediate_shift;
137 struct {
138 uint8_t Rm;
139 uint8_t shift;
140 uint8_t Rs;
141 } register_shift;
142 };
143
144 struct arm_data_proc_instr {
145 int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
146 uint8_t S;
147 uint8_t Rn;
148 uint8_t Rd;
149 union arm_shifter_operand shifter_operand;
150 };
151
152 struct arm_load_store_instr {
153 uint8_t Rd;
154 uint8_t Rn;
155 uint8_t U;
156 int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
157 int offset_mode; /* 0: immediate, 1: (scaled) register */
158 union {
159 uint32_t offset;
160 struct {
161 uint8_t Rm;
162 uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
163 uint8_t shift_imm;
164 } reg;
165 } offset;
166 };
167
168 struct arm_load_store_multiple_instr {
169 uint8_t Rn;
170 uint32_t register_list;
171 uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
172 uint8_t S;
173 uint8_t W;
174 };
175
176 struct arm_instruction {
177 enum arm_instruction_type type;
178 char text[128];
179 uint32_t opcode;
180
181 /* return value ... Thumb-2 sizes vary */
182 unsigned instruction_size;
183
184 union {
185 struct arm_b_bl_bx_blx_instr b_bl_bx_blx;
186 struct arm_data_proc_instr data_proc;
187 struct arm_load_store_instr load_store;
188 struct arm_load_store_multiple_instr load_store_multiple;
189 } info;
190
191 };
192
193 int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
194 struct arm_instruction *instruction);
195 int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
196 struct arm_instruction *instruction);
197 int thumb2_opcode(struct target *target, uint32_t address,
198 struct arm_instruction *instruction);
199 int arm_access_size(struct arm_instruction *instruction);
200
201 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])
202
203 #endif /* ARM_DISASSEMBLER_H */